A channel estimation method and system based on a storage-computing integrated device, a processing device and a storage medium

Abstract

The application relates to a channel estimation method and system based on a memory-computing integrated device, a processing device and a storage medium, which comprises the following steps: acquiring a pilot structure matrix and a probabilistic graph model of a to-be-tested channel estimation task, and determining the initial probability of the state value of each variable node in the probabilistic graph model according to a pilot signal observed by a receiving end and a variance and of channel uniform quantization; constructing a node state matrix corresponding to each undirected edge in the probabilistic graph model; constructing a driving vector corresponding to each undirected edge in the probabilistic graph model; performing memory-computing integrated device configuration based on the node state matrix corresponding to each undirected edge, so as to obtain a memory-computing integrated device subarray corresponding to each undirected edge; and determining a continuous channel estimation result in the to-be-tested channel estimation task according to the memory-computing integrated device subarray, the driving vector and the confidence of message transmission between each variable node and each check node connected through the undirected edge. The application can be widely used in the technical field of signal processing.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a channel estimation method, system, processing device, and storage medium based on a memory computing unit. Background Technology

[0002] With the full commercial deployment of fifth-generation mobile communication technology (5G), its three major application scenarios—enhanced mobile broadband (eMBB), ultra-reliable low-latency communication (uRLLC), and massive machine-type communication (mMTC)—have placed revolutionary demands on network speed, capacity, and latency. To meet these performance indicators, 5G has introduced key technologies including multiple-input multiple-output (MIMO), wider spectrum bandwidth (such as 100MHz and above), and higher frequency bands (such as millimeter waves). However, in the early stages of 5G commercialization, a particularly prominent problem has hindered user experience and further technological development: high power consumption and short standby time in 5G terminals. Compared to mature 4G terminals, 5G terminals consume significantly more power, becoming a core bottleneck restricting terminal battery life and product competitiveness.

[0003] The reasons for the dramatic increase in power consumption in 5G terminals are multifaceted and systemic. 5G terminals support more than five times the transmission bandwidth of 4G, and MIMO methods require terminals to have four times or more antenna paths. According to Shannon's formula for channel capacity, the increase in information transmission rate essentially stems from the increase in bandwidth and signal-to-noise ratio, which directly leads to a linear or even exponential increase in power consumption of modules such as the RF front-end and baseband processing. Studies show that, in terms of communication power consumption alone, 5G terminals are 50% to 100% higher than 4G terminals. This stacking of hardware capabilities places unprecedentedly stringent demands on the underlying signal processing algorithms. Taking channel estimation as a crucial step, in MIMO systems, the dimension of channel parameters that need to be estimated expands dramatically with the increase in the number of antennas and subcarriers. Existing classical estimation algorithms based on least squares (LS) or linear minimum mean square error (LMMSE) have computational complexity proportional to the square or even cube of the number of antennas, becoming a heavy burden on baseband processing units (such as DSPs and FPGAs), consuming a large amount of computing resources and time, directly translating into significant power consumption.

[0004] Therefore, there is an urgent need for a new channel estimation method and system that can significantly reduce the computational complexity of the algorithm without sacrificing estimation accuracy and communication performance, thereby fundamentally alleviating the power consumption pressure of 5G terminals, improving battery life, and laying the foundation for the popularization of 5G technology and the green and low-carbon design of the next generation of communication systems. Summary of the Invention

[0005] To address the aforementioned problems, the purpose of this invention is to provide a channel estimation method, system, processing device, and storage medium based on an in-memory computing unit, which can significantly reduce the computational complexity of the algorithm without sacrificing estimation accuracy and communication performance.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: Firstly, it provides a channel estimation method based on a memory computing device, comprising:

[0007] Obtain the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of the state value of each variable node in the probabilistic graphical model based on the pilot signal observed at the receiver, the variance of the channel uniform quantization and the noise variance.

[0008] For any check node in the probabilistic graphical model, construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model based on each undirected edge between the check node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver.

[0009] Based on the confidence level of each variable node in the probabilistic graphical model in passing its own state value to the verification node, the driving vector corresponding to each undirected edge in the probabilistic graphical model is constructed. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence level of the variable node in passing its own state value to each verification node connected by the undirected edge.

[0010] Based on the node state matrix corresponding to each undirected edge, the in-memory computing unit is configured to obtain the in-memory computing unit subarray corresponding to each undirected edge.

[0011] Based on the in-memory compute subarray corresponding to each undirected edge and the constructed driving vector, the confidence level of each verification node in the probabilistic graphical model when it transmits its own state value to the variable node is determined. Then, the confidence level of each variable node when it transmits its own state value to the verification node is updated until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task under test.

[0012] Secondly, a channel estimation system based on a memory computing unit is provided, including:

[0013] The acquisition unit is used to acquire the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and to determine the initial probability of the state value of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance.

[0014] The node state matrix construction unit is used to construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model for any verification node in the probabilistic graphical model, based on each undirected edge between the verification node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver.

[0015] The driving vector construction unit is used to construct the driving vector corresponding to each undirected edge in the probabilistic graphical model based on the confidence of each variable node in the probabilistic graphical model in passing its own state value to the verification node. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence of the variable node in passing its own state value to each verification node connected by the undirected edge.

[0016] The configuration unit is used to configure the in-memory computing unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory computing unit subarray corresponding to each undirected edge.

[0017] The estimation result determination unit is used to determine the confidence level of each verification node in the probabilistic graphical model to pass its own state value to the variable node based on the in-memory computing subarray corresponding to each undirected edge and the constructed driving vector. Then, it updates the confidence level of each variable node to pass its own state value to the verification node until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task under test.

[0018] Thirdly, a processing device is provided, including computer program instructions, wherein when the computer program instructions are executed by the processing device, they are used to implement the steps corresponding to the above-described channel estimation method based on in-memory computing.

[0019] Fourthly, a computer-readable storage medium is provided, wherein computer program instructions are stored on the computer-readable storage medium, wherein the computer program instructions, when executed by a processor, are used to implement the steps corresponding to the above-described channel estimation method based on a memory-computing device.

[0020] The present invention has the following advantages due to the adoption of the above technical solutions:

[0021] 1. This invention leverages the advantages of in-memory computing by loading static variables from the probabilistic graph iterative inference process into the in-memory computing device to overcome the energy overhead caused by storage access during the iteration process. At the same time, it utilizes Kirchhoff's circuit laws to transfer the discrete fixed-point number operations involved in the iteration process to the analog domain, breaking through the power consumption bottleneck of digital circuits. It can significantly reduce the computational complexity of the algorithm without sacrificing estimation accuracy and communication performance, and the estimation accuracy of the channel vector can approach the performance limit.

[0022] 2. This invention transfers the fixed-point arithmetic of traditional digital circuits to the analog domain, which can overcome the power consumption overhead caused by a large number of discrete fixed-point arithmetic operations and break through the power consumption bottleneck of digital circuits.

[0023] 3. Traditional digital MAC units consist of multipliers and adders, occupying a significant area, and each operation requires multiple memory accesses, three reads, and one write, resulting in substantial energy and latency overhead. In contrast, the in-memory compute unit based on a unified probabilistic graph in this invention completes matrix-vector multiplication in a single step, thereby significantly reducing the number of accesses and energy consumption.

[0024] 4. The present invention has a small area, occupying only a fraction of the area of ​​a traditional CMOS (Complementary Metal-Oxide-Semiconductor) circuit.

[0025] In summary, this invention can be widely applied in the field of signal processing technology. Attached Figure Description

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:

[0027] Figure 1 This is a schematic diagram of a method flow provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a unified signal model provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the connection relationship between the verification node and each variable node in a probabilistic graphical model provided by an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of a parallel processing architecture provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of a serial processing architecture provided in an embodiment of the present invention. Detailed Implementation

[0032] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0033] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0034] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "above," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure.

[0035] Existing classical estimation algorithms based on least squares (LS) or linear least mean square error (LMMSE) have computational complexity proportional to the square or even cube of the number of antennas, becoming a heavy burden on baseband processing units (such as DSPs and FPGAs), consuming a large amount of computational resources and time, and directly translating into significant power consumption. This invention provides a channel estimation method based on a memory computing unit, comprising: acquiring the pilot structure matrix and probabilistic graphical model of the channel to be estimated; determining the initial probability of the state value of each variable node in the probabilistic graphical model based on the pilot signal observed at the receiver and the variance of the channel uniform quantization; for any check node in the probabilistic graphical model, constructing the node state matrix corresponding to each undirected edge in the probabilistic graphical model based on each undirected edge between the check node and each connected target variable node, the pilot structure matrix transmitted by the transmitter, and the pilot signal observed by the receiver; and constructing the state matrix of each undirected edge in the probabilistic graphical model based on the confidence of each variable node transmitting its own state value to the check node. The corresponding driving vector involves, in the initial stage, using the initial probability of the state value of each variable node in the probabilistic graphical model as the confidence level by which the variable node transmits its own state value to each verification node connected by undirected edges; configuring the in-memory computing unit based on the node state matrix corresponding to each undirected edge to obtain the in-memory computing unit subarray corresponding to each undirected edge; determining the confidence level by which each verification node in the probabilistic graphical model transmits its own state value to the variable node based on the in-memory computing unit subarray corresponding to each undirected edge and the constructed driving vector, and then updating the confidence level by which each variable node transmits its own state value to the verification node until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task under test. This invention stores some static variables in in-memory computing units such as memristors, thereby transferring some traditional digital operations to the analog domain and using Kirchhoff's circuit laws for computation, breaking through the power consumption bottleneck of digital circuits.

[0036] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art. The ultra-low power universal baseband signal processing method and hardware circuit structure proposed in this invention are applicable to different types of application scenarios, and will now be described in detail with reference to specific embodiments.

[0037] Example 1

[0038] like Figure 1 As shown, this embodiment provides a channel estimation method based on a memory computing device, including the following steps:

[0039] S1. Obtain the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of the state value of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance.

[0040] In-memory computing devices are integrated devices that combine storage and computing capabilities, such as resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory (MRAM), and flash memory.

[0041] The channel estimation task is used to estimate the pilot signal observed at the receiver. The pilot structure matrix of the channel estimation task transmitted by the transmitter. To determine the continuous channel estimation results, the channel vector to be estimated is... , Represents the channel vector to be estimated The Each channel vector. The channel state is in... Discretize at equal intervals within the quantization range A state, namely , Indicates the quantization boundary value. Represents the channel vector to be estimated The One state, For the state set space, the values ​​taken are different depending on the number of discrete values ​​of the channel in the channel estimation task.

[0042] Among them, the probabilistic graphical model is a unified probabilistic graphical model corresponding to the pilot structure matrix, used for the task of estimating the channel under test.

[0043] The specific process of step S1 above is as follows:

[0044] S101. Obtain the pilot structure matrix transmitted by the transmitting end. .

[0045] Specifically, the pilot structure matrix of the channel estimation task transmitted by the transmitter. It is a dimension of The matrix, Pilot structure matrix number of rows; Pilot structure matrix The number of columns; Indicates that there is One transmitting antenna, This indicates that the pilot signal is occupied. Each time slot.

[0046] Specifically, the channel vector to be estimated Pilot signals observed at the receiving end The pilot structure matrix of the channel estimation task transmitted by the transmitter. There exists a unified signal model as ,like Figure 2 As shown (where Rx and Tx are the receiver and transmitter, respectively). For noise, continuous, continuous, For unknown discrete variables.

[0047] S102. Based on the unified signal model of the channel estimation task, construct the probabilistic graphical model of the channel estimation task under test according to the pilot structure matrix sent by the transmitter.

[0048] Specifically, the probabilistic graphical model includes variable nodes. Verification Node And undirected edges, where variable nodes The unknown variable represents the channel vector to be estimated in this invention. That is, each variable node corresponds to the channel vector to be estimated. One of the channel vectors; verification node This represents the coupling relationship between the pilot structure matrix transmitted by the transmitter for channel estimation, the pilot signal observed by the receiver, and the channel vector to be estimated; undirected edges are used to connect variable nodes and check nodes that have a connection relationship. Each variable node uniquely corresponds to the pilot structure matrix. A column vector in the array, where each check node uniquely corresponds to the pilot structure matrix. A row vector within the pilot structure matrix. The Middle Row vector representation , Pilot structure matrix No. Line 1 Column elements, representing validation nodes. With variable nodes The correlation between them, if the pilot structure matrix middle If the element is 1, then the check node is valid. With variable nodes If there is a connection relationship, and the pilot structure matrix has a connection relationship, then... middle If the element is 0, then the check node is validated. With variable nodes No connection exists.

[0049] To better illustrate the relationship between the pilot structure matrix and the probabilistic graphical model, as well as the relationship between variable nodes, check nodes, and undirected edges, the following Example 1 is presented and combined with... Figure 3 Let me introduce it.

[0050] Example 1: When the pilot structure matrix for OK, When the column matrix has a row vector in the third row of [0, 1, 1, 1, 0, 0], the probabilistic graphical model includes... One verification node, Number of variable nodes (at this time, (6), the third verification node in the probabilistic graphical model (at this time, 3) The connection relationships between the variables and the nodes are as follows: Figure 3 As shown, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 3 Apart from the third verification node, the connection relationships between other verification nodes and variable nodes are not shown. The connection relationships between other verification nodes and variable nodes can be understood by referring to the connection relationship between the third verification node and variable nodes mentioned above.

[0051] S103. Based on the pilot signal observed at the receiver, the pilot structure matrix transmitted at the transmitter, the variance of the channel uniform quantization, and the noise variance, determine the initial probability of the state value of each variable node in the probabilistic graphical model, i.e., the probability of each variable node's state value. The corresponding channel vector to be estimated The initial probability.

[0052] Specifically, the initial probability of the state value can be determined as follows:

[0053] 1) Calculate the variance of uniform quantization of the channel. The MMSE estimator reduces estimation error by introducing a regularization term into the maximum likelihood solution, which is related to noise power and channel prior statistics.

[0054] 2) Based on the pilot signal observed at the receiving end Pilot structure matrix Variance of channel uniform quantization and noise variance Calculate the initial estimates for all variable nodes, where the initial estimates for all variable nodes are... ,in, Represents the pilot structure matrix The transpose of .

[0055] 3) Calculate the distance from the initial estimate of all variable nodes to the state set space of the variable nodes, where the variable nodes... Initial estimation results to the state set space distance .

[0056] 4) Based on the distances from the initial estimates of all variable nodes to the state set space, obtain the initial probabilities of the state values ​​corresponding to each variable node, where the variable node... The initial probability of the corresponding state value is .

[0057] S2. For any check node in the probabilistic graphical model, construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model based on each undirected edge between the check node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver.

[0058] Here, the target variable node is a variable node that is connected to a certain verification node through an undirected edge. The target undirected edge is the undirected edge connecting the verification node and the target variable node.

[0059] Specifically, in this embodiment, for any verification node in the probabilistic graphical model, each target variable node connected to the verification node through undirected edges can be determined, as well as the target undirected edges between the verification node and each target variable node can be determined. Based on each target undirected edge and the pilot structure matrix, the node state matrix corresponding to each target undirected edge is constructed.

[0060] Specifically, the node state matrix is ​​a matrix used to configure the state of nodes in the in-memory computing unit.

[0061] It is understood that this embodiment can construct a node state matrix corresponding to each target undirected edge connected to a certain verification node. Therefore, this embodiment can construct a node state matrix corresponding to each undirected edge based on each undirected edge in the probabilistic graphical model. The total number of node state matrices corresponds to the total number of undirected edges.

[0062] S3. Based on the confidence level of each variable node in the probabilistic graphical model in transmitting its own state value to the verification node, construct the driving vector corresponding to each undirected edge in the probabilistic graphical model. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence level of the variable node in transmitting its own state value to each verification node connected by the undirected edge.

[0063] Specifically, in this embodiment, for any verification node in the probabilistic graphical model, the driving vector corresponding to each undirected edge can be constructed based on each undirected edge connected to the verification node and the confidence level of each variable node in passing its own state value to the verification node.

[0064] It is understandable that variable nodes will only send messages to check nodes that have a connection relationship, and will not send messages to check nodes that do not have a connection relationship.

[0065] It should be noted that the driving vector is used to input a driving physical quantity of a corresponding size into the in-memory computing unit, which drives the in-memory computing unit to store and compute based on its in-memory computing characteristics, thereby realizing channel estimation.

[0066] It is understood that this embodiment can construct a driving vector for each target undirected edge connected to a certain verification node. Therefore, this embodiment can construct a driving vector for each undirected edge based on each undirected edge in the probabilistic graphical model. The total number of driving vectors corresponds to the total number of undirected edges.

[0067] S4. Configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge to obtain the in-memory compute unit subarray corresponding to each undirected edge.

[0068] Specifically, in this embodiment, for any node state matrix corresponding to an undirected edge, the state of each node in the initial in-memory compute unit can be configured according to the node state matrix corresponding to the undirected edge to obtain the in-memory compute unit subarray corresponding to the undirected edge.

[0069] The initial state in-memory compute unit can be an in-memory compute unit whose node state has not been set.

[0070] It is understood that, in this embodiment, for any undirected edge in the probabilistic graphical model, a corresponding in-memory compute subarray can be configured.

[0071] S5. Based on the in-memory computing subarray corresponding to each undirected edge and the constructed driving vector, determine the confidence level of each verification node in the probabilistic graphical model when it transmits its own state value to the variable node, and then update the confidence level of each variable node when it transmits its own state value to the verification node until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task to be tested.

[0072] Specifically, this embodiment can determine the continuous channel estimation results in the channel estimation task under test based on the in-memory computing subarray corresponding to each undirected edge in the probabilistic graphical model and the constructed driving vector, as well as the confidence of message passing between each variable node and each verification node connected through the undirected edge.

[0073] The channel estimation method based on in-memory computing proposed in this embodiment can configure the in-memory computing subarray and driving vector corresponding to each undirected edge in the probabilistic graphical model according to the pilot structure matrix and probabilistic graphical model of the channel estimation task to be tested sent by the transmitter. Based on the in-memory computing subarray, driving vector, and confidence of message passing between each variable node and each verification node connected through the undirected edge, the continuous channel estimation results in the channel estimation task to be tested are determined. This invention can store some static variables involved in channel estimation in the in-memory computing unit and transfer some digital operations to the in-memory computing unit, utilizing the storage and computing performance of the in-memory computing unit for computation, thus overcoming the power consumption bottleneck and significantly reducing its hardware resource consumption and power consumption.

[0074] based on Figure 1 This embodiment proposes a second channel estimation method based on a memristor. In this method, the memristor is a memory resistor, and the node state matrix in step S2 is a node resistance state matrix.

[0075] Specifically, for the first There are undirected edges, and the node state matrix. for:

[0076]

[0077] in, for The corresponding nodal resistance matrix; Indicates the first The nth undirected edge (i.e., the nth undirected edge) The verification node and the first The candidate vector constructed from the undirected edges between the n variable nodes is the first one. Each element value; and , indicating the verification node Connected and variable nodes The state value is The combination of all variable node states, Represents the variable nodes in the candidate vector The corresponding element value; Indicates the noise variance; This indicates the pilot signal observed at the receiver. The One signal; Represents the pilot structure matrix The first in Column vector, where, China satisfies of The corresponding variable node is the check node. There is a connection. Represents the variable node A set of indexes of verifiable nodes with interconnected relationships.

[0078] Specifically, the construction process of the above-mentioned nodal resistance matrix includes:

[0079] S201, Obtain the number of undirected edges in the target area. Each target undirected edge is then assigned an internal order among all target undirected edges.

[0080] S202, constructing by Multiple candidate vectors are obtained by permuting and combining n target characters, and the number of candidate vectors is . For any candidate vector, if the element order of the target character in the candidate vector is equal to the internal order of the target undirected edge, then an association is established between the target character in the candidate vector and the target variable node connected by the target undirected edge. Here, the target character and... correspond.

[0081] S203. Iterate through each target undirected edge in turn.

[0082] S204, For the traversed first... There are several undirected edges representing the target vectors, which divide the multiple candidate vectors into several groups to be processed. Candidate vectors, based on each... Using candidate vectors, correlation relationships, pilot structure matrices, pilot signals observed at the receiver, variance of channel uniform quantization, and noise variance, construct the node resistance state matrix corresponding to the undirected edge of the target; where, the th... Among the candidate vectors, the th... The elements are .

[0083] Specifically, according to each Based on candidate vectors, correlation relationships, pilot structure matrices, pilot signals observed at the receiver, variance of channel uniform quantization, and noise variance, construct the node resistance state matrix corresponding to the target undirected edge, including:

[0084] (1) For any candidate vector to be processed, construct a zero vector with a total number of elements equal to the total number of variable nodes. Determine the node order of the target variable nodes associated with each target character in the candidate vector to be processed as the unique order to be arranged for each target character. Replace each zero element in the zero vector whose position order is equal to the order to be arranged with the target character uniquely corresponding to the order to be arranged to obtain the processed candidate vector. The candidate vector to be processed is any first-order variable variable node. There are 10 candidate vectors.

[0085] (2) Determine the unique target row vector corresponding to the verification node in the pilot structure matrix.

[0086] (3) Multiply the target row vector by each processed candidate vector to obtain multiple corresponding values, and arrange them as follows: A column vector of resistance states at each node. This represents the number of states.

[0087] (4) The column vectors of the resistive states of each node are horizontally concatenated, and the results are based on the pilot signals observed at the receiver. Variance of channel uniform quantization and noise variance We obtain the node resistance state matrix corresponding to the target undirected edge.

[0088] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 3 Let me introduce it.

[0089] Example 1: In this embodiment, for any verification node... The verification node can be determined in the probabilistic graphical model. Connecting the target variable nodes and the target undirected edges. For example... Figure 3 As shown, when When the value is 3, the target variable nodes connected by the 3rd verification node are the 2nd, 3rd, and 4th variable nodes, respectively. At this time, the number of undirected edges in the target node is... The value is 3. Each target undirected edge is an undirected edge connecting the 3rd verification node to the 2nd, 3rd, and 4th variable nodes, respectively. The internal order of each target undirected edge among all target undirected edges is 1, 2, and 3.

[0090] The target character includes 0 and 1. At this point... The result is 3. Multiple candidate vectors are constructed by permuting and combining the three target characters. The number of candidate vectors is 2^3, or 8: (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), and (1,1,1). It can be understood that the number of elements in the candidate vectors is the same as the number of undirected edges in the target vectors. The first, second, and third target characters in the candidate vectors are then associated with the target variable nodes connected by the undirected edges in the internal order 1, 2, and 3, respectively. In other words, the first, second, and third target characters in the candidate vectors are associated with the second, third, and fourth variable nodes, respectively.

[0091] The internal order of the target undirected edge. The process iterates through the first, second, and third target undirected edges in sequence. Each time a target undirected edge is encountered, the eight candidate vectors are divided into first candidate vectors and second candidate vectors. For example, when iterating through the third target undirected edge... If the third element of a candidate vector is 1, it is determined as the first candidate vector. If the third element of a candidate vector is 0, it is determined as the second candidate vector. The first candidate vectors include (0, 0, 1), (0, 1, 1), (1, 0, 1), and (1, 1, 1), while the second candidate vectors include (0, 0, 0), (0, 1, 0), (1, 0, 0), and (1, 1, 0).

[0092] Each of the first and second candidate vectors mentioned above is taken as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as a candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) is first constructed with a total number of elements equal to the total number of variable nodes (6). The first, second, and third target characters in the first candidate vector are associated with the second, third, and fourth variable nodes, respectively. Therefore, in this embodiment, the second, third, and fourth zero elements in the zero vector can be replaced with the first, second, and third target characters in the first candidate vector, respectively, to obtain the corresponding processed first candidate vector (0, 0, 1, 1, 0, 0).

[0093] At this point, when this embodiment traverses to the third target undirected edge, it can obtain four processed first candidate vectors and four processed second candidate vectors based on this target undirected edge. Then, this embodiment can determine the unique target row vector corresponding to the third check node in the pilot structure matrix, i.e., the third row vector in the pilot structure matrix. This target row vector is multiplied by each of the four processed first candidate vectors to obtain four corresponding values, which are then arranged vertically to obtain the first node's resistive state column vector. This target row vector is then multiplied by each of the four processed second candidate vectors to obtain four corresponding values, which are then arranged vertically to obtain the second node's resistive state column vector. The first and second node resistive state column vectors are then horizontally concatenated, and the result is determined based on the pilot signal observed at the receiver. Variance of channel uniform quantization and noise variance Thus, the node resistance state matrix corresponding to the third target undirected edge is obtained.

[0094] Specifically, when the in-memory processor is a memristor, the driving vector in S3 is a voltage vector, and step S3 includes:

[0095] When traversing to the th When the target is an undirected edge, delete the first edge from each candidate vector. Given several elements, we obtain multiple first vectors. We then remove duplicates from these first vectors to obtain multiple second vectors. For any second vector, we determine the target confidence level corresponding to each target character in the second vector. We multiply the target confidence levels corresponding to each target character in the second vector to obtain the product of the second vector. We arrange the products of each second vector to obtain the voltage vector corresponding to the undirected edge of the target. The target confidence level corresponding to the target character in the second vector is: the confidence level of the target variable node associated with the target character, which transmits its own state value equal to the target character to the verification node.

[0096] Specifically, the first The voltage vector corresponding to each undirected edge is denoted as , dimension The first node resistance matrix Voltage vector of the row for:

[0097]

[0098] in, Indicates the selection of the first probability of row The corresponding set of indices; Indicates the first The voltage vector corresponding to the nth undirected edge One element,

[0099] probability It concerns the information passed between the variable node and the verification node. The function, and its specific calculation method includes but is not limited to:

[0100]

[0101] in, Represents variable nodes To the verification node The information about the channel vector to be estimated is passed between them. The news Represents the variable nodes in the vector The corresponding element value, and , representing variable nodes From the verification node A set of indexes of variable nodes with connections Take the value from; at the start of the first iteration, .

[0102] Specifically, the upper limit of the number of voltage vectors input to the memristor subarray is the set. Mid-vector The number of them is , of which the set Indicates and verifies the node There are connections, except for variable nodes. The combination of all variable node states except for those.

[0103] Specifically, variable nodes To the verification node The information about the channel vector to be estimated is passed between them. The confidence level of the message is:

[0104]

[0105] in, Represents variable nodes To the verification node Passing information about variable nodes between nodes The state value is The news Represents variable nodes To the verification node The message is from the verification node. Other than variable nodes Connected verification nodes Provide message generation, The calculation methods include, but are not limited to, , Indicates the variable node at the start of the first iteration. To the verification node The information transmitted between them The message; Indicates the verification node To the variable node Passing information about variable nodes between nodes The state value is The news Indicates the verification node From variable nodes A set of check node indexes with connections Take the value from the middle, but verify the node. Do not take ; Represents variable nodes From the verification node A set of indexes of variable nodes with connections The value is taken from the variable node. Do not take .

[0106] Specifically, the verification node To the variable node The confidence level of the messages passed between them is:

[0107]

[0108] Specifically, when the in-memory computing unit is a memristor, the in-memory computing unit subarray is a memristor subarray. In this case, the node state matrix in the channel estimation task is... It is related not only to the undirected edges and pilot structure matrix, but also to the pilot signal observed at the receiver. Relevant. Observed pilot signal. Since the values ​​are different each time a signal arrives at the receiver, and considering the requirements for stable and high-speed signal processing, it is not possible to refresh the array values ​​after each signal arrival. Therefore, it is necessary to update the node state matrix. After the values ​​are statically defined, they are configured in the in-memory compute unit. Each variable is then directly configured... , Separate quantization and recombination will lead to dimensionality explosion, and deploying these discrete results to in-memory computing is very inefficient. Therefore, this invention employs a holistic quantization method, and step S4 above includes:

[0109] S401, elements in the nodal resistance matrix If we consider it as a whole, its value distribution can be regarded as a Gaussian distribution with a mean of 0.

[0110] S402. Set an acceptable range based on a trade-off between performance and complexity. .

[0111] S403, within the acceptance interval The above whole is quantified as follows: There are quantized states, and the quantization step size is... , recorded as to form a scale of Array.

[0112] S404, after quantization, for the first... In the n undirected edges, the th The element has a value of , for The quantization state of the th quantization state indivual.

[0113] S405. Configure the quantized node resistance matrix values ​​into the in-memory compute unit to obtain the in-memory compute unit subarray corresponding to each undirected edge.

[0114] Specifically, the memristor subarray corresponding to the undirected edge constructed in this embodiment It can be represented as:

[0115]

[0116] in, Represents the memristor subarray. The verification node and the first The undirected edges between the nth variable nodes correspond to the memristor subarray (i.e., the nth variable node). In the memristor subarray) the th The first line Each element.

[0117] Specifically, when the in-memory processor is a memristor, step S5 above includes:

[0118] S501. For any undirected edge, based on each voltage element in the voltage vector corresponding to the undirected edge, input a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and read the memristor subarray respectively. Current value in .

[0119] Specifically, the voltage vector is input to the memristor subarray. First, route selection is performed (selecting which row of voltage to input). Corresponding voltage input behavior:

[0120]

[0121] If there are multiple If you select to input on the same line, then select the line containing the input. Add them together.

[0122] S502. Based on the current value read from each memristor subarray, determine the confidence level of each verification node in the probabilistic graphical model in transmitting its own state value to the variable node, and then update the new confidence level of each variable node in transmitting its own state value to each verification node. .

[0123] Specifically, when using memristor subarrays, according to Therefore, the output current is... .

[0124] S503. Determine whether the preset iteration stop condition has been met.

[0125] S504. If the preset iteration stop condition is not met, the new confidence level of each variable node passing its own state value to each verification node is taken as the confidence level of the current corresponding variable node passing its own state value to each verification node. Return to step S3 to recalculate until the preset iteration stop condition is met.

[0126] S505. If the preset iteration stopping condition is met, then based on the initial probability of the state value of each variable node in the probabilistic graphical model and the new confidence obtained by the current corresponding variable node passing its own state value to each verification node, update the new probability of the state value of each variable node. Interpolation is used to determine the continuous channel estimation results in the channel estimation task under test.

[0127] Specifically, each variable node New probability of state value for:

[0128]

[0129] Specifically, considering that the channel is continuous, the new probability is based on the state value of each variable node. Interpolation is used to obtain continuous channel estimation results in the channel estimation task under test. The calculation methods include, but are not limited to, ,in, .

[0130] In a preferred embodiment of the present invention, it further includes a DAC (digital-to-analog converter) module and an ADC (analog-to-digital converter) module, wherein the ADC module is used to convert the memristor subarray... Output current value The calculations for message passing between the variable node and the verification node are converted into digital signals. This calculation process can be implemented using an existing FPGA (Field-Programmable Gate Array), which will not be elaborated upon here. The DAC module is used to convert the calculation results of the message passing between the variable node and the verification node into voltage signals for iterative calculations of message passing between the verification node and the variable node.

[0131] In a preferred embodiment of the present invention, the computing architecture of the in-memory computing device is configured in two modes, including: a time-parallel processing architecture and a time-serial processing architecture.

[0132] like Figure 4 The diagram shows a time-parallel processing architecture where each subarray is independently disconnected. For example, channel estimation can be performed using each memristor subarray by simultaneously inputting the input voltage into all subarrays and reading out the current for iterative calculation.

[0133] Figure 5 The diagram shows a time-series processing architecture, with each subarray connected. For example, each memristor subarray can be spliced ​​together to form a large memristor array for channel estimation. The implementation method is to input voltage to the corresponding subarray in a time-slot manner, and each subarray reads the corresponding input voltage and current in a time-slot manner for iterative calculation.

[0134] It should be noted that the array values ​​and sizes are exactly the same in both methods. In the time-parallel processing architecture, the subarrays are disconnected independently, while in the time-serial processing architecture, the subarrays are not disconnected. The subarrays can be arranged and connected sequentially.

[0135] To better illustrate the above execution process, this embodiment provides... Figure 4 The time-serial processing architecture shown is described in detail.

[0136] like Figure 4 As shown, the node resistance matrix constructed in this embodiment has The voltage vector has The current read is . Figure 4 The DAC is an exponential-to-analog converter, and the ADC is an exponential-to-digital converter.

[0137] in, This represents the memristor subarray corresponding to the undirected edge between the first check node and the first variable node with a connection relationship. Indicates the first The verifiable node and the first node with a connection relationship The undirected edges between the variable nodes correspond to the memristor subarrays. It should be noted that... and It does not refer to the second node order of the variable node, but rather to the order of the variable node connected to the check node among all the variable nodes connected to that check node.

[0138] This represents the voltage vector corresponding to the undirected edge between the first verification node and the first variable node with a connection relationship. Indicates the first The verifiable node and the first node with a connection relationship The voltage vector corresponding to the undirected edge between each variable node. This represents the current value in the memristor subarray corresponding to the undirected edge between the first verification node and the first variable node with which it is connected. Indicates the first The verifiable node and the first node with a connection relationship The current values ​​in the memristor subarray corresponding to the undirected edges between the variable nodes.

[0139] Corresponding to the same undirected edge and For example, in this embodiment, the undirected edge can be used as a reference. Each voltage element in the array is transmitted via a digital-to-analog converter (DAC) to the memristor subarray corresponding to the undirected edge. Each row of nodes in the array receives a voltage equal to the size of the voltage element; for example, this voltage is input to the memristor subarray. The first row of nodes in the input and... A voltage equal to the magnitude of the first voltage element is applied to the memristor subarray. The second row of nodes in the input is the same as the input. A voltage equal to the second voltage element is applied until the last row of nodes in the memristor subarray is input. The voltage is equal to the value of the last voltage element. Then, in this embodiment, the current value in the memristor subarray can be read via an analog-to-digital converter (ADC). For the node resistance matrix, voltage vector, and current vector corresponding to other undirected edges, this embodiment can refer to the above process for parallel processing, and will not be repeated here.

[0140] The channel estimation method based on in-memory computing proposed in this embodiment can store some static variables in devices with in-memory computing characteristics such as memristors, thereby transferring some digital operations to the analog domain and using Kirchhoff's circuit laws for calculation, breaking through the power consumption bottleneck of digital circuits and realizing innovation in channel estimation.

[0141] Example 2

[0142] This embodiment provides a channel estimation system based on a memory computing unit, including:

[0143] The acquisition unit is used to acquire the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and to determine the initial probability of the state value of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance.

[0144] The node state matrix construction unit is used to construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model for any verification node in the probabilistic graphical model, based on each undirected edge between the verification node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver.

[0145] The driving vector construction unit is used to construct the driving vector corresponding to each undirected edge in the probabilistic graphical model based on the confidence of each variable node in the probabilistic graphical model in passing its own state value to the verification node. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence of the variable node in passing its own state value to each verification node connected by the undirected edge.

[0146] The configuration unit is used to configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory compute unit subarray corresponding to each undirected edge.

[0147] The estimation result determination unit is used to determine the confidence level of each verification node in the probabilistic graphical model to pass its own state value to the variable node based on the in-memory computing subarray corresponding to each undirected edge and the constructed driving vector. Then, it updates the confidence level of each variable node to pass its own state value to the verification node until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task under test.

[0148] The system provided in this embodiment is used to execute the above-described method embodiments. For specific processes and details, please refer to the above embodiments, which will not be repeated here.

[0149] The channel estimation system based on in-memory computing proposed in this embodiment can configure the in-memory computing subarray and driving vector corresponding to each undirected edge in the probabilistic graphical model according to the pilot structure matrix and probabilistic graphical model of the channel estimation task under test. Based on the in-memory computing subarray, driving vector, and confidence of message passing between each variable node and each verification node connected through the undirected edge, the continuous channel estimation results in the channel estimation task under test are determined. This invention can store some static variables involved in channel estimation in the in-memory computing unit and transfer some digital operations to the in-memory computing unit. It utilizes the storage and computing performance of the in-memory computing unit for computation, breaking through the power consumption bottleneck and significantly reducing its hardware resource consumption and power consumption while retaining the channel estimation capability.

[0150] Example 3

[0151] This embodiment provides a processing device corresponding to the channel estimation method based on in-memory computing provided in Embodiment 1. The processing device can be applied to client processing devices, such as mobile phones, laptops, tablets, desktop computers, etc., to execute the method of Embodiment 1.

[0152] The processing device includes a processor, a memory, a communication interface, and a bus. The processor, memory, and communication interface are connected via the bus to enable communication between them. The memory stores computer programs that can run on the processing device. When the processing device runs the computer programs, it executes the channel estimation method based on a memory-computing device provided in Embodiment 1.

[0153] In some implementations, the memory may be high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device.

[0154] In other implementations, the processor can be any type of general-purpose processor, such as a central processing unit (CPU) or a digital signal processor (DSP), and there is no limitation here.

[0155] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] Those skilled in the art will understand that the structure of the above-described computing device is only a partial structure related to the present invention and does not constitute a limitation on the computing device to which the present invention is applied. A specific computing device may include more or fewer components, or combine certain components, or have different component arrangements.

[0157] Example 4

[0158] This embodiment provides a computer program product corresponding to the channel estimation method based on in-memory computing provided in Embodiment 1. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing the channel estimation method based on in-memory computing described in Embodiment 1 are loaded.

[0159] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof.

[0160] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0161] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0162] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0163] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0164] The above embodiments are only used to illustrate the present invention. The structure, connection method and manufacturing process of each component can be varied. All equivalent transformations and improvements made on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims

1. A channel estimation method based on in-memory computing, characterized in that, include: Obtain the pilot structure matrix and probabilistic graphical model for the channel estimation task, and base the results on the pilot signals observed at the receiver, the variance of the channel uniform quantization, and... Determine the initial probability of the state value of each variable node in the probabilistic graphical model; For any check node in the probabilistic graphical model, construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model based on each undirected edge between the check node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver. Based on the confidence level of each variable node in the probabilistic graphical model in passing its own state value to the verification node, the driving vector corresponding to each undirected edge in the probabilistic graphical model is constructed. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence level of the variable node in passing its own state value to each verification node connected by the undirected edge. Based on the node state matrix corresponding to each undirected edge, the in-memory computing unit is configured to obtain the in-memory computing unit subarray corresponding to each undirected edge. Based on the in-memory computing subarray corresponding to each undirected edge and the constructed driving vector, the confidence level of each verification node in the probabilistic graphical model that it transmits its own state value to the variable node is determined, and then the confidence level of each variable node that it transmits its own state value to the verification node is updated until the set iteration stopping condition is met, thus determining the continuous channel estimation results in the channel estimation task to be tested. When the in-memory computing device is a memristor, the node state matrix is ​​a node resistance state matrix. The node state matrix corresponding to each undirected edge in the constructed probabilistic graphical model includes: Get the number of target undirected edges Determine the internal order of each target undirected edge among all target undirected edges; Build by Multiple candidate vectors are obtained by permuting and combining n target characters, and the number of candidate vectors is . , This refers to the number of states after discretizing the channel state at equal intervals within a certain range. For any candidate vector, if the element order of the target character in the candidate vector is equal to the internal order of the target undirected edge, then an association is established between the target character in the candidate vector and the target variable node connected by the target undirected edge. Here, the target character and... correspond, The first element of the channel vector to be estimated represents the first element of the channel vector to be estimated. One state; Iterate through each target undirected edge in turn; For the traversed number... There are several undirected edges representing the target vectors, which divide the multiple candidate vectors into several groups to be processed. The candidate vectors are determined based on each... Using candidate vectors, correlation relationships, pilot structure matrices, pilot signals observed at the receiver, variance of channel uniform quantization, and noise variance, construct the node resistance state matrix corresponding to the undirected edge of the target; where, the th... Among the candidate vectors, the th... The elements are ; The node resistance matrix for: in, for The corresponding nodal resistance matrix; Indicates the first The candidate vector constructed from the nth undirected edge Each element value; , Indicates and verifies the node Connected and variable nodes Values The combination of all variable node states, Represents the variable nodes in the candidate vector The corresponding element value; express ; This indicates the pilot signal observed at the receiver. The One signal; Represents the pilot structure matrix The first in Column vector; The configuration of the in-memory compute unit based on the node state matrix corresponding to each undirected edge, resulting in an in-memory compute unit subarray corresponding to each undirected edge, includes: Elements in the nodal resistance matrix If we consider it as a whole, its value distribution is regarded as a Gaussian distribution with a mean of 0; Within a pre-defined acceptance range, the entire above is quantified as follows: One quantized state; After quantization, for the first In the n undirected edges, the th Each element has the following values: in, This is the quantization step size; for The quantization state of the th quantization state indivual; The quantized node resistance matrix values ​​are configured into the in-memory compute unit to obtain the in-memory compute unit subarray corresponding to each undirected edge.

2. The channel estimation method based on a memory computing unit as described in claim 1, characterized in that, The process involves acquiring the pilot structure matrix and probabilistic graphical model for estimating the channel under test, and then basing this model on the pilot signals observed at the receiver, the variance of the channel uniform quantization, and... Determine the initial probability of the state value of each variable node in the probabilistic graphical model, including: Obtain the pilot structure matrix transmitted by the transmitting end; Based on the unified signal model for the channel estimation task, a probabilistic graphical model for the channel estimation task is constructed according to the pilot structure matrix transmitted by the transmitter. The unified signal model for the channel estimation task is as follows: , The pilot signal observed at the receiving end. Let be the channel vector to be estimated; For noise, The pilot structure matrix for the channel estimation task transmitted by the transmitter; Pilot structure matrix number of rows; Pilot structure matrix The number of columns; Based on the pilot signal observed at the receiver, the pilot structure matrix transmitted at the transmitter, and the variance of the channel uniform quantization, Determine the initial probability of the state value of each variable node in the probabilistic graphical model.

3. The channel estimation method based on a memory computing unit as described in claim 2, characterized in that, The parameters are: the pilot signal observed at the receiver, the pilot structure matrix transmitted by the transmitter, and the variance of the channel uniform quantization. Determine the initial probability of the state value of each variable node in the probabilistic graphical model, including: Calculate the variance of uniform quantization of the channel; Based on the pilot signal observed at the receiver, the pilot structure matrix, the variance of the channel uniform quantization, and... Calculate the initial estimates for all variable nodes; Calculate the distance from the initial estimation results of all variable nodes to the state set space of the variable nodes, where the state set space of the variable nodes includes several states after the channel state is discretized at equal intervals within a certain range; The initial probability of the state value corresponding to each variable node is obtained by calculating the distance from the initial estimate of all variable nodes to the state set space.

4. The channel estimation method based on a memory computing unit as described in claim 1, characterized in that, When the in-memory computing unit is a memristor, the driving vector is a voltage vector. Based on the in-memory computing unit subarray corresponding to each undirected edge and the constructed driving vector, the confidence level of each verification node in the probabilistic graphical model that it transmits its own state value to the variable node is determined. This confidence level of each variable node that it transmits its own state value to the verification node is then updated until the set iteration stop condition is met, thus determining the continuous channel estimation results in the channel estimation task under test, including: For any undirected edge, according to each voltage element in the voltage vector corresponding to the undirected edge, input a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and read the current value in each memristor subarray respectively. Based on the current value read from each memristor subarray, determine the confidence level of each verification node in the probabilistic graphical model in passing its own state value to the variable node, and then update the new confidence level of each variable node in passing its own state value to each verification node. Determine whether the preset iteration stopping condition has been met; If the preset iteration stop condition is not met, the new confidence level of each variable node passing its own state value to each verification node will be used as the confidence level of the current corresponding variable node passing its own state value to each verification node, and the calculation will be repeated until the preset iteration stop condition is met. If the preset iteration stopping condition is reached, the new probability of the state value of each variable node is updated based on the initial probability of the state value of each variable node in the probabilistic graphical model and the new confidence obtained by the current corresponding variable node passing its own state value to each verification node. Then, the continuous channel estimation results in the channel estimation task under test are determined by interpolation.

5. A channel estimation system based on a memory computing unit, characterized in that, include: The acquisition unit is used to acquire the pilot structure matrix and probabilistic graphical model of the channel under test for estimation, and to acquire the pilot signal observed at the receiver, the variance of the channel uniform quantization, and the probability graph model. Determine the initial probability of the state value of each variable node in the probabilistic graphical model; The node state matrix construction unit is used to construct the node state matrix corresponding to each undirected edge in the probabilistic graphical model for any verification node in the probabilistic graphical model, based on each undirected edge between the verification node and each target variable node connected to it, the pilot structure matrix sent by the transmitter, and the pilot signal observed by the receiver. The driving vector construction unit is used to construct the driving vector corresponding to each undirected edge in the probabilistic graphical model based on the confidence of each variable node in the probabilistic graphical model in passing its own state value to the verification node. In the initial stage, the initial probability of the state value of each variable node in the probabilistic graphical model is used as the confidence of the variable node in passing its own state value to each verification node connected by the undirected edge. The configuration unit is used to configure the in-memory computing unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory computing unit subarray corresponding to each undirected edge. The estimation result determination unit is used to determine the confidence level of each verification node in the probabilistic graphical model to pass its own state value to the variable node based on the in-memory computing subarray corresponding to each undirected edge and the constructed driving vector, and then update the confidence level of each variable node to pass its own state value to the verification node until the set iteration stop condition is met, thereby determining the continuous channel estimation results in the channel estimation task under test. When the in-memory computing device is a memristor, the node state matrix is ​​a node resistance state matrix. The node state matrix corresponding to each undirected edge in the constructed probabilistic graphical model includes: Get the number of target undirected edges Determine the internal order of each target undirected edge among all target undirected edges; Build by Multiple candidate vectors are obtained by permuting and combining n target characters, and the number of candidate vectors is . , This refers to the number of states after discretizing the channel state at equal intervals within a certain range. For any candidate vector, if the element order of the target character in the candidate vector is equal to the internal order of the target undirected edge, then an association is established between the target character in the candidate vector and the target variable node connected by the target undirected edge. Here, the target character and... correspond, The first element of the channel vector to be estimated represents the first element of the channel vector to be estimated. One state; Iterate through each target undirected edge in turn; For the traversed number... There are several undirected edges representing the target vectors, which divide the multiple candidate vectors into several groups to be processed. The candidate vectors are determined based on each... Using candidate vectors, correlation relationships, pilot structure matrices, pilot signals observed at the receiver, variance of channel uniform quantization, and noise variance, construct the node resistance state matrix corresponding to the undirected edge of the target; where, the th... Among the candidate vectors, the th... The elements are ; The node resistance matrix for: in, for The corresponding nodal resistance matrix; Indicates the first The candidate vector constructed from the nth undirected edge Each element value; , Indicates and verifies the node Connected and variable nodes Values The combination of all variable node states, Represents the variable nodes in the candidate vector The corresponding element value; express ; This indicates the pilot signal observed at the receiver. The One signal; Represents the pilot structure matrix The first in Column vector; The configuration of the in-memory compute unit based on the node state matrix corresponding to each undirected edge, resulting in an in-memory compute unit subarray corresponding to each undirected edge, includes: Elements in the nodal resistance matrix If we consider it as a whole, its value distribution is regarded as a Gaussian distribution with a mean of 0; Within a pre-defined acceptance range, the entire above is quantified as follows: One quantized state; After quantization, for the first In the n undirected edges, the th Each element has the following values: in, This is the quantization step size; for The quantization state of the th quantization state indivual; The quantized node resistance matrix values ​​are configured into the in-memory compute unit to obtain the in-memory compute unit subarray corresponding to each undirected edge.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, wherein when the computer program instructions are executed by a processor, they are used to implement the steps corresponding to the channel estimation method based on the in-memory computing unit as described in any one of claims 1-4.

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