Time axis phase unwrapping method and system based on FPGA

Abstract

The invention belongs to the technical field of distributed optical fiber sensing (DAS) system signals, and discloses a time axis phase unwrapping method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps of phase data acquisition, stable group formation, phase progressive unwrapping, assembly line and cache cooperative processing and quality measurement closed-loop correction. According to the system, real-time phase extraction of interference signals is achieved through the FPGA demodulation unit, phase change is dynamically unwrapped through the reliable period screening unit and the phase progressive unwrapping unit, a self-adaptive unwrapping mechanism is formed in combination with anomaly judgment and threshold updating logic, and through collaborative design of an annular cache and a three-level assembly line comparator, the interference signal is obtained. According to the method, parallel transmission and time sequence synchronization of data are achieved, the precision and stability of phase unwrapping can be effectively improved in a complex noise environment, hardware delay and resource occupation are remarkably reduced, and the method is suitable for real-time signal unwrapping processing of a high-precision distributed optical fiber sensing system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of distributed acoustic sensing (DAS) system signals, and particularly relates to a time-axis phase unwrapping method and system based on FPGA. BACKGROUND

[0002] A distributed acoustic sensing (DAS) system is a detection technology based on backscattering Rayleigh signals of an optical fiber, and is widely applied to scenes such as oil and gas pipeline safety monitoring, bridge structure health detection, and geological disaster warning. In such a system, phase changes of interference signals are used to reflect external disturbance conditions, and therefore phase unwrapping is an important step for restoring real phase changes from wrapped phase data, and the processing accuracy directly relates to the spatial positioning ability and monitoring sensitivity of the system.

[0003] Existing DAS systems mostly use digital signal processors or general central processing units for phase demodulation and unwrapping operations, and have certain flexibility, but under conditions of high sampling rates and multi-channel real-time monitoring, there are problems of large calculation delay and insufficient response speed. In order to improve processing efficiency, some systems attempt to use field programmable gate arrays (FPGAs) to realize phase unwrapping functions, output phase data through CORDIC algorithms, and expand according to phase differences of adjacent sampling periods on a time axis, so as to realize high-speed parallel operation at a hardware layer.

[0004] However, in actual applications in complex environments, the above-mentioned technology still has certain limitations. The fixed threshold determination method for phase jumps is difficult to adapt to changes in different noise levels and signal strengths, and is easy to misjudge noise fluctuations as real jumps, resulting in increased unwrapping errors. In phase data processing, the reliability of different sampling periods is not identified, local abnormal points are difficult to correct in time, and errors are easy to spread along the time axis. At the same time, there is a lack of effective synchronization feedback mechanism between data storage and calculation paths, the resource utilization rate of an FPGA on-chip is high, and the processing timing is easy to be limited, affecting the continuity and stability of the unwrapping process. SUMMARY

[0005] The application aims to provide a time-axis phase unwrapping method and system based on FPGA to solve the problems in the background technology.

[0006] In order to achieve the above-mentioned purpose, the application provides the following technical scheme: a time-axis phase unwrapping method based on FPGA, which completes initial phase acquisition, stable reference selection, progressive expansion, pipeline processing, and quality closed-loop correction in the same clock domain, and specifically includes the following links: Firstly, phase data acquisition: the interference signal collected by the distributed optical fiber sensing system is quadrature demodulated, the CORDIC algorithm is used to obtain the initial phase data on the time axis, and the data is written into the FPGA input buffer at a fixed sampling rate, which is synchronized with the system clock to ensure the consistency of the subsequent processing timing and the continuity of the data; Secondly, stable group formation: the phase stability index and the amplitude stability index of the continuous period are jointly determined in the FPGA; when the phase stability index is lower than the first threshold value and the amplitude stability index is not lower than the second threshold value, the period is marked as a reliable period point; when the number of continuous reliable period points is not less than the preset group length, a stable group is formed as the reference interval for subsequent expansion, thereby selecting a relatively stable and reliable phase reference on the time axis; Thirdly, phase progressive unwrapping: starting from the end period of the stable group, the adjacent periods are processed one by one, when the phase difference between adjacent periods is lower than the third threshold value, cumulative unwrapping is performed; when the phase difference is not lower than the third threshold value, the phase change trend index and the amplitude change rate index of the previous and subsequent adjacent periods are jointly determined, if the preset abnormality determination condition is met, the period phase is corrected by ±2π, otherwise the current phase value is kept unchanged, so as to reduce the interference of isolated abnormalities on the entire phase sequence; Then, pipeline and buffer cooperative processing: three pipeline comparators of input stage, comparison stage and determination stage are cascaded in the FPGA, the phase data and the determination results are read and written in parallel and stored in a circular buffer composed of double-port BRAM, and the read and write pointers are cyclically managed by the control logic according to the preset update strategy, so that the data input, calculation and output continuously flow in the same clock domain and meet the real-time processing requirements; Finally, quality metric closed-loop correction: the quality metric index (error evaluation quantity including mean square error index) of the unwrapped phase sequence is calculated, when the index exceeds the fourth threshold value, the control logic sends a recalculation trigger signal, clears the intermediate result partition of the buffer and retains the input partition data, returns to the stable group formation and phase progressive unwrapping links to reselect and unwrap, forms an error feedback closed loop for time axis phase unwrapping, so as to ensure real-time while improving the reliability and continuity of long-time sequence phase unwrapping.

[0007] Further, the specific steps of the phase data acquisition are as follows: The FPGA demodulation unit receives the in-phase channel and quadrature channel voltage values of the interference signal output by the distributed optical fiber sensing system, respectively generates quadrature components and in-phase components through on-chip multiplication and addition operation logic, and then uses the CORDIC algorithm core to check the components for polar coordinate conversion to obtain the instantaneous phase of each sampling point; The transient phase is written into the internal input buffer area of the FPGA after being temporarily stored in a level-1 cache register, the input buffer area is composed of a dual-port storage unit, the writing end is driven by a sampling clock, and the reading end works synchronously with the subsequent phase screening unit under the same system clock domain, the sampling clock and the system clock are phase-locked through a clock distribution network, ensuring that the sampling interval is constant and that data writing and reading are performed under the same timing reference.

[0008] Further, the specific steps of forming the stable group are as follows: The determination logic circuit provided in the FPGA receives the phase data and amplitude data obtained from the input buffer area; The phase variation and the corresponding amplitude variation of a plurality of adjacent cycles are extracted in a preset sampling window, the phase stability index and the amplitude stability index of each cycle are obtained through a statistical calculation unit, and the values of the two indexes are compared with the first threshold value and the second threshold value stored in the threshold register in parallel; When the phase stability index of a cycle is less than the first threshold value and the amplitude stability index is not less than the second threshold value, the control logic writes a reliable flag bit at the cycle address position; when the number of continuous reliable flag bits reaches the preset group length, the control logic identifies the data in the continuous address segment as a stable group, and records the start address and the end address in the group index register, the stable group index information is used as the input reference of the subsequent phase unwinding unit.

[0009] Further, the specific steps of the phase progressive unwinding are as follows: The end cycle of the stable group is used as the unwinding start cycle, the phase data of adjacent cycles are read along the time axis in sequence, the phase difference between adjacent cycles is calculated and compared with the third threshold value stored in the threshold register; When the phase difference is less than the third threshold value, the phase values are accumulated in time sequence; when the phase difference is not less than the third threshold value, the phase variation trend data and the amplitude variation rate data of a plurality of cycles are read, and a joint judgment is made according to the preset trend judgment condition and the amplitude variation condition: if the judgment result meets the correction condition, the phase value of the current cycle is corrected by cycle jump; if the judgment result does not meet the correction condition, the phase value of the current cycle remains unchanged; The unwound phase data is output to the buffer area in time sequence for subsequent quality measurement and closed-loop correction.

[0010] Further, the specific steps of the pipeline and cache cooperative processing are as follows: A three-stage pipeline structure connected in sequence by an input stage, a comparison stage and a determination stage is formed in the FPGA, The phase data sequentially enters the comparison stage and the determination stage in the input stage for sequential processing, and the data is sequentially transmitted between the stages through a register to keep the timing consistent. The phase data and the determination result output by the determination stage are written into a ring buffer region composed of a dual-port BRAM, the buffer region sets a read pointer and a write pointer, and the read and write pointers are cyclically moved according to a preset update rule in clock beats, and when the interval between the write pointer and the read pointer reaches a preset buffer depth, the write pointer and the read pointer automatically enter a cyclic coverage mode, so that the phase data and the determination result are read and written in parallel and stored continuously. The output end of the buffer region synchronously transmits the unwound phase data of the current period to subsequent quality measurement and closed-loop correction, so as to ensure the sequential transmission and continuous processing of the data in the unified clock domain.

[0011] Further, the specific steps of the quality measurement and closed-loop correction are as follows: The unwound phase sequence output by the buffer region is sequentially read according to a preset sampling window, the phase difference data in the window is obtained by a statistical calculation unit, and the corresponding quality measurement parameter is calculated, the quality measurement parameter includes an error evaluation quantity reflecting the phase unwrapping accuracy; When the calculated quality measurement parameter exceeds the fourth threshold value stored in the threshold value register, the control logic generates a recalculation trigger signal and sends the signal to the buffer management unit; after receiving the recalculation trigger signal, the buffer management unit empties the intermediate results in the temporary storage partition, retains the original phase data of the input partition and the threshold value setting in the parameter register, so that the system re-executes the stable group formation and phase progressive unwinding process in the same clock domain; After the recalculation is completed, the new phase unwinding result replaces the original temporary storage data and is output to the buffer region, so that a continuous feedback closed loop is formed between data acquisition, unwrapping calculation and error evaluation.

[0012] The application further provides a time axis phase unwrapping system based on an FPGA, which is based on the above method, and the system comprises: A phase demodulation module is used for quadrature demodulating the interference signal and outputting time axis initial phase data; An FPGA unwrapping module comprises a reliable period screening unit, a phase progressive unwinding unit, an abnormality determination unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparator coupled therewith; A ring buffer module is composed of a dual-port BRAM on the FPGA, and comprises an input partition, a temporary storage partition and an output partition, and is used for parallel reading and writing and cyclic storage of the phase data and the determination result in the unwrapping process; A control and clock module is used for providing a system clock, threshold values and window parameters, a recalculation trigger signal, and for timing synchronization control of the read and write pointers and the pipeline stage registers; The FPGA unwrapping module and the ring buffer module are bidirectionally coupled through a correction signal and a holding signal; the abnormality determination result is used for guiding phase correction of the unwrapping unit, and is output to a quality metric and recalculation control unit to participate in online adjustment of a threshold value and a window parameter, thereby forming an algorithm-hardware cooperative closed loop.

[0013] Further, the phase demodulation module performs quadrature demodulation on the interference signal to obtain time axis initial phase data, the FPGA unwrapping module receives the initial phase data and performs phase screening, unwrapping and correction processing, the ring buffer module accesses the phase data and the determination result in the unwrapping process, and the control and clock module provides a unified clock signal and threshold parameter for each module and realizes overall timing synchronization.

[0014] Further, the FPGA unwrapping module comprises a reliable period screening unit, a phase progressive unwrapping unit, an abnormality determination unit, a quality metric and recalculation control unit, and a three-stage pipeline comparator sequentially connected with the units. The reliable period screening unit is used for continuously screening the input phase data, the phase progressive unwrapping unit performs phase unwrapping calculation according to the screening result, the abnormality determination unit judges the phase change trend and amplitude change rate, the quality metric and recalculation control unit calculates quality parameters and generates a recalculation trigger signal according to the determination result, and the three-stage pipeline comparator sequentially transmits comparison results between the units to ensure consistent data processing timing.

[0015] Further, the FPGA unwrapping module and the ring buffer module are bidirectionally connected through a correction signal and a holding signal, the correction signal output by the abnormality determination unit is used for guiding phase adjustment of the phase progressive unwrapping unit, and the holding signal and the correction signal are synchronously input to the quality metric and recalculation control unit to update real-time parameters in a threshold register and a window parameter register, so as to form a cooperative feedback closed loop of algorithm and hardware in the phase screening, unwrapping and quality metric process.

[0016] The present application has the following advantages: 1. The present application constructs a dynamic threshold value and window self-adaptive control mechanism in the FPGA, so that the phase unwrapping process can automatically adjust the determination parameters according to the real-time signal quality, when noise fluctuation caused by electromagnetic interference or structural vibration occurs in the monitoring environment, the system can quickly adjust the determination threshold value and the window length in the on-chip logic, thereby distinguishing the real phase change from the random noise disturbance, realizing noise response adaptive phase unwrapping, and compared with the fixed threshold value mode, the mechanism significantly improves the stability and precision of the unwrapping algorithm under complex noise conditions.

[0017] 2. This invention sets up a reliable period selection unit and a phase progressive unfolding unit in the FPGA unwrapping module to perform stability assessment and hierarchical processing on phase data with different sampling periods. The system uses window statistics and parallel comparison methods to identify reliable period points, and triggers phase correction operations on abnormal points through anomaly detection logic to prevent local errors from spreading along the time axis. Through this mechanism, the system can effectively suppress the accumulation of unwrapping errors, maintain the continuity and error convergence of the phase unfolding process, and improve the overall data reliability.

[0018] 3. This invention establishes a real-time feedback path between data acquisition, phase operation, and quality assessment by utilizing a ring buffer module and a three-stage pipeline structure. The unwrapping result and the judgment signal are read and written in parallel through a dual-port buffer. The correction signal and the hold signal are transmitted synchronously between modules, enabling data processing to be performed continuously in the same clock domain. This design effectively reduces on-chip data latency and logic occupancy, enabling the system to achieve low-latency, high-precision real-time phase unwrapping under high-speed sampling conditions. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the stable group formation process of the present invention; Figure 2 This is a flowchart of the quality measurement and recalculation process of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] like Figures 1-2 As shown, this embodiment of the invention provides a time-axis phase unwrapping method based on FPGA to complete phase data access, stable reference selection, phase progressive development, pipeline processing, and quality measurement and recalculation control within the same FPGA chip. The processing flow can be executed sequentially according to the following steps. First, in the phase data acquisition stage, the interference signal collected by the distributed fiber optic sensing system is orthogonally demodulated, and the initial phase data arranged along the time axis is obtained by using the CORDIC algorithm. The initial phase data is written into the input buffer of the FPGA at a fixed sampling rate. The sampling rate is set synchronously with the system clock so that the input data and subsequent processing logic work in the same clock domain, avoiding timing inconsistencies between sampling and operation. Secondly, in the stable group forming link, the phase stability index and the amplitude stability index of the continuous period are jointly determined in the FPGA, the phase stability index and the amplitude stability index are calculated based on the phase change and the amplitude change in each period, when the phase stability index of a period is lower than the first threshold value, and the amplitude stability index is not lower than the second threshold value, the period is marked as a reliable period point; when the continuous number of reliable period points on the time axis is not less than the preset group length, the continuous interval is defined as a stable group, and the stable group is used as a reference for subsequent phase unwrapping. Then, in the phase progressive unwrapping link, the end period of the stable group is taken as the starting point, and the subsequent periods are processed along the time axis, when the phase difference between two adjacent periods is lower than the third threshold value, the phase difference is unwrapped in an accumulated manner; when the phase difference is not lower than the third threshold value, the phase change trend index and the amplitude change rate index of the adjacent periods are called in the FPGA to jointly determine whether the current period belongs to abnormal change: if the preset abnormal determination condition is met, the phase of the current period is corrected by ±2π; if the abnormal condition is not met, the phase value of the current period is kept unchanged, thereby reducing the influence of a single abnormal period on the whole phase sequence. In the pipeline and cache cooperative processing link, three pipeline comparators of input stage, comparison stage and determination stage are sequentially cascaded in the FPGA, the phase data and the determination result are read and written in parallel and circularly stored through the ring cache composed of double-port BRAM, the read and write pointers are circularly managed by the control logic according to the preset update strategy, so that the input, comparison calculation and determination output of the phase data can continuously flow in the same clock domain, while the read and write order relationship of the data of the previous and subsequent periods in the cache is ensured, which provides data support for phase progressive unwrapping and abnormal determination. Finally, in the quality metric closed-loop correction link, the time axis phase sequence after unwrapping is calculated, and the quality metric index including the error evaluation quantity such as mean square error index is calculated. When the quality metric index exceeds the fourth threshold value, the recalculation trigger signal is generated by the control logic in the FPGA, the partition for storing the intermediate calculation result in the ring cache is emptied, while the input data partition is kept unchanged, so that the system returns to the stable group forming link and the phase progressive unwrapping link to reselect reliable periods and unwrap the phase, through the recalculation control driven by the above quality metric, the phase unwrapping process is recalculated on demand without changing the original input phase data, forming an error feedback closed loop for time axis phase unwrapping.

[0022] Specific steps of phase data acquisition are as follows: The FPGA demodulation unit is a circuit unit arranged in the on-chip logic area of the FPGA chip and used for quadrature demodulation of the interference signal, and includes multiplication-addition operation logic, a CORDIC algorithm core and a register array, and can output time-axis continuous instantaneous phase data under a fixed sampling frequency. The interference signal collected by the distributed optical fiber sensing system is converted into two voltage signals after photoelectric conversion: in-phase channel voltage and quadrature channel voltage , both in volts (V). To realize high-speed real-time demodulation, the two signals are directly input into the on-chip demodulation unit of the FPGA, which is composed of multiplication-addition operation logic, a CORDIC algorithm core and a register array and arranged in the on-chip logic area of the FPGA. Generation of in-phase and quadrature components The FPGA demodulation unit performs on-chip multiplication-addition operation logic on the input voltage signal to generate normalized in-phase and quadrature components. The normalization coefficient takes the maximum amplitude of the input signal , ensuring that the numerical range is between [-1, 1]; The multiplication-addition logic adopts a two-stage pipeline structure, processing one sampling point per system clock cycle, and the sampling frequency is not higher than half of the system clock to ensure timing stability. CORDIC polar coordinate conversion The in-phase and quadrature components output by the multiplication-addition logic are sent to the CORDIC (Coordinate Rotation Diqital Computer) algorithm core. The CORDIC module iteratively calculates the phase angle through shifting and table lookup operations, and the calculation relationship is: , where represents the instantaneous phase value at the corresponding sampling time, in radians (rad). The CORDIC algorithm core in the FPGA uses 16 iterations to achieve a phase accuracy , and the output result is obtained on-chip without the participation of CPU or DSP, thereby avoiding external bus delay. Cache structure and timing synchronization To ensure the time continuity of the phase data, the instantaneous phase data is first temporarily stored in a level-1 register and then written into the input cache area in the FPGA, The input cache area is composed of a dual-port RAM (BlockRAM), one port for writing and one port for reading, with a storage depth of N=2^10 sampling points and a bit width of W=16 bits. The write port is controlled by the sampling clock. The driver reads the port via the system clock. control; The sampling clock and the system clock are synchronized in phase through the FPGA's built-in phase-locked loop (PLL), and the phase-locking deviation is controlled. Keep it within 10^-6 radians. The clock frequency difference satisfies: This design ensures that write and read operations are completed under a unified timing reference, eliminating the risk of phase drift caused by cross-clock domains; Data transfer and collaboration logic The output of the input buffer is connected to the phase filtering unit (subsequent stable group formation module); when the amount of data in the buffer reaches the preset sampling window length... Nw= 1024 When a sampling point is reached, the read pointer is activated, and data is sequentially fed into the subsequent logic. This architecture allows phase demodulation, buffer writing, and phase filtering to flow continuously within the same clock domain. A data stream-level collaborative processing mechanism is established to ensure that the overall system data latency does not exceed two sampling cycles; The core hardware implementation of the CORDIC algorithm is carried out on an FPGA chip, and combined with on-chip multiply-accumulate logic and dual-port BRAM cache, it realizes a fully hardware pipelined processing from input signal to instantaneous phase output. Furthermore, by using PLL phase-locked loop and unified clock domain design, data sampling and processing are ensured to be performed under the same phase reference, avoiding the phase jitter and data delay problems that occur in traditional systems with multiple clock domains.

[0023] The specific steps for the formation of a stable group are as follows: The decision logic circuit inside the FPGA performs statistical calculations and parallel comparisons on phase and amplitude data to identify continuous and stable segments of the signal on the time axis, forming a reference group for subsequent phase expansion. Input data and unit composition The input buffer sequential output sampling window length is Phase data sequence With amplitude data sequence , in Here is the sampling point index, and the sampling interval is... The unit is seconds. The decision logic circuit inside the FPGA consists of the following units: Statistical calculation unit: calculates the phase change and amplitude change between adjacent sampling points; Threshold comparison unit: compares the calculated result with the first threshold in the register. With the second threshold Perform parallel comparisons; Control logic: generate reliable flag according to comparison result and monitor continuity Group index register: record the start address of each stable group and end address ; All the above units are fixed-point logic structure, working in the same clock domain as the demodulation module Phase and amplitude stability index calculation Statistical calculation unit calculates in each sampling window: , , And calculate the phase and amplitude stability index: , , In the formula, the summation symbol represents point-by-point accumulation in the sampling window, using 16-bit fixed-point precision operation : the instantaneous phase of the th sampling point, unit rad : the amplitude of the th sampling point, unit V : phase change, unit rad : amplitude change, unit V : phase stability index unit rad² : amplitude stability index, unit V² : threshold parameter, same unit as above ; sampling window length, unit, number of sampling points : stable group length threshold, unit, number of sampling points The smaller the value, the more stable the phase, The smaller the value, the smaller the amplitude fluctuation and the higher the signal quality; threshold determination and reliable flag generation and are sent to the threshold comparison unit respectively, and compared with , in the threshold register When and , the control logic identifies the current sampling point as a reliable point ; Otherwise, it is identified as an unreliable point ; All are written in the reliability register array in sequence to form the reliable flag sequence Stable group detection and index recording When the number of consecutive "1"s is detected to reach the preset group length threshold (typically 16-64 sampling points); The control logic triggers the group index register to record the start address of the section and the end address ; The addresses are in units of sampling point numbers, with a count step of 1; The group index table also includes a valid flag Validflag indicating the validity of the current group data; Timing coordination and output interface The statistical calculation, threshold comparison, and group detection unit work in a pipeline manner under a unified system clock; Every time a new stable group index information is generated, the control logic synchronously sends the index information to the input register of the phase progression unwinding unit through the bus, forming a continuous path from the input buffer to the decision logic to the group index to the unwinding unit; The joint determination of the phase stability index and the amplitude stability index is adopted, and parallel comparison logic is implemented in FPGA, which can generate stable group indexes in real time at the hardware layer, eliminating software processing delay. In addition, by setting group index registers in FPGA, stable groups can be directly addressed, thereby forming an automatic data transfer mechanism in the hardware pipeline, improving the determinism and real-time performance of the overall system.

[0024] The specific steps of phase progression unwinding are as follows: The phase progression unwinding unit in FPGA takes the phase value at the end of the stable group as the unwinding starting point and continuously unwinds the phase data along the time axis to restore the phase continuity across cycles; The unwinding starting point and input data The end address recorded in the stable group index register is loaded into the phase progression unwinding unit as the unwinding starting point, and the phase unwinding unit sequentially reads the phase data and amplitude data of the sampling sequence from the input buffer. Each cycle corresponds to a sampling point index, and the time interval is the sampling period (seconds), and the phase unwinding logic runs independently in FPGA, with input and output being phase-locked synchronized with the previous module; Phase difference calculation and determination The phase unwinding unit calculates the phase difference between two adjacent sampling periods and compares it with the third threshold value stored in the threshold register, which is used to determine whether the phase difference crosses a cycle (usually π radians); When the phase difference is less than the third threshold value, the system considers that the phase change between the current cycle and the previous cycle is continuous, The phase difference is accumulated to the unwrapping phase sequence, so that the phase value keeps continuous growth along the time axis; When the phase difference is not less than the third threshold value, the system considers that the phase jumps, triggering the abnormality determination logic; Abnormality determination and correction When the abnormality determination logic is triggered, the phase progressive unwrapping unit reads the phase data and amplitude data of three periods before and after the current period from the cache area, calculates the change trend and amplitude change rate, and when it is detected that the phase change direction is consistent and the amplitude change rate does not exceed the amplitude change threshold value, it is considered that the jump belongs to period flipping, and the phase value of the current period is corrected by the control logic, that is, the original phase value is increased or decreased by a complete period angle (2π radians), so as to ensure the continuity of the phase curve on the time axis, and if the trend does not meet the correction condition, the current phase value is kept unchanged; Unwrapping result output and cache connection The unwrapped and corrected phase data are output to the output partition of the cache area according to the sampling order.

[0025] The output partition adopts a dual-port RAM structure and is written by the unwrapping unit, and the subsequent quality metric and closed-loop correction module reads the unwrapping result from the cache area to calculate the quality, so as to ensure the consistency of the timing, and the cache area reading and writing operations are operated under a unified system clock; Module timing coordination The phase difference calculation, jump determination and correction logic form a three-stage pipeline in the FPGA in sequence, each stage is delayed by one clock cycle, the continuous data stream is unwrapped, all operation logics are in the same clock domain, the phase drift caused by cross-domain delay is avoided, the threshold parameters and trend determination conditions can be configured through registers, so that the system can dynamically adjust the unwrapping sensitivity and accuracy according to the signal-to-noise ratio of the interference signal; The double-dimensional joint determination mechanism and hardware-level correction logic are realized in the FPGA, the jump property is determined by the trend and amplitude change of the previous and subsequent periods, the false correction is reduced, the correction operation is completed in the hardware logic layer without the participation of software, the response speed reaches the nanosecond level, and the parameter threshold values can be configured in real time, so that the system adapts to different signal conditions.

[0026] In order to realize high-speed flow unwrapping and real-time synchronization of phase data in the FPGA, the three-stage pipeline structure is constructed in the FPGA logic, and the double-port ring cache area is combined to realize parallel reading and writing and cyclic storage of phase data and determination results, so as to ensure that all processing links continuously run in a unified clock domain; Three-stage pipeline structure The pipeline structure includes an input stage, a comparison stage and a determination stage along the data path, and the stages are connected through registers, and the registers are used to latch data at each clock edge to maintain the continuity of the timing; Input stage: responsible for receiving phase data stream from phase progressive unwrapping module, latching data and passing to next stage; Comparison stage: performs adjacent cycle phase difference calculation and criticality determination, providing input for subsequent decision logic; Decision stage: generates decision signal (including "stable" and "needs correction" flags) based on comparison result, and outputs synchronously with phase data; All three stages work under unified system clock, each delayed by one clock cycle, realizing continuous data stream processing; Structure and operation logic of ring buffer Phase data and corresponding decision result output by decision stage are written into ring buffer composed of on-chip dual-port BRAM of FPGA simultaneously; The buffer is divided into input partition, temporary storage partition and output partition, each of which can be accessed through independent address pointer; The buffer is provided with read pointer (ReadPtr) and write pointer (WritePtr), which are independently incremented under unified clock control; At each rising edge of system clock, the write pointer moves to the next storage address to receive new phase data; The read pointer moves to output data at the same pace as the subsequent module, and when the interval between the write pointer and the read pointer reaches one less than the buffer depth, the write pointer returns to the starting address to overwrite the old data, thus realizing cyclic writing; The buffer management logic monitors the pointer interval in real time, and when it detects that the interval of data not yet read is approached by the write pointer, it automatically suspends the writing operation to prevent data overwrite; Through this mechanism, phase data and decision result can be read and written in parallel in the same storage body, forming a continuous data path; Data synchronization and module connection The output end of the buffer is connected to the quality metric and closed-loop correction module; Under unified clock domain, the phase data and decision flags output by the buffer are read synchronously by the subsequent module and error metric calculation is performed, ensuring that phase unwrapping, data buffering and error correction run continuously in time dimension, forming a real-time feedback closed loop; All signal transmission is completed within the FPGA, avoiding external bus transmission delay, so that the system can still maintain stable and lossless phase unwrapping data stream under high sampling rate conditions; Parallel pipeline cascade design: input, comparison and decision three-stage logic are triggered continuously under the same clock domain, eliminating the problem of traditional software or multi-module synchronization delay, ensuring the integrity of the timing chain; Double-port ring buffer structure: through double-port BRAM to support simultaneous read and write operations, phase data and determination flag are bound to output, data flow is uninterrupted, and real-time streaming cache is realized in a true sense; Pointer distance self-monitoring mechanism: read-write interval detection and write protection logic are added in hardware logic, Prevent buffer data from being overwritten in advance, thereby guaranteeing the reliability of the unwrapping result; Unified clock domain cooperation mechanism: all pipeline and cache modules run under a single clock signal, Eliminate phase drift and synchronization distortion caused by cross-clock-domain transmission; In summary, the pipeline and cache cooperation structure of the application not only ensures the timing continuity and storage stability of the unwrapping process, but also realizes high-bandwidth, low-delay phase data streaming transmission at the hardware level, which has obvious speed advantage and robustness improvement compared with the traditional architecture.

[0027] In this embodiment, to realize real-time precision detection and error self-correction of the phase unwrapping result, the application introduces a quality metric and closed-loop correction mechanism in the FPGA; This mechanism realizes real-time evaluation of the unwrapping result quality through hardware logic without relying on external CPU or software control, and automatically triggers recalculation when detecting that the error exceeds the threshold, realizing adaptive closed-loop control at the hardware level; Collection and calculation of quality metric parameters The phase unwrapping sequence output by the ring buffer area is read in sequence according to the sampling window, and each window contains a fixed number of sampling period points; The window length is set by a parameter register and can be dynamically adjusted according to the system sampling rate; The statistical calculation unit performs difference operation on the phase sequence in each window to calculate the phase change between adjacent sampling points; These changes are used to evaluate the smoothness of the phase change in the current window, and then the calculation unit generates a quality metric parameter to reflect the overall stability and continuity of the phase unwrapping; In this embodiment, the main quality metric parameter is mean square error (MSE), which is used to measure the average deviation degree of the phase change in the window; Optionally, the system can also calculate auxiliary indicators such as phase mutation rate and amplitude consistency ratio at the same time to realize multi-dimensional evaluation of the unwrapping result, and these parameters generate a comprehensive quality index through register weighting for subsequent recalculation determination; Recalculation trigger logic and signal generation The quality metric module compares the comprehensive index of each window with a fourth threshold value stored in a threshold register; when the quality indexes of two consecutive sampling windows are both higher than the threshold value, the control logic generates a single-cycle high-level pulse signal as a recalculation trigger signal; To avoid false triggering caused by transient noise, the system also detects whether the amplitude change rate is lower than the amplitude threshold value before generating the recalculation signal; only when the consecutive over-limit and the stable amplitude change are detected, the recalculation signal is confirmed and sent to the cache management unit; Cache recalculation and data backflow control After receiving the recalculation trigger signal, the cache management unit performs recalculation control in the following order: Emptying the temporary storage partition: clearing the temporary area data in the cache for storing intermediate expansion results; Preserving input data: the original phase sequence and amplitude data in the input partition are not affected, ensuring that the recalculation process is re-executed based on the original signal; Maintaining parameter register settings: all threshold values, weights and timing parameters remain unchanged to avoid reconfiguring delays; Triggering backflow execution: the control logic issues a recalculation instruction signal through the internal bus, and activates the "stable group formation module" and the "phase progressive expansion module" to re-expand the phase sequence in a unified clock domain; After the new phase expansion result is generated, it will overwrite the original temporary area data and be written back to the cache output port for the quality metric module to detect again; Closed-loop feedback mechanism The above process forms a complete hardware-level closed-loop path: Forward path: phase expansion module outputs phase sequence → cache area → quality metric module; Feedback path: quality metric module calculation result → recalculation trigger signal → cache management unit → phase expansion module; Through this closed-loop feedback, the system can achieve adaptive correction between data acquisition, expansion and quality evaluation, so that the phase data remains continuous and stable for a long time; The entire process is completed entirely within the FPGA internal logic unit, without the need for CPU intervention or external clock coordination, greatly improving the real-time performance and stability of the unwinding process; The closed-loop correction mechanism of the present application has the following unique technical features: Hardware-level real-time quality evaluation: quality parameters are calculated in a streaming manner on the FPGA chip, with a response speed of milliseconds; Dual-condition triggering mechanism: both consecutive over-limit and stable amplitude change are detected to ensure reliable recalculation triggering; Partitioned cache backflow control: local intermediate data is emptied and original data is preserved, reducing calculation delay; Clock domain unified design: all logic runs under a unified system clock, avoiding cross-clock drift and data synchronization problems; The design effectively avoids problems such as incorrect correction, excessive delay or calculation blocking in traditional schemes, and realizes high-precision and sustainable phase unwrapping closed-loop control, and has outstanding technical effects and creativity.

[0028] The application also provides a time-axis phase unwrapping system based on FPGA, which is based on the above method, and the system comprises: A phase demodulation module is used for quadrature demodulation of the interference signal and output of time-axis initial phase data; An FPGA unwrapping module comprises a reliable period screening unit, a phase progressive unwrapping unit, an abnormality judging unit, a quality metric and recalculation control unit, and a three-stage pipeline comparator coupled therewith; A ring buffer module is composed of an on-chip dual-port BRAM, and comprises an input partition, a temporary storage partition and an output partition, and is used for parallel reading and writing and cyclic storage of phase data and judgment results in the unwrapping process; A control and clock module is used for providing system clock, threshold and window parameters, recalculation trigger signal, and timing synchronization control of reading and writing pointers and pipeline inter-stage registers; The FPGA unwrapping module and the ring buffer module are bidirectionally coupled through a correction signal and a holding signal: the abnormality judgment result is used to guide the phase correction of the unwrapping unit, and is output to the quality metric and recalculation control unit to participate in online adjustment of the threshold and window parameters, forming an algorithm-hardware cooperative closed loop.

[0029] The time-axis phase unwrapping system based on FPGA comprises four main modules: a phase demodulation module, an FPGA unwrapping module, a ring buffer module and a control and clock module; each module is arranged in a logic region of the same FPGA chip, signal transmission, data interaction and unified timing synchronization are realized through an on-chip AXI bus and control registers, and the whole system forms a continuous flow type data processing path from interference signal collection to phase unwrapping output; The phase demodulation module The phase demodulation module is used for receiving in-phase channel signals and quadrature channel signals output by a distributed optical fiber sensing system, and comprises a multiplication-addition logic unit and a CORDIC algorithm core inside; the multiplication-addition unit performs quadrature demodulation operation on the two signals, and the CORDIC algorithm core is responsible for converting the signals in rectangular coordinate form into polar coordinate form and outputting corresponding instantaneous phase values; The module adopts a pipeline design, calculates a phase value of a sampling point in each system clock cycle, writes the calculation result into an input buffer area after temporary storage through a first register, and forms a time-axis initial phase data sequence, thereby providing input for a subsequent unwrapping module. FPGA unwrapping module The FPGA unwrapping module is a core operation unit of the system, responsible for performing phase screening, progressive unwrapping and error correction on initial phase data; The module is composed of the following sub-units: Reliable period screening unit: performs stability determination on the initial phase sequence, eliminates noise periods, and forms a reliable data set; Phase progressive unwrapping unit: continuously unwraps phase values in the time axis direction to achieve phase compensation at the period level; Abnormality determination unit: detects jump points and corrects them according to trend and amplitude change characteristics; Quality metric and recalculation control unit: determines whether to trigger a recalculation instruction based on the error indicator calculation result returned by the buffer area; The entire unwrapping module runs in a parallel pipeline manner inside the FPGA, and the sub-units exchange data synchronously through registers. The phase screening, unwrapping and correction processes are continuously completed in the same system clock domain; Ring buffer module The ring buffer module is composed of a dual-port BRAM, which is divided into an input partition, a temporary storage partition and an output partition. The input partition is used to store the initial phase data from the phase demodulation module. The temporary storage partition stores the intermediate unwrapping results. The output partition is used to output the final unwrapping phase values to the quality metric module and external interface; The buffer area controls data flow through read and write pointers, which are incremented synchronously at the clock rising edge, When the interval between the write pointer and the read pointer reaches the upper limit of the preset buffer depth, the write pointer returns to the starting address, realizing cyclic writing; When the quality metric module triggers a recalculation signal, the buffer management logic only empties the temporary storage partition, retaining the input partition data, so that the system can quickly re-unwind and ensure real-time performance; Control and clock module The control and clock module provides a unified clock signal and parameter management function for the system. This module includes a phase-locked loop (PLL), a clock distribution network and a parameter register group; The phase-locked loop is used to stabilize the system main clock and distribute the clock signal to each module; The parameter register group is used to store the threshold values, sampling window length and weight coefficients required for unwrapping; The control logic writes parameter values at the clock rising edge through the on-chip bus and dynamically adjusts the threshold register content according to the feedback signal from the quality metric module, ensuring that each module runs cooperatively under the same timing reference; Through the above control mechanism, the system can automatically optimize the unwrapping parameters when noise environment or signal changes are detected, thus realizing adaptive operation; Module collaboration relationships and data paths The four modules collaborate bidirectionally via data lines and a control bus, forming the following two logical paths: Master data path: Interference signal input → Phase demodulation module → FPGA unwrapping module → Ring buffer module → Quality measurement and closed-loop correction module; Feedback control path: Quality Measurement Module → Control and Clock Module → FPGA Unwrapping Module and Buffer Module; This dual-path design enables the system to provide real-time feedback, automatically adjusting parameters and re-unfolding when the error exceeds the threshold, achieving continuous self-correction and high-precision phase recovery. Unlike existing distributed fiber unwrapping systems that rely solely on external CPUs or independent DSPs, this invention achieves the following innovations through an integrated multi-module design within an FPGA: The entire signal chain is hardware-based: demodulation, unwinding, buffering, and control are all performed on the same chip, avoiding external bus delays; Closed-loop control architecture: The phase expansion results are fed back to the control module in real time to achieve dynamic error correction; Unified clock domain architecture: All logic runs under a single PLL output clock, eliminating cross-domain phase drift; Adaptive parameter update mechanism: The parameter register is automatically adjusted based on real-time feedback to enhance system robustness; These features together ensure the system's high real-time performance, scalability, and long-term stability, effectively solving problems such as large latency, synchronization errors, and fixed parameters in traditional systems.

[0030] The FPGA unwrapping module is the core computing and control unit of the system. This module consists of five functional units connected in sequence: a reliable cycle screening unit, a phase progressive development unit, an anomaly detection unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparison unit. All units exchange signals and parameters with the register group through the on-chip bus and operate synchronously under the same system clock to ensure the real-time performance and data consistency of the unwrapping process; Reliable Periodic Screening Unit This unit is used to filter out stable periods from the input raw phase and amplitude data. Its inputs are: the phase data sequence, amplitude data sequence, sliding window length and threshold parameters output by the demodulation module; The processing flow is as follows: Within a set window length, calculate the phase change and amplitude change between consecutive sampling points; Statistical phase changes in the window fluctuation (by calculating the average and dispersion of changes), and at the same time, the stability of the amplitude change; If the phase fluctuation is less than the first threshold and the amplitude stability is not less than the second threshold, it means that the interval data is stable, and the system writes "reliable flag" at the corresponding address position; When the number of consecutive reliable flag bits reaches the preset group length, the system automatically defines the continuous data segment as a "stable group", and records the start position and end position in the group index register. This information will be used as a reference interval in the subsequent phase unwrapping process; The output results include: address index of stable group and corresponding reliable flag sequence. This screening process uses a hardware implementation of register plus accumulator, does not involve complex mathematical models, and is suitable for the parallel pipeline structure of FPGA; Phase progressive unwrapping unit This unit unwraps the phase point by point on the time axis based on the reliable period; The input includes: stable group index, original phase data, amplitude data, and third threshold and tolerance parameters; The processing flow is as follows: Take the end point of the stable group as the starting position, and read the phase values of adjacent samples in turn; Compare whether the phase change between adjacent samples is less than the set third threshold: If the change is less than the threshold, it is considered that the phase is continuous, and it is directly added into the unwrapping result; If the change is greater than or equal to the threshold, read the data of several samples before and after this point, and judge whether the phase change trend is continuous, and whether the amplitude change is within the tolerance range; If the trend direction reverses, but the amplitude change is still stable, the system considers that a period jump has occurred, and automatically performs a period angle compensation (equivalent to adding or subtracting a complete period of phase value) in hardware; otherwise, keep the current result unchanged; The final unwrapped phase data is written in the output partition of the cache module in time sequence for use by the subsequent quality evaluation unit; This unit realizes the phase continuity correction mechanism, and avoids the phase fault problem caused by turning back or drifting in traditional algorithms; Abnormality judgment unit This unit is used to identify abnormal jump points in the unwrapping process. The input signals include phase change results, amplitude change results, third threshold and tolerance parameters; The processing steps are as follows: The first channel is used to detect whether the phase change exceeds the third threshold. If it does, output a "phase jump signal"; The second channel is used to detect whether the amplitude variation exceeds the tolerance range, and outputs an "amplitude abnormal signal" if it does; The control logic comprehensively judges the results of the two channels: If only phase jump occurs and the amplitude is normal, the abnormal flag is output in the active state; If both are abnormal, the abnormal flag is not triggered immediately, but a short-term delay monitoring is started, and the confirmation is made again in a continuous number of sampling periods; If only the amplitude is abnormal but the phase is continuous, it is considered to be noise disturbance, and the abnormal signal is not triggered; Through the determination mechanism, the real phase foldover and the pseudo-jump caused by noise can be distinguished, and the reliability of the unwrapping data is ensured; Quality measurement and recalculation control unit This unit continuously evaluates the overall quality of the unwrapping result during system operation, and automatically triggers recalculation according to the evaluation result; The inputs include: unwrapped phase data, preset sampling window length, and fourth threshold value.

[0031] The processing flow is as follows: The system performs quality analysis on the phase data in a sampling window of a set length, including but not limited to: The average deviation of phase fluctuation; The proportion of phase jump exceeding the threshold value; The synchronization consistency between phase variation and amplitude variation; The above results are combined into a quality index value according to the weight; If the quality index of the continuous two evaluations is higher than the fourth threshold value, the system outputs a recalculation trigger signal; After receiving the recalculation signal, the cache management logic will clear the data in the intermediate calculation area, but the original input data and parameter settings are retained, and the stable group screening and phase unwrapping process is re-executed; The new unwrapping result replaces the old result, forming an automatic closed-loop correction process; This mechanism ensures the long-term stability of the unwrapping process, and enables the system to have self-correction ability; Three-stage pipeline comparison unit To ensure that the data comparison and judgment between units are performed in a fixed time sequence, the system constructs a three-stage pipeline comparator structure in the FPGA; The first stage is the input comparison stage, which is responsible for parallel comparison of the current phase and amplitude data with each threshold parameter; The second stage is the trend comparison stage, which is responsible for analyzing the change direction and amplitude trend of the continuous period data; The third stage is the comprehensive decision stage, which generates the final determination result in combination with the results of the previous two stages and the abnormal flag signal; Each stage is connected sequentially through registers and triggered by the rising edge of the system clock, ensuring that data transmission and judgment are synchronized and that there is no cross-clock delay or signal jitter. Unlike existing CPU or DSP-based untangling algorithms, this invention implements all calculation processes in hardware logic. Reliable periodic screening, progressive development, anomaly detection, quality measurement and recalculation are all completed in parallel pipeline within the FPGA, and data is transmitted without leaving the chip. This structure achieves true real-time phase unwrapping and has the following significant advantages: No software iteration is required, and the response time is only in the microsecond range. The threshold register can be dynamically configured to adapt to different sensing scenarios; A fixed delay and continuous output are maintained through a three-stage pipelined comparator; A complete hardware closed-loop feedback structure was formed, which effectively suppressed noise and drift. The design of this embodiment achieves synergy in the logic layer, timing layer, and storage layer, which not only improves the untangling accuracy but also enhances the system robustness, demonstrating significant innovative features.

[0032] Among them, a bidirectional communication mechanism is set between the FPGA unwrapping module and the ring buffer module to form real-time collaborative feedback between the algorithm control logic and the hardware execution unit. This mechanism is implemented through two types of signals: one is a "correction signal" used for instruction phase adjustment; the other is a "hold signal" used to lock the buffer area during correction to prevent data overwriting. Together, they form a closed-loop control link for phase filtering, unwrapping and quality evaluation. Two-way communication and signal interaction mechanism Correction signal generation and transmission When the anomaly detection unit inside the FPGA unwrapping module detects a continuity interruption, abrupt change, or reversal in the phase unfolding result, it immediately generates a correction signal. The correction signal is transmitted to the phase progressive unfolding unit via the on-chip control bus to trigger its internal phase compensation logic. The compensation logic performs data correction in the next clock cycle, adjusting the phase value corresponding to the anomaly to a reasonable range. The adjusted result is rewritten to the output partition of the ring buffer module, overwriting the original abnormal data. Maintain signal triggering and recovery While the correction signal is generated, the anomaly detection unit outputs a hold signal to the ring buffer module; while the hold signal is high, the read and write pointers of the buffer area stop incrementing, locking the current buffer page to prevent data from being overwritten by new samples during the correction period; Once phase compensation is complete, the system automatically clears the hold signal, restores the normal incrementing state of the read / write pointer, and allows the buffer to re-enter the loop for read / write. The double signal mechanism ensures that the correction process and the data access process are always synchronized under high-speed data flow, without causing timing disorder or data loss. Parameter dynamic updating and feedback path During the action of the correction and maintenance signals, the ring buffer module synchronously sends trigger pulses to the quality metric and recalculation control unit; After receiving the pulses, the quality metric and recalculation control unit recalculates the parameters suitable for the current state, including the phase determination threshold and the sliding window length, according to the error distribution of the current unwrapping result and the data stability; The new threshold parameters and window length are written into the threshold register and window parameter register in the FPGA in real time, which are connected with the phase filtering unit and the phase unwrapping unit, ensuring that the new parameters take effect immediately in the subsequent data processing process; the entire parameter updating and writing back process is completed completely inside the FPGA, with a delay of only a few clock cycles, without the need for external controller participation; When the error evaluation module detects that the phase change rate continuously exceeds the preset stable interval, the system automatically increases the upper limit parameter in the threshold register and appropriately increases the window length; when it detects that the data is continuously stable, the system automatically reduces the threshold and shortens the window length; This real-time adaptive mechanism can dynamically adjust the judgment standard according to the signal noise environment, so that the system can maintain reliable unwrapping output under different interference conditions; Hardware closed-loop execution process The above-mentioned bidirectional signal and parameter updating logic jointly constitute a hardware feedback path inside the FPGA; The working process is as follows: The abnormality determination unit finds an abnormality and sends a correction signal; The phase progressive unwrapping unit immediately performs phase correction, and the maintenance signal is activated to freeze the buffer area; The ring buffer module suspends data updating and waits for the correction to be completed; The quality metric and recalculation control unit receives the synchronous trigger pulse and performs real-time evaluation, and generates new parameter values; The new parameter values are written back to each unwrapping unit through the register; The maintenance signal is released, the buffer resumes operation, and enters the next data processing period; Through the hardware closed-loop structure, the system realizes complete synchronization of abnormality detection, data correction, parameter updating and buffer management, ensuring real-time continuous output under high-speed sampling conditions; Bidirectional signal interaction: The invention designs correction signals and maintenance signals to realize bidirectional synchronization control of the unwrapping module and the buffer module, and the traditional technology is mostly in a one-way data output mode, lacking immediate feedback capability; Parameter adaptive update: The system can automatically adjust the threshold and window length according to real-time data quality, which is different from the existing fixed threshold or static judgment method; Full-frame closed loop implementation: The whole process from anomaly detection to parameter update is completed in the FPGA logic, without the need for external CPU participation, and the response time is controlled within microseconds, significantly improving real-time performance; Hardware level synchronization control: The three types of signals, correction, maintenance and evaluation, are triggered by on-chip clock synchronization to ensure execution under the same timing reference and eliminate cross-clock domain interference; This structure is not a simple improvement of existing algorithms, but a new FPGA hardware adaptive control system with clear technical progress points.

[0033] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0034] Although embodiments of the present application have been shown and described, it will be understood by those having ordinary skill in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based time series phase unwrapping method, characterized in that: The specific steps of the method are as follows: Phase data acquisition: the interference signal collected by the distributed optical fiber sensing system is quadrature demodulated, the CORDIC algorithm is used to obtain the initial phase data on the time axis, and the phase data is written into the FPGA input buffer at a fixed sampling rate, the sampling rate is synchronized with the system clock; Stable group formation: the phase stability index and the amplitude stability index of the continuous period are jointly determined in the FPGA; when the phase stability index is lower than the first threshold value and the amplitude stability index is not lower than the second threshold value, the period is marked as a reliable period point; when the number of continuous reliable period points is not less than the preset group length, a stable group is formed as the unwinding reference; Phase progressive unwinding: starting from the end period of the stable group, the periods are processed along the time axis; when the phase difference between adjacent periods is lower than the third threshold value, cumulative unwinding is performed; When the phase difference is not lower than the third threshold value, the phase change trend index and the amplitude change rate index of the adjacent periods are jointly determined: if the abnormal determination condition is met, the ±2π correction is performed, otherwise the current phase value is kept unchanged; Pipeline and buffer cooperative processing: three pipeline comparators of input stage, comparison stage and determination stage are cascaded in the FPGA; the phase data and the determination result are read and written in parallel and stored in a circular buffer composed of double-port BRAM, and the read and write pointers are cyclically managed by the control logic according to the preset update strategy; Quality metric closed-loop correction: the quality metric index of the unwound phase sequence is calculated, and when the index exceeds the fourth threshold value, the control logic sends a recalculation trigger signal, clears the intermediate result partition of the buffer and retains the input partition data, and returns to the stable group formation and phase progressive unwinding for reselection and unwinding.

2. The FPGA-based time series phase unwrapping method of claim 1, wherein: The specific steps of the phase data acquisition are as follows: The FPGA demodulation unit receives the in-phase channel and quadrature channel voltage values of the interference signal output by the distributed optical fiber sensing system, respectively generates quadrature components and in-phase components through on-chip multiplication and addition operation logic, and then converts the components into polar coordinates by using the CORDIC algorithm to obtain the instantaneous phase of each sampling point; The instantaneous phase is temporarily stored in a first-level cache register and then written into the FPGA internal input buffer area; the input buffer area is composed of a double-port storage unit, the write end is driven by the sampling clock, and the read end and the subsequent phase selection unit work synchronously in the same system clock domain; the sampling clock and the system clock are phase-locked through a clock distribution network, ensuring that the sampling interval is constant and that data writing and reading are performed under the same timing reference.

3. The FPGA-based time series phase unwrapping method of claim 2, wherein: The specific steps of the stable group formation are as follows: The determination logic circuit inside the FPGA receives the phase data and amplitude data of the input buffer area output by the phase data acquisition; The phase change amount and the corresponding amplitude change amount of adjacent periods are extracted in a preset sampling window, the phase stability index and the amplitude stability index of each period are obtained through a statistical calculation unit, and the values of the two indexes are compared with the first threshold value and the second threshold value stored in the threshold register in parallel; When the phase stability index of a certain cycle is less than the first threshold value and the amplitude stability index is not lower than the second threshold value, a reliable flag bit is written at the cycle address position by the control logic; when the number of continuous reliable flag bits reaches a preset group length, the control logic identifies the data of the continuous address segment as a stable group and records the start address and end address thereof in the group index register, and the stable group index information is used as an input reference of a subsequent phase unwrapping unit.

4. The FPGA-based time series phase unwrapping method of claim 3, wherein: The specific steps of the phase progressive unwrapping are as follows: The end cycle of the stable group is taken as the unwrapping start cycle, the phase data of adjacent cycles are read along the time axis in sequence, the phase difference between adjacent cycles is calculated and compared with a third threshold value stored in a threshold register; When the phase difference is less than the third threshold value, the phase values are accumulated in time sequence; When the phase difference is not less than the third threshold value, the phase change trend data and amplitude change rate data of several cycles before and after the current cycle are read, and a joint judgment is made according to preset trend judgment conditions and amplitude change conditions: if the judgment result satisfies the correction condition, the phase value of the current cycle is corrected by cycle jump; if the judgment result does not satisfy the correction condition, the phase value of the current cycle is kept unchanged; The unwrapped phase data are output to a cache area in time sequence for subsequent quality measurement and closed-loop correction.

5. The FPGA-based time series phase unwrapping method of claim 4, wherein: The specific steps of the pipeline and cache cooperative processing are as follows: A three-stage pipeline structure connected in sequence by an input stage, a comparison stage and a judgment stage is formed in the FPGA, The phase data are sequentially processed in the input stage, the comparison stage and the judgment stage in sequence, and the data are sequentially transmitted between stages through registers to keep the time sequence consistent; The phase data and the judgment result output by the judgment stage are written into a ring-shaped cache area composed of double-port BRAM, the cache area is provided with a read pointer and a write pointer, the read and write pointers are cyclically moved according to a preset update rule at the clock beat, and when the interval between the write pointer and the read pointer reaches a preset cache depth, the cyclic coverage mode is automatically entered, so that the parallel reading and writing and continuous storage of the phase data and the judgment result are realized; The output end of the cache area synchronously transmits the unwrapped phase data of the current cycle to the subsequent quality measurement and closed-loop correction.

6. The FPGA-based time series phase unwrapping method of claim 5, wherein: The specific steps of the quality measurement and closed-loop correction are as follows: The unwrapped phase sequence output by the cache area is read in sequence according to a preset sampling window, the phase difference data in the window are obtained by a statistical calculation unit, and the corresponding quality measurement parameters are calculated, the quality measurement parameters including an error evaluation quantity reflecting the phase unwrapping accuracy; When the calculated quality measurement parameter exceeds a fourth threshold value stored in a threshold register, a recalculation trigger signal is generated by the control logic and sent to a cache management unit; After receiving the recalculation trigger signal, the cache management unit clears the intermediate results in the temporary storage partition, retains the original phase data in the input partition and the threshold setting in the parameter register, so that the system re-executes the stable group formation and phase progressive unwrapping process in the same clock domain. After the re-computation is completed, the new phase unwrapping result replaces the original temporary data and is output to the buffer area, thereby forming a continuous feedback loop between data acquisition, unwrapping computation and error evaluation.

7. An FPGA-based time series phase unwrapping system, characterized in that: The FPGA-based time series phase unwrapping system is based on the method of any one of claims 1-6, and the system comprises: a phase demodulation module for quadrature demodulating the interference signal and outputting time series initial phase data; an FPGA unwrapping module comprising a reliable period screening unit, a phase progressive unwrapping unit, an abnormality judging unit, a quality metric and re-computation control unit, and a three-stage pipeline comparator coupled therewith; a ring buffer module composed of on-chip dual-port BRAMs, comprising an input partition, a temporary storage partition and an output partition, for parallel reading and writing and cyclic storage of phase data and judgment results during unwrapping; a control and clock module for providing system clock, threshold and window parameters, re-computation trigger signals, and timing synchronization control of reading and writing pointers and pipeline stage registers; wherein the FPGA unwrapping module and the ring buffer module are bidirectionally coupled through correction signals and holding signals: the abnormality judgment result is used to guide the phase correction of the unwrapping unit, and is output to the quality metric and re-computation control unit to participate in the online adjustment of threshold and window parameters, forming an algorithm-hardware co-synergic closed loop.

8. The FPGA-based time series phase unwrapping system of claim 7, wherein: The phase demodulation module quadrature demodulates the interference signal to obtain time series initial phase data, the FPGA unwrapping module receives the initial phase data and performs phase screening, unwrapping and correction processing, the ring buffer module accesses phase data and judgment results during unwrapping, and the control and clock module provides uniform clock signals and threshold parameters for each module and realizes overall timing synchronization.

9. The FPGA-based time series phase unwrapping system of claim 8, wherein: The FPGA unwrapping module comprises a reliable period screening unit, a phase progressive unwrapping unit, an abnormality judging unit, a quality metric and re-computation control unit, and a three-stage pipeline comparator sequentially connected with the units; wherein the reliable period screening unit is used for continuous period screening of input phase data, the phase progressive unwrapping unit performs phase unwrapping calculation according to the screening result, the abnormality judging unit judges the phase change trend and amplitude change rate, the quality metric and re-computation control unit calculates quality parameters and generates re-computation trigger signals according to the judgment result, and the three-stage pipeline comparator sequentially transmits comparison results between the units to ensure consistent data processing timing.

10. The FPGA-based time series phase unwrapping system of claim 9, wherein: The FPGA unwrapping module and the ring buffer module are bidirectionally connected through correction signals and holding signals, the correction signal output by the abnormality judging unit is used to guide the phase adjustment of the phase progressive unwrapping unit, and the holding signal and the correction signal are simultaneously input to the quality metric and re-computation control unit to update real-time parameters in the threshold register and the window parameter register, so as to form an algorithm-hardware co-synergic feedback closed loop in the phase screening, unwrapping and quality metric processes.

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