Function waveform generation method and system based on expression compilation and adaptive segmented sampling

Abstract

According to the function waveform generation method and system based on expression compilation and adaptive segmented sampling, the combination of an upper computer, an ARM, an FPGA and a DAC is adopted, and the upper computer inputs a segmented function set and parameters; the ARM processor executes expression compilation and completes segmentation coverage degree and continuity verification; in each section, according to second-order difference curvature approximation, under the constraint of an error upper limit epsilon, adaptively determining a step length for sampling, then performing uniform resampling at a global equidistant position, and performing linear calibration and quantization according to y '= alphay + beta to generate a waveform lookup table; a DDS in the FPGA calculates a frequency control word FCW and a phase control word POW according to a work clock and a target frequency, a phase accumulator looks up a table to output a digital waveform, and finally the digital waveform is converted into an analog signal by a DAC. According to the scheme, the maximum error of the amplitude is controlled, meanwhile, the sample point and table scale is remarkably reduced, the bandwidth is reduced, the frequency and the phase are independently adjustable, and the expression ability and the freedom degree of waveform generation are greatly improved through a segmented expression.

Description

Technical Field

[0001] This invention relates to the field of signal generation and measurement and control technology, specifically to a method and system for generating function waveforms based on expression compilation and adaptive segmented sampling. Background Technology

[0002] Arbitrary Waveform Generators (AWGs) are widely used in scientific research and industrial testing. Existing waveform generation schemes commonly employ fixed-step uniform sampling and pre-defined lookup tables. However, for complex functions with peaks or high curvature regions, meeting amplitude error constraints requires a significantly increased global sampling rate, leading to a sharp increase in lookup data and transmission bandwidth. Conversely, reducing the sampling rate easily results in noticeable distortion. Furthermore, existing devices typically do not support direct input of piecewise function strings, lacking automatic verification of segment coverage, non-overlapping, and adjacent continuity, resulting in low waveform editing and debugging efficiency. Therefore, there is an urgent need for a general waveform generation method and system that can directly accept piecewise expression input, implement adaptive piecewise sampling and global uniform resampling under error upper limit constraints, and provide automatic segment consistency verification. This would reduce table size and bandwidth usage while ensuring waveform accuracy and increasing the degree of freedom in waveform generation. Summary of the Invention

[0003] This invention addresses the deficiencies or shortcomings of existing technologies by providing a method and system for generating function waveforms based on expression compilation and adaptive segmented sampling. This method reduces table size and bandwidth usage while ensuring waveform accuracy and increasing the degree of freedom in waveform generation.

[0004] The technical solution of the present invention is as follows:

[0005] A function waveform generation method based on expression compilation and adaptive segmented sampling is characterized by employing a host computer + ARM + FPGA + DAC combination. The host computer inputs the function string in segments according to its domain. The ARM side compiles the expression into a syntax tree, performs constant folding and domain consistency checks, and generates non-uniform samples by adaptive sampling according to curvature under an error upper limit constraint ε. Then, it uniformly resamples to construct a fixed-length waveform lookup table and completes linear calibration and fixed-point quantization. The FPGA side uses a DDS phase accumulator to read the waveform lookup table and outputs a digital waveform. The DAC converts the digital waveform into a function analog waveform signal.

[0006] Includes the following steps:

[0007] Step 1: Use the host computer to send the set of piecewise function expressions {f} to the ARM processor module. k (x),[a k ,b k]} and the following parameters: ε, Δx min Δx max N, B, W, A, f clk f out φ0, α, β, ε are the upper limit of error, and Δx is the sampling step size. min It is the minimum sampling step size, Δx max Where is the maximum sampling step size, N is the number of global uniform resampling points, B is the bit width of the digital-to-analog converter, W is the bit width of the phase accumulator, A is the bit width of the lookup table address, and f is the maximum sampling step size. clk Here, φ0 is the clock frequency, α is the initial phase, β is the first linear calibration parameter, and f is the second linear calibration parameter. k (x) is the string representing the k-th segment of the piecewise function, where k is the index, and a k It is the starting point of the kth segment, b k It is the end point of the k-th segment;

[0008] Step 2: The ARM processor module determines whether the piecewise function expression syntax / domain is valid. If not, it returns to Step 1; if yes, it proceeds to Step 3.

[0009] Step 3: The ARM processor module sequentially completes expression compilation, adaptive sampling, uniform resampling and calibration to generate a waveform lookup table, and writes the waveform lookup table into the FPGA module through the communication unit;

[0010] Step 4: The DDS unit in the FPGA module calculates the frequency control word FCW and the phase offset word POW according to the working clock and the target frequency, reads the waveform lookup table through the phase accumulator, forms a segmented sampled function digital waveform, and transmits the function digital waveform to the DAC module through the data bus.

[0011] Step 5: The DAC module converts the digital waveform of the function into an analog waveform signal and outputs it to the display screen of the host computer for display.

[0012] Step 3 includes the following expression:

[0013]

[0014] Where Δx0 is a quantity related to the value of Δx, if Δx0 < Δx min Then take Δx = Δx min If Δx0 > Δx max Then take Δx = Δx max Otherwise, take Δx = Δx0; thus, non-uniform sample points {(x) are obtained through adaptive sampling of Δx. i ,y i )};

[0015] f″(x) is the second-order difference approximation of the curvature of f(x), f(x) is a piecewise function, δ is a perturbation, δ>0, and h is a fixed fraction of the piece length.

[0016] Step 3 includes the following expression:

[0017]

[0018] where y′(u j ) is y(u j The first derivative of y(u) j ) is in the global interval [x min ,x max [Formed into N equally spaced positions u] j And for non-uniform sample points {(x i ,y i The uniformly resampled sequence obtained by interpolation is: code is the compiler operator, sat is the saturation operator, and round is the rounding operator.

[0019] Step 3 includes the following expression:

[0020]

[0021]

[0022] Where y l It is an equally spaced position u j The left adjacent sample point (x) l ,y l The y-axis coordinate value in ) and x l It is an equally spaced position u j The left adjacent sample point (x) l ,y l The x-axis coordinate value in ) r It is an equally spaced position u j The right adjacent sample point (x) r ,y r The x-axis coordinates and y-axis coordinates in the data are shown in the original text. r It is an equally spaced position u j The right adjacent sample point (x) r ,y r The y-axis coordinate value in ) and x min It is the global interval [x min ,x max The starting point in [], j is the ordinal number, x max It is the global interval [x min ,x max The endpoint in ].

[0023] Step 4 includes the following expression:

[0024]

[0025] The round operator is used for rounding from 4 to 5.

[0026] Step 4 includes the following expression:

[0027] Φ(n+1)=(Φ(n)+FCW)mod 2 W ,

[0028] Φ(n+1) is the phase accumulation value at the (n+1)th sampling time of the phase accumulator, Φ(n) is the phase accumulation value at the nth sampling time of the phase accumulator, n is the sampling time number, and mod is the modulo operator.

[0029] A function waveform generation system based on expression compilation and adaptive segmented sampling is characterized by being used to execute the aforementioned function waveform generation method based on expression compilation and adaptive segmented sampling.

[0030] include:

[0031] The host computer is used to input function strings in segments according to their domains and send parameters down.

[0032] The ARM processor module is used to compile function strings, perform constant folding and domain consistency checks, and perform adaptive sampling and uniform resampling under the upper limit of error ε to build a fixed-length waveform lookup table, and complete linear calibration and fixed-point quantization.

[0033] The FPGA module is used to read the waveform lookup table using the DDS phase accumulator and output the digital waveform. It can also achieve independent adjustment of frequency and phase based on the frequency control word FCW and the phase offset word POW.

[0034] A DAC module is used to convert digital waveforms into analog signals.

[0035] The host computer includes a frequency / phase input unit and a function input unit; the ARM processor module includes an expression compilation unit, an adaptive sampling unit, a uniform resampling unit, a calibrated quantization unit, and a communication unit; the FPGA module includes a DDS unit, a BRAM unit, and a clock divider unit.

[0036] The technical advantages of this invention are as follows: This invention is based on a function waveform generation method and system using expression compilation and adaptive segmented sampling. It employs a host computer + ARM + FPGA + DAC combination. The host computer inputs the function string in segments according to its domain. The ARM side compiles the expression into a syntax tree, performs constant folding and domain consistency checks, and generates non-uniform samples by adaptive sampling according to curvature under an error upper limit constraint ε. Then, it uniformly resamples to construct a fixed-length waveform lookup table and completes linear calibration and fixed-point quantization. The FPGA side uses a DDS phase accumulator to read the lookup table and outputs a digital waveform, which is then converted into an analog signal by the DAC. This invention can significantly reduce the required sampling points and improve waveform fidelity under the same error conditions, and supports independent adjustment of frequency and phase. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the function waveform generation system based on expression compilation and adaptive segmented sampling, which implements the present invention.

[0038] Figure 2 This is a schematic diagram of the function waveform generation method based on expression compilation and adaptive segmented sampling of the present invention. Figure 2 The process includes: Step 1, input to the host computer; Step 2, parameter distribution; Step 3, checking if the expression syntax / domain is valid. If not, return to Step 2; if yes, proceed to Step 4; Step 4, expression compilation and segment table generation; Step 5, adaptive sampling; Step 6, uniform resampling; Step 7, calibration; Step 8, the ARM writes the waveform lookup table to the BRAM (ARM, Advanced RISC Machine; BRAM, Block RAM); Step 9, writing FCW and POW, and DDS lookup table (FCW, Frequency Control Word; POW, Phase Shift Word; DDS, Direct Digital Synthesis); Step 10, the DAC outputs the analog waveform (DAC, Digital-to-Analog Converter).

[0039] The reference numerals in the attached diagram are listed below: 1-Host computer (sends segmented function strings and control parameters); 2-Frequency / phase input unit; 3-Function input unit; 4-ARM processor module (receives segmented function strings and control parameters, sends waveform lookup tables, ARM, Advanced RISC Machine); 5-Expression compilation unit; 6-Adaptive sampling unit; 7-Uniform resampling unit; 8-Standardization unit; 9-Communication unit; 10-FPGA module (FPGA, Field Programmable Gate Array, sets FCW and POW through DDS, outputs digital signals, i.e., digital waveforms, based on waveform lookup tables); 11-DDS (FCW / POW) unit (FCW, Frequency Control Word; POW, Phase Shift Word; DDS, Direct Digital Synthesis); 12-BRAM unit (BRAM, Block RAM); 13-Clock divider unit; 14-DAC module (receives digital signals, outputs analog signals, DAC, Digital-to-Analog). Converter (digital-to-analog converter). Detailed Implementation

[0040] The following is in conjunction with the attached diagram ( Figures 1-2 The present invention will be described below.

[0041] Figure 1 This is a schematic diagram of the function waveform generation system based on expression compilation and adaptive segmented sampling, which implements the present invention. Figure 2 This is a schematic diagram illustrating the function waveform generation method based on expression compilation and adaptive segmented sampling of the present invention. (Reference) Figures 1 to 2 As shown, the function waveform generation method based on expression compilation and adaptive segmented sampling includes a combination of host computer + ARM + FPGA + DAC. The host computer inputs the function string in segments according to the domain. The ARM side compiles the expression into a syntax tree, performs constant folding and domain consistency checks, and generates non-uniform samples by adaptive sampling according to curvature under the error upper limit ε constraint. Then, uniform resampling is used to construct a fixed-length waveform lookup table and complete linear calibration and fixed-point quantization. The FPGA side reads the waveform lookup table with a DDS phase accumulator and outputs a digital waveform. The DAC converts the digital waveform into a function analog waveform signal.

[0042] The steps include: Step 1, using the host computer to send a set of piecewise function expressions {f} to the ARM processor module. k (x),[a k ,b k ]} and the following parameters: ε, Δx min Δxmax N, B, W, A, f clk f out φ0, α, β, ε are the upper limit of error, and Δx is the sampling step size. min It is the minimum sampling step size, Δx max Where is the maximum sampling step size, N is the number of global uniform resampling points, B is the bit width of the digital-to-analog converter, W is the bit width of the phase accumulator, A is the bit width of the lookup table address, and f is the maximum sampling step size. clk Here, φ0 is the clock frequency, α is the initial phase, β is the first linear calibration parameter, and f is the second linear calibration parameter. k (x) is the string representing the k-th segment of the piecewise function, where k is the index, and a k It is the starting point of the kth segment, b k This is the end point of the k-th segment; Step 2, the ARM processor module determines whether the syntax / domain of the piecewise function expression is valid. If not, return to step 1; if yes, proceed to step 3.

[0043] Step 3: The ARM processor module sequentially completes expression compilation, adaptive sampling, uniform resampling, and calibration to generate a waveform lookup table, and writes the waveform lookup table into the FPGA module through the communication unit. Step 4: The DDS unit in the FPGA module calculates the frequency control word FCW and the phase offset word POW according to the working clock and the target frequency, reads the waveform lookup table through the phase accumulator, forms a segmented sampled function digital waveform, and transmits the function digital waveform to the DAC module through the data bus. Step 5: The DAC module converts the function digital waveform into a function analog waveform signal and outputs it to the display screen for display.

[0044] Step 3 includes the following expression:

[0045]

[0046] Where Δx0 is a quantity related to the value of Δx, if Δx0 < Δx min Then take Δx = Δx min If Δx0 > Δx max Then take Δx = Δx max Otherwise, take Δx = Δx0; thus, non-uniform sample points {(x) are obtained through adaptive sampling of Δx. i ,y i )};f″(x) is the second-order difference approximation of the curvature of f(x), f(x) is a piecewise function, δ is a perturbation, δ>0, and h is a fixed fraction of the piece length.

[0047] Step 3 includes the following expression:

[0048]

[0049] where y′(u j ) is y(u j The first derivative of y(u) j ) is in the global interval [x min ,x max [Formed into N equally spaced positions u] j And for non-uniform sample points {(x i ,y i The uniformly resampled sequence obtained by interpolation is: code is the compiler operator, sat is the saturation operator, and round is the rounding operator.

[0050] Step 3 includes the following expression:

[0051]

[0052] Where y l It is an equally spaced position u j The left adjacent sample point (x) l ,y l The y-axis coordinate value in ) and x l It is an equally spaced position u j The left adjacent sample point (x) l ,y l The x-axis coordinate value in ) r It is an equally spaced position u j The right adjacent sample point (x) r ,y r The x-axis coordinates and y-axis coordinates in the data are shown in the original text. r It is an equally spaced position u j The right adjacent sample point (x) r ,y r The y-axis coordinate value in ) and x min It is the global interval [x min ,x max The starting point in [], j is the ordinal number, x max It is the global interval [x min ,x max The endpoint in ].

[0053] Step 4 includes the following expression:

[0054]

[0055] The round operator is used for rounding from 4 to 5.

[0056] Step 4 includes the following expression:

[0057] Φ(n+1)=(Φ(n)+FCW)mod 2 W ,

[0058] Φ(n+1) is the phase accumulation value at the (n+1)th sampling time of the phase accumulator, Φ(n) is the phase accumulation value at the nth sampling time of the phase accumulator, n is the sampling time number, and mod is the modulo operator.

[0059] A function waveform generation system based on expression compilation and adaptive segmented sampling is used to execute the aforementioned function waveform generation method based on expression compilation and adaptive segmented sampling. It includes: a host computer 1, used to input function strings in segments according to their domain and send parameters; an ARM processor module 4, used to compile the function strings, perform constant folding and domain consistency checks, and perform adaptive sampling and uniform resampling under an error upper limit constraint ε to construct a fixed-length waveform lookup table, and complete linear calibration and fixed-point quantization; an FPGA module 10, used to read the waveform lookup table using a DDS phase accumulator and output digital waveforms, and can achieve independent frequency and phase adjustment based on the frequency control word FCW and the phase bias word POW; and a DAC module 14, used to convert the digital waveforms into analog signals. The host computer 1 includes a frequency / phase input unit 2 and a function input unit 3; the ARM processor module 4 includes an expression compilation unit 5, an adaptive sampling unit 6, a uniform resampling unit 7, a calibration and quantization unit 8, and a communication unit 9; the FPGA module 10 includes a DDS unit 11, a BRAM unit 12, and a clock divider unit 13.

[0060] This invention discloses a method and system for generating function waveforms based on expression compilation and adaptive segmented sampling, employing an ARM+FPGA architecture on a ZYNQ platform. The host computer inputs the function string in segments according to its domain. On the ARM side, the expression is compiled into a syntax tree, constant folding and domain consistency checks are performed, and non-uniform samples are generated by adaptive sampling according to curvature under an error upper limit constraint ε. Then, uniform resampling is used to construct a fixed-length waveform lookup table and complete linear calibration and fixed-point quantization. On the FPGA side, a DDS phase accumulator reads the lookup table and outputs a digital waveform, which is then converted into an analog signal by a DAC. This scheme significantly reduces the required sampling points and improves waveform fidelity under the same error conditions, and supports independent adjustment of frequency and phase, making it suitable for scientific research experiments, industrial testing, and medical diagnosis.

[0061] A method for generating function waveforms based on expression compilation and adaptive piecewise sampling, wherein the host computer provides a set of piecewise function expressions {f} to the ARM processor module (Advanced RISC Machine). k (x),[a k ,b k ]} and parameters ε, Δx min ,Δx max ,N,B,W,A,f clk ,f out,φ0,α,β; ARM compiles the expression into a evaluateable structure and performs coverage and continuity checks; within each segment, based on curvature estimation using second-order difference, the sampling step size Δx is determined under the upper limit of error ε, and adaptive sampling is performed to obtain non-uniform sample points {(x i ,y i )}; in the global interval [x min ,x max [Formed into N equally spaced positions u] j And for {(x i ,y i Interpolation yields a uniformly sampled sequence y(u) j );according to

[0062]

[0063] The uniform sampling is linearly calibrated and quantized to form a waveform lookup table; the lookup table is downloaded to the FPGA module (Field Programmable Gate Array, FPGA), and the Direct Digital Synthesis (DDS) module in the FPGA sets the frequency control word FCW and the phase control word POW with the phase accumulator bit width W according to the following formula:

[0064]

[0065] The frequency control word (FCW) and phase control word (POW) are set. A digital waveform is output based on a lookup table. The phase accumulation value is added to the phase offset word (POW), and the high A bits of the sum are used as the address index of the waveform lookup table, where A is the address width of the lookup table. The digital waveform sampled values ​​are transmitted via the data bus to the digital-to-analog converter (DAC) module, which converts them into corresponding analog signals and outputs them. Here, ε is the upper limit of the amplitude approximation error; Δx min ,Δx max These represent the lower and upper limits of the sampling step size within the segment, respectively; N is the number of global uniform resampling points; B is the bit width of the digital-to-analog converter; W is the bit width of the phase accumulator; A is the bit width of the lookup table address; f clk f is the system operating clock frequency; out φ0 is the target output frequency; α and β are the initial phase; round is for rounding; and sat is for rounding to [0, 2]. B Saturation operation of the interval [-1].

[0066] The sampling step size is determined by the following formula:

[0067]

[0068] If Δx0 < Δx min Then take Δx = Δx min If Δx0 > Δx max Then take Δx = Δx max Otherwise, take Δx = Δx0; the second derivative f″(x) is approximated using the second-order difference:

[0069]

[0070] and for those containing u j Adjacent sample points (x) l ,y l ),(x r ,y r Perform linear interpolation:

[0071]

[0072] Phase accumulation follows the formula:

[0073] Φ(n+1)=(Φ(n)+FCW)mod 2 W .

[0074] Where Φ(n) is the phase accumulation value at the nth sampling time, FCW is the frequency control word, W is the bit width of the phase accumulator, and mod represents the modulo operation.

[0075] The compilation of the expression includes:

[0076] Lexical scanning, that is, the input string f containing the number of piecewise functions. k (x) is segmented into notations, which include at least: decimal real constants with optional signs, decimal points and exponents, identifiers, left parentheses "(" and right parentheses ")", binary operators "+", "-", "×", "÷" and "^", parameter separators ","; whitespace is ignored during scanning;

[0077] Syntax analysis, that is, constructing a evaluateable abstract syntax tree (AST) based on the arithmetic expression grammar. The node types of the AST include at least constant nodes, variable nodes, and function nodes with a number of elements from 0 to 7.

[0078] Identifier binding, that is, the resolution and binding of identifiers based on functions and constant registry, wherein the registry shall have at least the following mathematical entities built in: sine, cosine, exponent, natural logarithm, power, square root, absolute value, floor down, floor up, and at least one of combination and permutation;

[0079] Constant folding and algebraic simplification involve evaluating a subtree composed of pure functions and replacing it with equivalent constant nodes to obtain an optimized evaluateable structure.

[0080] Piecewise domain interval validation, that is, validating the set of piecewise expressions {f} k (x),[a k ,b k The following checks are performed sequentially: coverage check (the union of all intervals covers the target domain), non-overlap check (the intersection of any two intervals does not exceed the common endpoint), and adjacent continuity check (the left and right limits at the common endpoint are consistent); when the endpoint amplitude is missing, endpoint samples are generated by linear interpolation as boundary interpolation.

[0081] A validity error report outputs an error code structure containing the error type and the character position index in the input string when a lexical or syntactic error occurs, which is used to locate the error location.

[0082] A function waveform generation system for implementing the method of claim 1, comprising:

[0083] The host computer is used to input function strings in segments according to their domains and send parameters down.

[0084] The ARM processor is used to compile function strings, perform constant folding and domain consistency checks, and perform adaptive sampling and uniform resampling under the upper limit of error ε to build a fixed-length waveform lookup table, and complete linear calibration and fixed-point quantization.

[0085] The FPGA is used to read the waveform lookup table using the DDS phase accumulator and output the digital waveform. It can also achieve independent adjustment of frequency and phase based on the frequency control word FCW and the phase bias word POW.

[0086] A DAC is used to convert digital waveforms into analog signals.

[0087] The FPGA is configured with clock synthesis circuitry for generating sampling or operating clocks, including a phase-locked loop or mixed-mode clock manager. The ARM and FPGA communicate via an Advanced eXtensible Interface (AXI) bus, while the host computer communicates with the ARM via serial communication.

[0088] The FPGA's on-chip block RAM (BRAM) is used to store lookup tables, and data is accessed and aligned to the bus width. A method or system for generating function waveforms based on expression compilation and adaptive segmented sampling, in any embodiment:

[0089] The communication interface between the host computer and the ARM processor is one of UART, USB, or Ethernet, and the transmitted data frame carries at least the set of piecewise function expressions {f}. k (x),[a k ,bk ]} and parameters ε, Δx min ,Δx max ,N,B,W,A,f clk ,f out ,φ0,α,β;

[0090] The waveform lookup table is stored in the FPGA's on-chip block RAM (BRAM), with an address width of A and a data width of not less than B, and communicates with the ARM processor via the AXI bus.

[0091] Adaptive segmented sampling and uniform resampling are performed by the ARM processor, linear calibration and saturation quantization are performed by the ARM processor, and phase accumulation is performed within the DDS module.

[0092] Expression compilation and execution includes lexical scanning, syntax analysis, identifier binding, constant folding, and error reporting mechanisms. The built-in mathematical functions and constants have ranges. Segment consistency checks are performed according to coverage, non-overlap, and adjacent continuity rules, and boundary interpolation is performed by linear interpolation when endpoint samples are missing.

[0093] The lookup table addressing process includes retrieving the highest A bit of Φ(n) + POW as the address index; the determination of calibration parameters α and β, and the calculation of the frequency control word FCW and the phase control word POW, are all performed according to the relationship in claim 1 by f. clk ,f out φ0 is obtained, and the digital waveform is converted into an analog signal output by the DAC.

[0094] A method and system for generating function waveforms based on expression compilation and adaptive piecewise sampling: A host computer inputs a set of piecewise functions and parameters; an ARM processor executes expression compilation and performs piecewise coverage and continuity verification; within each segment, sampling is performed based on the second-order difference curvature approximation, with an error upper limit ε constrained, and the step size is adaptively determined. Then, uniform resampling is performed at globally equidistant positions, and linear calibration and quantization are performed according to y′=αy+β to generate a waveform lookup table, where y′ is the derivative of y, y is the uniform resampling, α is the first linear calibration parameter, and β is the second linear calibration parameter; the DDS within the FPGA calculates the frequency control word FCW and phase control word POW based on the operating clock and target frequency, outputs the digital waveform through a phase accumulator lookup table, and finally converts it into an analog signal by a DAC. This scheme significantly reduces the number of samples and table size, lowers bandwidth, achieves independent adjustable frequency and phase, and directly improves the expressive power and degree of freedom of waveform generation through piecewise expressions while ensuring controlled maximum amplitude error.

[0095] A function waveform generation system based on expression compilation and adaptive piecewise sampling. For example... Figure 1As shown, the host computer (1) sends segmented function strings and control parameters to the ARM processor module (4), wherein the control parameters are obtained by the host computer frequency / phase input 2 and function input 3; the ARM completes expression compilation (5), adaptive sampling (6), uniform resampling (7) and calibration (8) in sequence, and writes the waveform lookup table into the BRAM (12) in the FPGA module (10) through the communication unit (9); the FPGA reads the lookup table under the working clock provided by the clock division unit (13) using the DDS (FCW / POW) (11) function, outputs the digital signal to the DAC module (14), and converts it into the corresponding analog signal.

[0096] The host computer (1) requires the user to input: (a) a function string segmented by the domain; (b) the target output frequency f. out (c) Static phase φ0 and amplitude / DC bias. Other parameters are automatically determined or preset by the system: table length N is determined by the BRAM byte capacity and write address step size; code value bit width B matches the DAC vertical resolution; upper error limit ε, minimum step size, and maximum step size Δx. min Δx max By default, the phase accumulator bit width W and the lookup table address bit width A are fixed in the FPGA.

[0097] The ARM processor module (4) parses the function string into an evaluable expression structure via expression compilation and normalizes it to a segment table S = {f k (x),[a k ,b k The expression compilation first performs a lexical scan on the input segmented function string, dividing it into tokens. Tokens include numerical constants, identifiers, parentheses "()", binary operators "+", "-", "×", "÷", "^", and parameter separators ",". Whitespace is ignored during the scan, and unary negative signs are supported. Subsequently, based on the arithmetic expression grammar, a recursive descent method is used for syntax analysis to construct a evaluateable abstract syntax tree (AST). The nodes of the AST include at least constant nodes, variable nodes, and function nodes with atom numbers from 0 to 7. Then, identifier resolution and binding are completed based on the function / constant registry. The registry can contain commonly used mathematical functions and constants and supports expansion. Constant folding is performed on the subtree composed of pure functions, replacing them with equivalent constant nodes to obtain an optimized evaluateable structure. If a lexical or syntax error occurs, an integer index based on the character position of the input string is returned for location. During the compilation phase, the interval sorting and coverage check of each piecewise function in the segment table are completed, the non-overlapping check of adjacent segments and the boundary continuity check are performed, and if necessary, endpoint samples are generated at the intersection by linear interpolation as boundary interpolation.

[0098] ARM processors in each [a k ,bk Within this range, the curvature is approximated using a second-order difference:

[0099]

[0100] Where h is a fixed fraction of the segment length and a perturbation δ>0 is set to avoid division by zero. Sampling is performed incrementally from the start to the end of the segment with a step size Δx, resulting in non-uniform sample points {(x...}... i ,y i All segmented samples are merged into a global sequence, and deduplication and boundary correction are performed in ascending order of x. The incremental step size Δx is estimated based on the upper limit of error as follows:

[0101]

[0102] If Δx0 < Δx min Then take Δx = Δx min If Δx0 > Δx max Then take Δx = Δx max Otherwise, take Δx = Δx0.

[0103] ARM processors in the global range [x min ,x max N equally spaced positions u are generated on the [top]. j To perform uniform resampling. For each u j Locate the left and right neighboring points (x l ,y l ),(x r ,y r Perform intra-segment linear interpolation:

[0104]

[0105] A sequence of equally spaced sample points of length N is obtained, which serves as the basis for the amplitude lookup table.

[0106] The ARM processor performs the following linear calibration and fixed-point quantization operations on equally spaced samples:

[0107]

[0108] Where α and β are calibration parameters, round is for rounding, and sat is for rounding [0, 2]. B Saturation operation in the range of [-1]. When the DAC is 14-bit, the quantization code value is saturated to [0, 16383]. To facilitate bus alignment, the code value is stored in 16-bit form in the table to maintain matching with the BRAM port.

[0109] ARM based on system clock f clk With the target frequency f out Calculate the frequency control word:

[0110]

[0111] And calculate the phase offset word based on the set static phase φ0:

[0112]

[0113] The aforementioned FCW / POW is written by the ARM to the DDS register (11) of the FPGA (10) through the communication unit (9) and operates in the clock domain provided by the clock divider unit (13).

[0114] The ARM writes the waveform lookup table into the FPGA's BRAM (12) via the communication unit (9) and the AXI bus protocol; in this embodiment, 16 bits are used as a sample point to write to the BRAM, and the write address step size is 2 bytes; therefore, the table length N = BRAM_WIDTH / 2,

[0115] Where BRAM_WIDTH represents the number of BRAM bytes used to store the lookup table. The byte address of the i-th item is 2i. To ensure beginning and end coverage, the normalization position for uniform resampling is preferably ti. i = i / (N-1).

[0116] Inside the FPGA, the DDS module performs phase accumulation according to the following formula:

[0117] Φ(n+1)=(Φ(n)+FCW)mod 2 W

[0118] Where Φ(n) is the phase accumulation value at the nth sampling time, FCW is the frequency control word, W is the bit width of the phase accumulator, and mod represents modulo operation. After adding the phase accumulation value to the phase offset word (POW), the high A bits of the sum are used as the address index of the waveform lookup table, and the corresponding digital waveform sample value is read from the BRAM, where A is the address width of the lookup table. The digital waveform sample value is transmitted to the DAC module via the data bus, whereby the DAC module converts it into the corresponding analog signal and outputs it.

[0119] This embodiment improves the efficiency of table lookup without changing the DDS structure: it can significantly reduce table length and bandwidth under the same error ε, or improve waveform fidelity under the same table length; at the same time, it greatly improves the degree of freedom of waveform generation by inputting piecewise functions.

[0120] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A function waveform generating method based on expression compilation and adaptive segmented sampling, characterized in that, The method comprises the following steps:

2. The function waveform generation method based on expression compilation and adaptive segmented sampling according to claim 1, characterized in that, Step 2, the ARM processor module judges whether the segmented function expression syntax / domain is legal? If not, return to step 1, if yes, go to step 3; Step 1, the host computer sends a segmented function expression set {f k (x),[a k ,b k ]} and the following parameters to the ARM processor module: ε, Δx min , Δx max , N, B, W, A, f clk , f out , φ0, α, β, ε is the upper limit of error, Δx is the sampling step, Δx min is the minimum sampling step, Δx max is the maximum sampling step, N is the number of global uniform resampling points, B is the bit width of the digital-to-analog converter, W is the bit width of the phase accumulator, A is the table address bit width, f clk is the clock frequency, φ0 is the initial phase, α is the first linear calibration parameter, β is the second linear calibration parameter, f k (x) is the kth segmented function string, k is the serial number, a k is the starting point of the kth segment, b k is the end point of the kth segment; Step 3, the ARM processor module generates a waveform lookup table after completing expression compilation, adaptive sampling, uniform resampling and calibration quantization in turn, and writes the waveform lookup table into the FPGA module through the communication unit; Step 4, the DDS unit in the FPGA module calculates the frequency control word FCW and the phase offset word POW according to the working clock and the target frequency, reads the waveform lookup table through the phase accumulator, forms the segmented sampled function digital waveform, and transmits the function digital waveform to the DAC module through the data bus; Step 5, the DAC module converts the function digital waveform into a function analog waveform signal and outputs it to the display screen of the host computer for display. The expression in step 3 includes:

3. The method of claim 2, wherein the expression-based compilation and adaptive piecewise sampling of a function waveform generation method is characterized by, f''(x) is the second-order difference approximation evaluation curvature of f(x), f(x) is a segmented function, δ is a perturbation, δ>0, h is a fixed fraction of the segment length. where Δx0 is a value-dependent quantity of Δx, if Δx0 < Δx min , then take Δx = Δx min ; if Δx0 > Δx max , then take Δx = Δx max ; otherwise, take Δx = Δx0; thus, the non-uniform sampling points {(x i , y i )} are obtained by the adaptive sampling of Δx. The expression in step 3 includes:

4. The method of claim 2, wherein the expression-based compilation and adaptive piecewise sampling of a function waveform generation method is characterized by, The expression in step 3 includes: where y′(u j ) is y(u j The first derivative of y(u) j ) is in the global interval [x min ,x max [Formed into N equally spaced positions u] j And for non-uniform sample points {(x i ,y i The uniformly resampled sequence obtained by interpolation is: code is the compiler operator, sat is the saturation operator, and round is the rounding operator.

5. The function waveform generation method based on expression compilation and adaptive segmented sampling according to claim 4, characterized in that, The expression in step 4 includes: where y l is a y-axis coordinate value in a left neighboring sample (x j , y l ) of the equidistant position u l , x l is an x-axis coordinate value in the left neighboring sample (x j , y l ) of the equidistant position u l , x r is an x-axis coordinate value in a right neighboring sample (x j , y r ) of the equidistant position u r , y r is a y-axis coordinate value in the right neighboring sample (x j , y r ) of the equidistant position u r , x min is a start point in a global interval [x min , x max ], j is a serial number, and x max is an end point in the global interval [x min , x max ].

6. The method of claim 2, wherein the function waveform generation method based on expression compilation and adaptive segmented sampling is characterized by, Where round is a 4-round 5-integer operator. The expression in step 4 includes:

7. The method of claim 2, wherein the expression-based compilation and adaptive piecewise sampling of a function waveform generation method is characterized by, Φ(n+1) is the phase accumulation value of the phase accumulator at the n+1 sampling time, Φ(n) is the phase accumulation value of the phase accumulator at the n sampling time, n is the sampling time sequence number, and mod is the modulus operator. Φ(n + 1) = (Φ(n) + FCW) mod 2 W , The method for generating a function waveform based on expression compilation and adaptive segmented sampling includes:

8. A function waveform generation system based on expression compilation and adaptive segmented sampling, characterized by, The host computer is used to segment the input function string according to the definition domain and issue parameters; The ARM processor module is used to compile the function string, constant folding and definition domain consistency check, and adaptive sampling and uniform resampling under the error upper limit ε constraint to construct a fixed length waveform lookup table, and complete linear calibration and fixed point quantization; The FPGA module is used to read the waveform lookup table output digital waveform using DDS phase accumulator, and can realize independent adjustable frequency and phase based on frequency control word FCW and phase offset word POW; The DAC module is used to convert the digital waveform into an analog signal. The host computer includes a frequency / phase input unit and a function input unit; the ARM processor module includes an expression compilation unit, an adaptive sampling unit, a uniform resampling unit, a calibration quantization unit, and a communication unit; the FPGA module includes a DDS unit, a BRAM unit, and a clock division unit.

9. The expression-based compilation and adaptive piecewise-sampling function waveform generation system of claim 8, wherein, ​

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