Integrated circuit design Verilog code generation method and device based on large language model, equipment and medium

Abstract

The invention discloses an integrated circuit design Verilog code generation method and device based on a large language model, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps that semantic analysis is conducted on an input language of an integrated circuit user side through the large language model, and a target constraint set is determined based on an obtained performance index set and through a regular expression; a candidate architecture scheme is generated by utilizing thinking chain technology reasoning, the candidate architecture scheme is predicted by utilizing an XGBoost regression model, and a target architecture scheme is determined based on an index prediction result and the candidate architecture scheme by utilizing a non-dominated sorting genetic algorithm; and determining an initial Verilog code based on the target architecture scheme and a preset code template library, and performing code style conversion on the initial Verilog code based on a code style feature corresponding to the integrated circuit user side to obtain a target Verilog code. And the efficiency and availability of integrated circuit design are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and in particular to a large language model-based integrated circuit design Verilog code generation method, device and medium. BACKGROUND

[0002] In the modern integrated circuit design process, the traditional design method follows the forward design mode of functional requirements, code implementation, performance verification and iterative optimization. The designer first writes the hardware description language code according to the functional specification, and then verifies the performance indicators through logic synthesis, layout and wiring and other back-end processes. When the actual performance cannot meet the requirements, it is necessary to return to modify the code architecture, forming a multi-round iterative cycle. The traditional method has the following technical defects: long design iteration cycle and low efficiency. Due to the lack of a direct mapping mechanism from performance targets to architecture parameters, the designer needs to adjust the code repeatedly based on experience, and each modification needs to re-execute the complete verification process; the architecture selection lacks intelligent guidance. When determining key architecture parameters such as pipeline depth, parallelism and data bit width, existing technologies mainly rely on the personal experience of designers, lacking intelligent decision support based on specific performance constraints; it is difficult to balance multiple target constraints. Actual chip design needs to meet multiple performance indicators such as working frequency, power budget and chip area, which are mutually restrictive, and existing tools lack intelligent trade-off mechanisms for multiple target constraints; lack of natural language understanding and reasoning ability. Existing EDA (Electronic Design Automation) tools cannot understand the user's natural language description and cannot perform complex design reasoning and decision-making.

[0003] From the above, how to improve the efficiency and usability of integrated circuit design is a problem to be solved at present. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a large language model-based integrated circuit design Verilog code generation method, device and medium, which can improve the efficiency and usability of integrated circuit design. The specific scheme is as follows:

[0005] In the first aspect, the present application provides a large language model-based integrated circuit design Verilog code generation method, comprising:

[0006] The large language model is used to perform semantic analysis on the input language of the integrated circuit user terminal, and a performance indicator set is determined based on the analysis result. Based on the performance indicator set and the preset constraint template library and using regular expressions, template matching and conversion are performed to obtain numerical constraints, and a target constraint set is determined based on the numerical constraints and a preset statistical method;

[0007] determine a hardware design intention by using a text convolutional neural network and the analysis result, format convert the target constraint set and the hardware design intention to obtain a target description file, determine a constraint correlation matrix by using a correlation analysis algorithm based on the target constraint set in the target description file, determine a target constraint weight by using the constraint correlation matrix and an analytic hierarchy process, fuse the target constraint weight into the target constraint set, perform a feasibility judgment on the obtained fused constraint set, and determine an effective constraint set based on a judgment result;

[0008] generate a candidate architecture scheme including architecture parameters based on the effective constraint set and by using a thinking chain technology reasoning, predict each performance index of the candidate architecture scheme by using an XGBoost regression model to obtain an index prediction result, perform multi-objective optimization by using a non-dominated sorting genetic algorithm based on the index prediction result and the candidate architecture scheme to obtain a Pareto optimal solution set, and determine a target architecture scheme by using the target constraint weight and the Pareto optimal solution set and by using a TOPSIS method;

[0009] determine an initial Verilog code based on an architecture type of the target architecture scheme and a preset code template library, perform a syntax check on the initial Verilog code, and perform syntax repair and code style conversion on the initial Verilog code by using a sequence-to-sequence model based on a check result and a code style feature corresponding to the integrated circuit user end to obtain a target Verilog code.

[0010] Optionally, the input language of the integrated circuit user end is semantically analyzed by using a large language model, and a performance index set is determined based on an analysis result, template matching and conversion are performed on the performance index set and a preset constraint template library by using a regular expression to obtain a numerical constraint, and a target constraint set is determined based on the numerical constraint and a preset statistical method, including:

[0011] A target large language model is obtained by fine-tuning a large language model by using a corpus in the field of hardware design, an input language of an integrated circuit user end is obtained, and the input language is semantically analyzed based on the target large language model to obtain an analysis text;

[0012] A target entity recognition model is determined based on a bidirectional long short-term memory network and a conditional random field, and named entity recognition is performed on the analysis text by using the target entity recognition model to determine a performance index set based on an analysis result;

[0013] Template matching is performed on index text in the performance index set by using a preset constraint template library, and a constraint structure is determined based on a matching result, and the constraint structure is converted based on a regular expression to obtain a numerical constraint;

[0014] performing dependency syntax analysis on the parsed text based on a preset natural language processing toolkit, and determining a logical relationship between target constraints by using analysis results and the numerical constraints, and constructing an initial constraint set based on the logical relationship;

[0015] determining indicator weights in the initial constraint set by using a TF-IDF algorithm, and determining a priority of a target constraint based on the indicator weights, and determining a target constraint set by using the priority and the initial constraint set.

[0016] Optionally, the hardware design intention is determined by using a text convolutional neural network and the parsed results, format conversion is performed on the target constraint set and the hardware design intention to obtain a target description file, a constraint correlation matrix is determined based on the target constraint set in the target description file and by using a correlation analysis algorithm, and a target constraint weight is determined by using the constraint correlation matrix and an analytic hierarchy process, including:

[0017] the parsed text is recognized by using a text convolutional neural network model to obtain a design intention, the target constraint set and the design intention are integrated to obtain an integrated file, and the integrated file is converted into a target description file in a JSON format;

[0018] a constraint correlation degree is determined based on the target constraint set in the target description file and by using a correlation analysis algorithm, and a constraint correlation matrix is constructed by using the constraint correlation degree;

[0019] a judgment matrix is determined by using the constraint correlation matrix, and a target constraint weight is determined based on the judgment matrix and by using an analytic hierarchy process.

[0020] Optionally, the target constraint weight is fused into the target constraint set, a feasibility of a fused constraint set obtained after fusion is judged, and an effective constraint set is determined based on a judgment result, including:

[0021] the target constraint weight is fused into the target constraint set to obtain a fused constraint set;

[0022] a constraint feasible region in the fused constraint set is determined, and it is judged whether an intersection of the constraint feasible region is an empty set;

[0023] if the intersection of the constraint feasible region is not an empty set, it is determined that there is no constraint conflict, and the fused constraint set is determined as the effective constraint set.

[0024] Optionally, the candidate architecture scheme including the architecture parameters is generated based on the effective constraint set and by using the thinking chain technology reasoning, each performance index of the candidate architecture scheme is predicted by using an XGBoost regression model to obtain an index prediction result, a multi-objective optimization is performed on the index prediction result and the candidate architecture scheme by using a non-dominated sorting genetic algorithm to obtain a Pareto optimal solution set, a target architecture scheme is determined by using the target constraint weight and the Pareto optimal solution set and by using a TOPSIS method, including:

[0025] The candidate architecture scheme including the architecture parameters is generated based on the effective constraint set and a preset architecture reasoning prompt template and by using the thinking chain technology reasoning;

[0026] A performance data set including historical hardware design schemes is constructed, and the XGBoost regression model is trained by using the performance data set to obtain a target regression model;

[0027] The performance of the candidate architecture scheme is predicted based on the target regression model to obtain an index prediction result corresponding to the candidate architecture scheme, and an index confidence interval is determined by using a Bayesian neural network, and a performance prediction result is determined based on the index prediction result and the index confidence interval;

[0028] The target optimization function including each optimization target is defined based on the performance prediction result, and a multi-objective optimization is performed on the candidate architecture scheme based on the target optimization function and by using a non-dominated sorting genetic algorithm and a penalty function method to obtain a Pareto optimal solution set;

[0029] The Pareto optimal solution set is sorted based on the target constraint weight and by using a TOPSIS method to obtain an architecture scheme sorting result including a comprehensive score, and the candidate architecture scheme with the highest comprehensive score is determined as the target architecture scheme based on the architecture scheme sorting result.

[0030] Optionally, the initial Verilog code is determined based on the architecture type of the target architecture scheme and a preset code template library, the initial Verilog code is syntax checked, the initial Verilog code is syntax repaired and code style converted by using a sequence-to-sequence model based on the checking result and the code style characteristics corresponding to the integrated circuit user end to obtain a target Verilog code, including:

[0031] The corresponding combination template is determined based on the architecture type of the target architecture scheme and a preset code template library; the code template library includes a basic template, an architecture template and an optimization template;

[0032] Fill the target architecture parameters corresponding to the target architecture scheme into the combination template by using a preset template engine and a preset parameter mapping rule set, to obtain initial Verilog code;

[0033] Perform syntax checking on the initial Verilog code by using a preset syntax checker and an abstract syntax tree, to obtain an error report, perform syntax repair on the initial Verilog code based on the error report, to obtain repaired Verilog code;

[0034] Perform analysis on the historical code of the integrated circuit user end by using a clustering algorithm, to obtain code style features, perform code style conversion on the repaired Verilog code based on the code style features and by using a sequence-to-sequence model, to obtain target Verilog code.

[0035] Optionally, after the target Verilog code is obtained by performing syntax repair and code style conversion on the initial Verilog code based on the checking result and the code style features corresponding to the integrated circuit user end and by using a sequence-to-sequence model, the method further includes:

[0036] Collect a synthesis report of the target Verilog code by using an EDA tool, and extract the synthesis report, to obtain actual performance data;

[0037] Construct a performance prediction error library based on the actual performance data and the index prediction result, and update the XGBoost regression model based on the performance prediction error library and by using a stochastic gradient descent algorithm.

[0038] In a second aspect, the present application provides a device for generating Verilog code for integrated circuit design based on a large language model, comprising:

[0039] A constraint set determination module is configured to perform semantic analysis on input language of an integrated circuit user end by using a large language model, determine a performance index set based on an analysis result, perform template matching and conversion based on the performance index set and a preset constraint template library and by using a regular expression, to obtain numerical constraints, and determine a target constraint set based on the numerical constraints and a preset statistical method.

[0040] The weight fusion module is configured to determine a hardware design intention by using the text convolutional neural network and the parsing result, perform format conversion on the target constraint set and the hardware design intention to obtain a target description file, determine a constraint correlation matrix based on the target constraint set in the target description file and by using a correlation analysis algorithm, determine target constraint weights by using the constraint correlation matrix and an analytic hierarchy process, fuse the target constraint weights into the target constraint set, perform feasibility judgment on the obtained fused constraint set, and determine an effective constraint set based on a judgment result.

[0041] The target scheme determination module is configured to generate a candidate architecture scheme including architecture parameters based on the effective constraint set and by using a thinking chain technology reasoning, predict each performance index of the candidate architecture scheme by using an XGBoost regression model to obtain an index prediction result, perform multi-objective optimization by using a non-dominated sorting genetic algorithm based on the index prediction result and the candidate architecture scheme to obtain a Pareto optimal solution set, and determine a target architecture scheme by using the target constraint weights and the Pareto optimal solution set and by using a TOPSIS method.

[0042] The target code determination module is configured to determine an initial Verilog code based on an architecture type of the target architecture scheme and a preset code template library, perform syntax checking on the initial Verilog code, and perform syntax repair and code style conversion on the initial Verilog code by using a sequence-to-sequence model based on a checking result and a code style feature corresponding to the integrated circuit user end to obtain a target Verilog code.

[0043] In a third aspect, the present application provides an electronic device, comprising:

[0044] A memory configured to save a computer program.

[0045] A processor configured to execute the computer program to implement the foregoing integrated circuit design Verilog code generation method based on a large language model.

[0046] In a fourth aspect, the present application provides a computer readable storage medium configured to save a computer program, wherein the computer program is executed by a processor to implement the foregoing integrated circuit design Verilog code generation method based on a large language model.

[0047] The application utilizes a large language model to perform semantic analysis on the input language of an integrated circuit user terminal, determines a performance index set based on the analysis result, performs template matching and conversion based on the performance index set and a preset constraint template library and using a regular expression to obtain a numerical constraint, determines a target constraint set based on the numerical constraint and a preset statistical method; determines a hardware design intent using a text convolutional neural network and the analysis result, performs format conversion on the target constraint set and the hardware design intent to obtain a target description file, determines a constraint correlation matrix using a correlation analysis algorithm based on the target constraint set in the target description file, determines a target constraint weight using the constraint correlation matrix and an analytic hierarchy process, fuses the target constraint weight into the target constraint set, performs feasibility judgment on the obtained fused constraint set, and determines an effective constraint set based on the judgment result; generates a candidate architecture scheme including architecture parameters based on the effective constraint set and using a mind chain technology reasoning, predicts each performance index of the candidate architecture scheme using an XGBoost regression model to obtain an index prediction result, performs multi-objective optimization using a non-dominated sorting genetic algorithm based on the index prediction result and the candidate architecture scheme to obtain a Pareto optimal solution set, determines a target architecture scheme using a TOPSIS method using the target constraint weight and the Pareto optimal solution set; determines an initial Verilog code based on the architecture type of the target architecture scheme and a preset code template library, performs syntax checking on the initial Verilog code, performs syntax repair and code style conversion on the initial Verilog code using a sequence-to-sequence model based on the checking result and the code style characteristics corresponding to the integrated circuit user terminal to obtain a target Verilog code.

[0048] As can be seen from the above, the application utilizes a large language model to analyze the natural language requirements of an integrated circuit user terminal, generates a target constraint set using a regular expression and a preset statistical method, identifies a design intent using a text convolutional neural network and generates a target description file, performs constraint correlation analysis and weight fusion, and then performs feasibility judgment to obtain an effective constraint set; then generates a candidate architecture scheme using a mind chain technology, predicts the performance indexes of the scheme using an XGBoost regression model, optimizes based on a non-dominated sorting genetic algorithm, and determines an optimal architecture scheme using a TOPSIS method; then generates a target Verilog code through the target architecture scheme and a preset code template library and based on the code style characteristics corresponding to the user terminal. In this way, the target Verilog code is determined based on the architecture template and the code style of the user terminal and using a large language model, which can accurately understand user requirements and improve the syntax accuracy of the code, greatly reducing the overall design cycle. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description are only a part of the present application, and all other drawings obtained by those of ordinary skill in the art without creative work based on the present application are within the scope of the present application.

[0050] Figure 1 A large language model-based integrated circuit design Verilog code generation method flowchart disclosed by the present application;

[0051] Figure 2 A large language model-based integrated circuit design Verilog code generation method flowchart disclosed by the present application;

[0052] Figure 3 A target description file generation schematic diagram provided by the present application;

[0053] Figure 4 A target architecture scheme generation schematic diagram provided by the present application;

[0054] Figure 5 A target Verilog code generation schematic diagram provided by the present application;

[0055] Figure 6 A large language model-based integrated circuit design Verilog code generation device structure schematic diagram disclosed by the present application;

[0056] Figure 7 An electronic device structure diagram disclosed by the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of the present application.

[0058] Currently, in the modern integrated circuit design flow, the design iteration period of the traditional design method is long and inefficient, and when determining the pipeline depth, parallelism, data bit width and other key architecture parameters, it relies on the personal experience of the designer and lacks intelligent decision support based on specific performance constraints. Therefore, the present application provides an integrated circuit design Verilog code generation method based on a large language model, which determines the target Verilog code based on the architecture template and the code style of the user end and uses a large language model to accurately understand user needs and improve the syntax accuracy of the code, greatly reducing the overall design cycle.

[0059] Referring to Figure 1 As shown in the drawings, the embodiment of the application discloses an integrated circuit design Verilog code generation method based on a large language model, comprising:

[0060] Step S11, using a large language model to perform semantic analysis on the input language of the integrated circuit user end, and determining a performance index set based on the analysis result, performing template matching and conversion based on the performance index set and a preset constraint template library and using a regular expression to obtain a numerical constraint, and determining a target constraint set based on the numerical constraint and a preset statistical method.

[0061] In this embodiment, the target large language model is obtained by fine-tuning a large language model using a corpus in the hardware design field, and the large language model can be a BERT-Large (BERT series model; BERT, Bidirectional Encoder Representations from Transformers, a pre-trained language representation model) model based on the Transformer (i.e. a deep learning model) architecture; in one specific embodiment, the model parameter amount of the large language model can be 340M, the hidden layer dimension can be 1024, and the number of attention heads can be 16. Then the input language of the integrated circuit user end is obtained, the input language is semantically analyzed based on the target large language model to obtain parsed text; a target entity recognition model is determined based on a bidirectional long short-term memory network and a conditional random field; in one specific embodiment, the hidden layer dimension of the target entity recognition model can be 512, and the learning rate is set to 2e-5; a hardware design vocabulary is constructed based on the professional terms in the hardware design field, and the professional terms can be pipeline depth, clock frequency and efficiency budget; the parsed text is named entity recognized based on the hardware design vocabulary and using the target entity recognition model to obtain a performance index set; the performance index set can include frequency, power consumption, area, delay and throughput.

[0062] It can be understood that after obtaining the performance index set, a preset constraint template library containing common constraint patterns is defined, such as a frequency not lower than 5MHz; template matching is performed on index text in the performance index set by using the preset constraint template library, and constraint structures are determined based on the matching results, numerical extraction and conversion are performed on the constraint structures based on regular expressions, scientific notation and engineering unit conversion are supported to obtain numerical constraints, such as 5e2MHz converted into 500MHz; dependency syntax analysis is performed on the parsed text based on a preset natural language processing toolkit, and logical relationships between target constraints are determined based on the analysis results and the numerical constraints, an initial constraint set containing logical relationships is constructed, index weights in the initial constraint set are determined by using a TF-IDF (Term Frequency-Inverse Document Frequency, a weighting technique) algorithm, and the priority of the target constraint is determined based on the index weights, and a target constraint set containing the priority is constructed.

[0063] Specifically, the input language of the integrated circuit user terminal is semantically parsed by using the large language model, and the performance index set is determined based on the parsed results, template matching and conversion are performed based on the performance index set and the preset constraint template library by using regular expressions to obtain numerical constraints, the target constraint set is determined based on the numerical constraints and the preset statistical method, including: a target large language model is obtained by fine-tuning a large language model by using a corpus in the hardware design field, an input language of an integrated circuit user terminal is obtained, and the input language is semantically parsed based on the target large language model to obtain parsed text; a target entity recognition model is determined based on a bidirectional long short-term memory network and a conditional random field, and named entity recognition is performed on the parsed text by using the target entity recognition model to determine a performance index set based on the recognition results; template matching is performed on index text in the performance index set by using a preset constraint template library, and constraint structures are determined based on the matching results, and conversion is performed on the constraint structures based on regular expressions to obtain numerical constraints; dependency syntax analysis is performed on the parsed text based on a preset natural language processing toolkit, and logical relationships between target constraints are determined based on the analysis results and the numerical constraints, and an initial constraint set is constructed based on the logical relationships; index weights in the initial constraint set are determined by using a TF-IDF algorithm, and the priority of the target constraint is determined based on the index weights, and the target constraint set is determined by using the priority and the initial constraint set.

[0064] Step S12: Determine the hardware design intent using a text convolutional neural network and the parsing results; convert the target constraint set and the hardware design intent into a format to obtain a target description file; determine the constraint correlation matrix based on the target constraint set in the target description file using a correlation analysis algorithm; determine the target constraint weights using the constraint correlation matrix and the analytic hierarchy process (AHP); fuse the target constraint weights into the target constraint set; perform a feasibility assessment on the obtained fused constraint set; and determine the effective constraint set based on the assessment results.

[0065] In this embodiment, a target number of initial design intentions are defined. These initial design intentions include performance priority, power consumption priority, area priority, balanced design, high throughput, low latency, configurability, and scalability. The TextCNN (Text Convolutional Neural Network) model is used to classify the intentions of the parsed text. Simultaneously, an 8-head attention mechanism can be used to enhance the weights of keywords such as "fast" and "power-saving" to identify the design intentions. The kernel size of the text convolutional neural network model can be [3, 4, 5]. The target constraint set and the design intentions are integrated to obtain an integrated file. A preset format conversion tool is used to convert the integrated file into a target description file in JSON (JavaScript Object Notation) format. The corresponding code is as follows:

[0066] "constraints": {

[0067] "frequency": {"value": 100, "unit": "MHz", "operator": ">=", "priority": 0.9};

[0068] "power": {"value": 50, "unit": "mW", "operator": "<=", "priority":0.8};

[0069] "area": ​​{"value": 1000, "unit": "LUT", "operator": "<=", "priority": 0.7};

[0070] }

[0071] "intent": "performance_priority"; / / Design intent: performance priority

[0072] "preferences": {

[0073] "pipeline_depth": "flexible";

[0074] "parallelism": "high";

[0075] "code_style": "readable";

[0076] }

[0077] }。

[0078] It can be understood that the constraint correlation degree is determined based on the target constraint set in the target description file and by using a correlation analysis algorithm, and a constraint correlation matrix is constructed by using the constraint correlation degree, the constraint correlation matrix is used to measure the influence relationship between different constraints, for example, the frequency and power consumption correlation coefficient is 0.85, and the frequency and area correlation coefficient is 0.72; then a 9*9 judgment matrix is constructed by using the constraint correlation matrix, and the target constraint weight is determined based on the judgment matrix and by using an analytic hierarchy process. Specifically, the hardware design intention is determined by using a text convolutional neural network and the analysis result, the target constraint set and the hardware design intention are format-converted to obtain a target description file, the constraint correlation matrix is determined based on the target constraint set in the target description file and by using a correlation analysis algorithm, and the target constraint weight is determined by using the constraint correlation matrix and an analytic hierarchy process, including: the design intention is obtained by identifying the analysis text by using a text convolutional neural network model, the target constraint set and the design intention are integrated to obtain an integrated file, and the integrated file is converted into a target description file in JSON format; the constraint correlation degree is determined based on the target constraint set in the target description file and by using a correlation analysis algorithm, and a constraint correlation matrix is constructed by using the constraint correlation degree; the judgment matrix is determined by using the constraint correlation matrix, and the target constraint weight is determined based on the judgment matrix and by using an analytic hierarchy process.

[0079] In this embodiment, after the target constraint weight is obtained, the target constraint weight is fused into the target constraint set to obtain a fused constraint set, and then the fused constraint set is subjected to feasibility judgment. For example, if the first target constraint is greater than or equal to 120 MHz and the second target constraint is less than or equal to 40 mW, and the feasible region is empty, it is determined that there is a constraint conflict, a preset conflict resolution mechanism is triggered, for example, it is suggested that the first target constraint be greater than or equal to 110 MHz or the second target constraint be less than or equal to 50 mW. If the feasible region is not empty, it is determined that there is no constraint conflict, and then the fused constraint set is determined as an effective constraint set. Specifically, the target constraint weight is fused into the target constraint set, the obtained fused constraint set is subjected to feasibility judgment, and the effective constraint set is determined based on the judgment result. The method comprises the following steps: the target constraint weight is fused into the target constraint set to obtain a fused constraint set; the constraint feasible region in the fused constraint set is determined, and it is judged whether the intersection of the constraint feasible region is an empty set; if the intersection of the constraint feasible region is not an empty set, it is determined that there is no constraint conflict, and then the fused constraint set is determined as an effective constraint set.

[0080] In step S13, a candidate architecture scheme including architecture parameters is generated based on the effective constraint set and by using a thinking chain technology reasoning, each performance index of the candidate architecture scheme is predicted by using an XGBoost regression model to obtain an index prediction result, and a Pareto optimal solution set is obtained by using a non-dominated sorting genetic algorithm for multi-objective optimization based on the index prediction result and the candidate architecture scheme. A target architecture scheme is determined by using a TOPSIS method based on the target constraint weight and the Pareto optimal solution set.

[0081] In this embodiment, after obtaining the effective constraint set, a candidate architecture scheme including architecture parameters is generated based on the effective constraint set and by using a GPT-4 (Generative Pre-trained Transformer 4, which is a language model) model, a preset architecture inference prompt template, and a CoT (Chain of Thought) technology; for example, the candidate architecture scheme can be a pipeline depth of 3 levels, a parallelism degree of 8, a data bit width of 32 bits, and a cache size of 5 KB; then a performance dataset including historical hardware design schemes is constructed, and an XGBoost (eXtreme Gradient Boosting, which is an extreme gradient boosting regression model) regression model is trained by using the performance dataset to obtain a target regression model; the model parameters corresponding to the XGBoost regression model can be n_estimators=1000, max_depth=8, and learning_rate=0.1; then the performance of the candidate architecture scheme is predicted based on the target regression model to obtain an index prediction result corresponding to the candidate architecture scheme, and a Bayesian neural network is used to determine an index confidence interval, for example, the index confidence of the frequency is 95%; a performance prediction result is determined based on the index prediction result and the index confidence interval, and a target optimization function including each optimization target is defined based on the performance prediction result; in a specific implementation, three target optimization functions can be defined, if the optimization target is to maximize the frequency, the corresponding first target optimization function is: , if the optimization target is to minimize the power consumption, the corresponding second target optimization function is: , and if the optimization target is to minimize the area, the corresponding third target optimization function is: .

[0082] It can be understood that after obtaining the target optimization function, the candidate architecture scheme is subjected to multi-objective optimization based on the target optimization function and by using a non-dominated sorting genetic algorithm and a penalty function method; in a specific implementation, the population size can be set to 100, the evolution algebra can be set to 500, the crossover probability can be set to 0.9, the mutation probability can be set to 0.1, 91 reference points are uniformly distributed in the target space, constraint violations are handled by a penalty function method, the candidate architecture scheme is subjected to multi-objective optimization to obtain a Pareto optimal solution set, the Pareto optimal solution set is sorted based on the target constraint weight and by using a TOPSIS method (which is a method for approximating an ideal solution) to obtain an architecture scheme sorting table including comprehensive scores, and the candidate architecture scheme with the highest comprehensive score is determined as the target architecture scheme based on the architecture scheme sorting table.

[0083] Specifically, the generating a candidate architecture scheme including architecture parameters based on the effective constraint set and using the thinking chain technology to reason, predicting each performance index of the candidate architecture scheme using an XGBoost regression model to obtain an index prediction result, performing multi-objective optimization based on the index prediction result and the candidate architecture scheme and using a non-dominated sorting genetic algorithm to obtain a Pareto optimal solution set, determining a target architecture scheme using the target constraint weight and the Pareto optimal solution set and using a TOPSIS method includes: generating a candidate architecture scheme including architecture parameters based on the effective constraint set and a preset architecture reasoning prompt template and using the thinking chain technology to reason; constructing a performance data set including historical hardware design schemes, training an XGBoost regression model using the performance data set to obtain a target regression model; predicting the performance of the candidate architecture scheme based on the target regression model to obtain the index prediction result corresponding to the candidate architecture scheme, and determining the index confidence interval using a Bayesian neural network, and determining the performance prediction result based on the index prediction result and the index confidence interval; defining a target optimization function including each optimization target based on the performance prediction result, performing multi-objective optimization on the candidate architecture scheme based on the target optimization function and using a non-dominated sorting genetic algorithm and a penalty function method to obtain a Pareto optimal solution set; sorting the Pareto optimal solution set based on the target constraint weight and using a TOPSIS method to obtain an architecture scheme sorting result including a comprehensive score, and determining the candidate architecture scheme with the highest comprehensive score as the target architecture scheme based on the architecture scheme sorting result.

[0084] Step S14, determining an initial Verilog code based on the architecture type of the target architecture scheme and a preset code template library, performing syntax checking on the initial Verilog code, and performing syntax repair and code style conversion on the initial Verilog code based on the checking result and the code style characteristics corresponding to the integrated circuit user end and using a sequence-to-sequence model to obtain a target Verilog code.

[0085] In this embodiment, after obtaining the target architecture scheme, a preset code template library is constructed based on a basic template, an architecture template and an optimization template and by using a CodeT5-Large model (i.e., a pre-trained code generation model); the basic template can include an adder, a multiplier and a memory; the architecture template can include a pipeline processor and a parallel computing unit; the optimization template can include clock gating and power consumption management; incremental updating and rollback of the templates are supported. Based on the architecture type of the target architecture scheme and the preset code template library, corresponding target basic template, target architecture template and target optimization template are determined, and the target basic template, the target architecture template and the target optimization template are combined to obtain a combined template. The target architecture parameters corresponding to the target architecture scheme can be filled into the combined template by using a Jinja2 template engine and a preset parameter mapping rule set, to obtain initial Verilog code. A preset syntax checker and an abstract syntax tree (AST, i.e., Abstract Syntax Tree) analysis code result are used to perform syntax checking on the initial Verilog code, to obtain an error report. Verilator (i.e., a Verilog / SystemVerilog simulator; Verilog, i.e., a hardware description language; SystemVerilog, i.e., a hardware description and verification language) can be used as the preset syntax checker. Based on the error report, syntax repair is performed on the initial Verilog code, to obtain repaired Verilog code. A clustering algorithm is used to analyze the historical code of the integrated circuit user end, to extract a 20-dimensional code style feature vector. Based on the code style feature vector, a user personal coding style is determined. Based on the user personal coding style and by using a sequence-to-sequence model (Sequence-to-Sequence Model, i.e., a neural network model), code style conversion is performed on the repaired Verilog code, to obtain target Verilog code.

[0086] Specifically, the method comprises: determining a combined template based on the architecture type of the target architecture scheme and the preset code template library; the code template library comprises a basic template, an architecture template, and an optimization template; filling target architecture parameters corresponding to the target architecture scheme into the combined template by using a preset template engine and a preset parameter mapping rule set to obtain initial Verilog code; performing syntax checking on the initial Verilog code by using a preset syntax checker and an abstract syntax tree to obtain an error report; performing syntax repair on the initial Verilog code based on the error report to obtain repaired Verilog code; analyzing historical code of the integrated circuit user end by using a clustering algorithm to obtain code style features; and performing code style conversion on the repaired Verilog code based on the code style features and by using a sequence-to-sequence model to obtain target Verilog code.

[0087] It can be understood that after the target Verilog code is obtained, a synthesis report of the target Verilog code is collected by using an EDA tool, and the synthesis report is extracted to obtain actual performance data, error data between the actual performance data and the index prediction result is determined, and the error data is stored in a performance prediction error library, and then the XGBoost regression model is updated by using a stochastic gradient descent algorithm. Specifically, after the target Verilog code is obtained by performing syntax repair and code style conversion on the initial Verilog code based on the error report and the code style features corresponding to the integrated circuit user end and by using a sequence-to-sequence model, the method further comprises: collecting a synthesis report of the target Verilog code by using an EDA tool, and extracting the synthesis report to obtain actual performance data; constructing a performance prediction error library based on the actual performance data and the index prediction result, updating the XGBoost regression model based on the performance prediction error library and by using a stochastic gradient descent algorithm, and recording a corresponding update effect.

[0088] Further, the latest hardware design research results can be obtained from an academic database, and the latest hardware design research results are extracted by using a natural language processing technology to obtain new design knowledge, the preset scoring mechanism is used to evaluate the quality based on the new design knowledge, and a hardware design knowledge base is constructed based on the obtained evaluation results, which can be used for the next semantic analysis step; or a corresponding learning report can be generated based on the update effect and the hardware design knowledge base.

[0089] As can be seen from the above, the present application uses a large language model to analyze the natural language requirements of the integrated circuit user end, and uses regular expressions and a preset statistical method to generate a target constraint set, uses a text convolutional neural network to identify design intent and generate a target description file, and performs constraint correlation analysis and weight fusion, and then performs feasibility judgment to obtain an effective constraint set; then, the thought chain technology is used to generate a candidate architecture scheme, the XGBoost regression model is used to predict the performance indicators of the scheme, the non-dominated sorting genetic algorithm is used for optimization, and the TOPSIS method is used to determine the optimal architecture scheme; then, the target architecture scheme and the preset code template library are used to generate the target Verilog code based on the corresponding code style characteristics of the user end. In this way, based on the architecture template and the code style of the user end and by using the large language model to determine the target Verilog code, the user requirements can be accurately understood, and the syntax accuracy of the code is improved, so that the overall design cycle is greatly reduced.

[0090] As can be seen from the above embodiment, the present application determines the target Verilog code in the hardware design field based on the target architecture template and the code style of the user end and by using the large language model, and therefore, the process of determining the target Verilog code in the hardware design field based on the target architecture template and the code style of the user end and by using the large language model is described.

[0091] Referring to Figure 2 As shown in the drawings, the embodiment of the present application discloses a specific integrated circuit design Verilog code generation method based on a large language model, which comprises:

[0092] In this embodiment, the input language of the integrated circuit user end is obtained, the large language model is fine-tuned to obtain a target large language model by using the corpus in the hardware design field, and the input language is semantically analyzed based on the target large language model to obtain an analysis text. Figure 3The target description file generation schematic diagram provided for the embodiment, a target entity recognition model is determined based on a bidirectional long short-term memory network and a conditional random field, named entity recognition is performed on the parsed text by using the target entity recognition model, a performance index set is determined based on the recognition result, index text in the performance index set is matched by using a preset constraint template library, a constraint structure is determined based on a matching result, the constraint structure is converted based on a regular expression to obtain a numerical constraint, the parsed text is analyzed based on a preset natural language processing toolkit, a logical relationship between target constraints is determined by using an analysis result and the numerical constraint, an initial constraint set is constructed based on the logical relationship, index weights in the initial constraint set are determined by using a TF-IDF algorithm, a priority of a target constraint is determined based on the index weights, a target constraint set is determined by using the priority and the initial constraint set, the parsed text is recognized by using a text convolutional neural network model, and meanwhile, a keyword weight can be enhanced through an attention mechanism to obtain a design intention, the target constraint set and the design intention are integrated to obtain an integrated file, and the integrated file is converted into a target description file in a JSON format.

[0093] Figure 4The schematic diagram of a target architecture scheme provided for the embodiment is generated based on a target constraint set in the target description file, a constraint correlation degree is determined by using a correlation analysis algorithm, and a constraint correlation matrix is constructed by using the constraint correlation degree; a judgment matrix is determined by using the constraint correlation matrix, a target constraint weight is determined based on the judgment matrix and by using an analytic hierarchy process, the target constraint weight is fused into the target constraint set to obtain a fused constraint set, a constraint feasible region in the fused constraint set is determined, if an intersection of the constraint feasible regions is not an empty set, the fused constraint set is determined as an effective constraint set, a candidate architecture scheme including architecture parameters is generated based on the effective constraint set and by using a GPT-4 model, a preset architecture reasoning prompt template and a thinking chain technology, a performance dataset including historical hardware design schemes is constructed, an XGBoost regression model is trained by using the performance dataset to obtain a target regression model, the performance of the candidate architecture scheme is predicted based on the target regression model to obtain an index prediction result corresponding to the candidate architecture scheme, an index confidence interval is determined by using a Bayesian neural network, a performance prediction result is determined based on the index prediction result and the index confidence interval, a target optimization function including each optimization target is defined based on the performance prediction result, the candidate architecture scheme is multi-objective optimized based on the target optimization function and by using a non-dominated sorting genetic algorithm and a penalty function method to obtain a Pareto optimal solution set; the Pareto optimal solution set is sorted based on the target constraint weight and by using a TOPSIS method to obtain an architecture scheme sorting result including a comprehensive score, and a candidate architecture scheme with the highest comprehensive score is determined as the target architecture scheme.

[0094] Figure 5A target Verilog code generation schematic diagram provided for the embodiment is based on a basic template, an architecture template and an optimization template, and a preset code template library is constructed by using a CodeT5-Large model, a corresponding target basic template, a target architecture template and a target optimization template are determined based on an architecture type of the target architecture scheme and the preset code template library, and the target basic template, the target architecture template and the target optimization template are combined to obtain a combined template, the target architecture parameters corresponding to the target architecture scheme can be filled into the combined template by using a Jinja2 template engine and a preset parameter mapping rule set, an initial Verilog code is obtained, a syntax check is performed on the initial Verilog code by using a Verilator and an abstract syntax tree to obtain an error report, a syntax repair is performed on the initial Verilog code based on the error report to obtain a repaired Verilog code, a clustering algorithm is used to analyze the historical code of the integrated circuit user end to extract a code style feature vector, a user personal coding style is determined based on the code style feature vector, and a sequence-to-sequence model is used to perform code style conversion on the repaired Verilog code based on the user personal coding style to obtain a target Verilog code.

[0095] As can be seen from the above, the application uses a large language model to perform semantic analysis on the input language of the user end, determines a target constraint set by using a regular expression, generates a target description file by identifying a design intention, determines an effective constraint set after constraint correlation analysis and weight fusion, then uses an XGBoost regression model to predict the performance indicators of the candidate architecture scheme, performs multi-objective optimization based on a non-dominated sorting genetic algorithm to determine a target architecture scheme. In this way, the target architecture scheme and the preset code template library are used to generate a target Verilog code corresponding to the user code style features, which provides an intelligent, efficient and customizable automatic solution for integrated circuit design, and is suitable for modern chip development and digital system design scenarios with tight design cycle and limited human resources.

[0096] Correspondingly, referring to Figure 6 The application further provides an integrated circuit design Verilog code generation device based on a large language model, which comprises:

[0097] The constraint set determination module 11 is configured to perform semantic analysis on the input language of the integrated circuit user end by using a large language model, determine a performance indicator set based on the analysis result, perform template matching and conversion based on the performance indicator set and a preset constraint template library by using a regular expression to obtain numerical constraints, and determine a target constraint set based on the numerical constraints and a preset statistical method.

[0098] The weight fusion module 12 is configured to determine a hardware design intention by using a text convolutional neural network and the parsed result, perform format conversion on the target constraint set and the hardware design intention to obtain a target description file, determine a constraint correlation matrix based on the target constraint set in the target description file and by using a correlation analysis algorithm, determine a target constraint weight by using the constraint correlation matrix and an analytic hierarchy process, fuse the target constraint weight into the target constraint set, perform feasibility judgment on the obtained fused constraint set, and determine an effective constraint set based on a judgment result;

[0099] The target scheme determination module 13 is configured to generate a candidate architecture scheme including an architecture parameter based on the effective constraint set and by using a thinking chain technology reasoning, predict each performance index of the candidate architecture scheme by using an XGBoost regression model to obtain an index prediction result, perform multi-objective optimization based on the index prediction result and the candidate architecture scheme and by using a non-dominated sorting genetic algorithm to obtain a Pareto optimal solution set, and determine a target architecture scheme by using the target constraint weight and the Pareto optimal solution set and by using a TOPSIS method.

[0100] The target code determination module 14 is configured to determine an initial Verilog code based on an architecture type of the target architecture scheme and a preset code template library, perform syntax checking on the initial Verilog code, and perform syntax repair and code style conversion on the initial Verilog code based on a checking result and a code style feature corresponding to the integrated circuit user end and by using a sequence-to-sequence model to obtain a target Verilog code.

[0101] In some embodiments, the constraint set determination module 11 can specifically include:

[0102] The semantic parsing unit is configured to fine-tune a large language model by using a corpus in the field of hardware design to obtain a target large language model, obtain input language of an integrated circuit user end, and perform semantic parsing on the input language based on the target large language model to obtain parsed text.

[0103] The index set determination unit is configured to determine a target entity recognition model based on a bidirectional long short-term memory network and a conditional random field, perform named entity recognition on the parsed text by using the target entity recognition model, and determine a performance index set based on a recognition result.

[0104] The structure conversion unit is configured to perform template matching on index text in the performance index set by using a preset constraint template library, determine a constraint structure based on a matching result, and convert the constraint structure based on a regular expression to obtain a numerical constraint.

[0105] An initial set construction unit is configured to perform dependency syntax analysis on the parsed text based on a preset natural language processing toolkit, determine a logical relationship between target constraints by using analysis results and the numerical constraints, and construct an initial constraint set based on the logical relationship;

[0106] A target set determination unit is configured to determine an index weight in the initial constraint set by using a TF-IDF algorithm, determine a priority of the target constraint based on the index weight, and determine a target constraint set by using the priority and the initial constraint set.

[0107] In some embodiments, the weight fusion module 12 can specifically include:

[0108] A file conversion unit is configured to identify the parsed text by using a text convolutional neural network model to obtain a design intent, integrate the target constraint set and the design intent to obtain an integrated file, and convert the integrated file into a target description file in a JSON format.

[0109] A correlation matrix construction unit is configured to determine a constraint correlation degree by using a correlation analysis algorithm based on the target constraint set in the target description file, and construct a constraint correlation matrix by using the constraint correlation degree.

[0110] A target weight determination unit is configured to determine a judgment matrix by using the constraint correlation matrix, and determine a target constraint weight based on the judgment matrix and by using an analytic hierarchy process.

[0111] In some embodiments, the weight fusion module 12 can specifically include:

[0112] A weight fusion unit is configured to fuse the target constraint weight into the target constraint set to obtain a fused constraint set.

[0113] An intersection judgment unit is configured to determine a constraint feasible region in the fused constraint set, and judge whether an intersection of the constraint feasible region is an empty set.

[0114] An effective set determination unit is configured to determine that there is no constraint conflict if the intersection of the constraint feasible region is not an empty set, and determine the fused constraint set as an effective constraint set.

[0115] In some embodiments, the target scheme determination module 13 can specifically include:

[0116] A candidate scheme generation unit is configured to generate a candidate architecture scheme including an architecture parameter based on the effective constraint set and a preset architecture reasoning prompt template and by using a thinking chain technology reasoning.

[0117] The regression model training unit is configured to construct a performance data set including historical hardware design schemes, train an XGBoost regression model by using the performance data set, and obtain a target regression model.

[0118] The prediction result determination unit is configured to predict the performance of the candidate architecture scheme based on the target regression model, obtain an index prediction result corresponding to the candidate architecture scheme, determine an index confidence interval by using a Bayesian neural network, and determine a performance prediction result based on the index prediction result and the index confidence interval.

[0119] The scheme optimization unit is configured to define a target optimization function including optimization objectives based on the performance prediction result, perform multi-objective optimization on the candidate architecture scheme based on the target optimization function and by using a non-dominated sorting genetic algorithm and a penalty function method, and obtain a Pareto optimal solution set.

[0120] The target scheme determination unit is configured to sort the Pareto optimal solution set based on the target constraint weight and by using a TOPSIS method, obtain an architecture scheme sorting result including a comprehensive score, and determine a candidate architecture scheme with the highest comprehensive score as a target architecture scheme based on the architecture scheme sorting result.

[0121] In some embodiments, the target code determination module 14 can specifically include:

[0122] The combined template determination unit is configured to determine a corresponding combined template based on the architecture type of the target architecture scheme and a preset code template library; the code template library includes a basic template, an architecture template, and an optimization template.

[0123] The parameter filling unit is configured to fill target architecture parameters corresponding to the target architecture scheme into the combined template by using a preset template engine and a preset parameter mapping rule set, and obtain initial Verilog code.

[0124] The syntax repair unit is configured to perform syntax checking on the initial Verilog code by using a preset syntax checker and an abstract syntax tree, obtain an error report, perform syntax repair on the initial Verilog code based on the error report, and obtain repaired Verilog code.

[0125] The code conversion unit is configured to analyze historical code of the integrated circuit user end by using a clustering algorithm, obtain code style features, perform code style conversion on the repaired Verilog code based on the code style features and by using a sequence-to-sequence model, and obtain target Verilog code.

[0126] In some embodiments, the large language model-based integrated circuit design Verilog code generation device can further include:

[0127] A report extraction unit is configured to collect a synthesis report of the target Verilog code by using an EDA tool, and extract the synthesis report to obtain actual performance data.

[0128] A model updating unit is configured to construct a performance prediction error library based on the actual performance data and the index prediction result, and update the XGBoost regression model based on the performance prediction error library and by using a stochastic gradient descent algorithm.

[0129] Further, the embodiment of the present application also discloses an electronic device, Figure 7 is an electronic device 20 structure diagram according to an exemplary embodiment, the contents in the figure cannot be considered as any limitation on the use range of the present application. The electronic device 20, specifically can include: at least one processor 21, at least one memory 22, power supply 23, communication interface 24, input output interface 25 and communication bus 26. Wherein, the memory 22 is used for storing computer program, the computer program is loaded and executed by the processor 21, to realize the related steps in the foregoing any embodiment disclosed large language model-based integrated circuit design Verilog code generation method. In addition, the electronic device 20 in the embodiment of the present application can be an electronic computer.

[0130] In the embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which is not limited here; the input output interface 25 is used to obtain external input data or output data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0131] In addition, the memory 22 as the carrier of resource storage can be read-only memory, random access memory, disk or optical disk, etc., and the resources stored thereon can include operating system 221, computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0132] The operating system 221 is configured to manage and control each hardware device on the electronic device 20 and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the large language model-based integrated circuit design Verilog code generation method disclosed in any of the preceding embodiments executed by the electronic device 20, the computer program 222 can further include computer programs capable of completing other specific tasks.

[0133] Further, the present application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the large language model-based integrated circuit design Verilog code generation method disclosed in the preceding embodiments. For the specific steps of the method, please refer to the corresponding content disclosed in the preceding embodiments, which will not be repeated here.

[0134] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0135] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0136] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0137] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the stated element.

[0138] The above detailed description of the technical solutions provided by the present application has been provided, and the principles and implementation modes of the present application have been described by applying specific examples. The above description of the examples is only for the purpose of helping to understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description of the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for generating Verilog code for integrated circuit design based on a large language model, characterized in that, include: A large language model is used to perform semantic parsing on the input language of the integrated circuit user terminal, and a set of performance indicators is determined based on the parsing results. Based on the set of performance indicators and a preset constraint template library, regular expressions are used to perform template matching and transformation to obtain numerical constraints. Based on the numerical constraints and a preset statistical method, a set of target constraints is determined. The hardware design intent is determined using a text convolutional neural network and the parsing results. The target constraint set and the hardware design intent are converted into a format to obtain a target description file. Based on the target constraint set in the target description file, a constraint correlation matrix is ​​determined using a correlation analysis algorithm. The target constraint weights are determined using the constraint correlation matrix and the analytic hierarchy process (AHP). The target constraint weights are fused into the target constraint set. The feasibility of the fused constraint set is assessed, and the effective constraint set is determined based on the assessment results. Based on the effective constraint set, candidate architecture schemes including architecture parameters are generated using the thinking chain technique. The performance indicators of the candidate architecture schemes are predicted using the XGBoost regression model to obtain the indicator prediction results. Based on the indicator prediction results and the candidate architecture schemes, multi-objective optimization is performed using the non-dominated sorting genetic algorithm to obtain the Pareto optimal solution set. The target architecture scheme is determined using the target constraint weights and the Pareto optimal solution set and the TOPSIS method. Based on the architecture type of the target architecture scheme and the preset code template library, the initial Verilog code is determined. The initial Verilog code is then subjected to syntax checking. Based on the checking results and the code style characteristics corresponding to the user terminal of the integrated circuit, the initial Verilog code is subjected to syntax repair and code style conversion using a sequence-to-sequence model to obtain the target Verilog code.

2. The method for generating Verilog code for integrated circuit design based on a large language model according to claim 1, characterized in that, The process involves semantically parsing the input language from the integrated circuit user terminal using a large language model, determining a set of performance indicators based on the parsing results, performing template matching and transformation using regular expressions based on the set of performance indicators and a preset constraint template library to obtain numerical constraints, and determining a target constraint set based on the numerical constraints and a preset statistical method, including: A target large language model is obtained by fine-tuning a large language model using corpus from the hardware design field. The input language of the integrated circuit user terminal is obtained, and semantic parsing is performed on the input language based on the target large language model to obtain parsed text. A target entity recognition model is determined based on a bidirectional long short-term memory network and a conditional random field. The target entity recognition model is then used to perform named entity recognition on the parsed text, and a set of performance indicators is determined based on the recognition results. The indicator text in the performance indicator set is template matched using a preset constraint template library, and the constraint structure is determined based on the matching results. The constraint structure is then transformed using regular expressions to obtain numerical constraints. The parsed text is subjected to dependency parsing based on a pre-set natural language processing toolkit. The analysis results and numerical constraints are used to determine the logical relationship between the target constraints. An initial constraint set is constructed based on the logical relationship. The TF-IDF algorithm is used to determine the index weights in the initial constraint set, and the priority of the target constraint is determined based on the index weights. The target constraint set is then determined using the priority and the initial constraint set.

3. The method for generating Verilog code for integrated circuit design based on a large language model according to claim 2, characterized in that, The process of determining the hardware design intent using a text convolutional neural network and the parsing results, converting the target constraint set and the hardware design intent into a format to obtain a target description file, determining the constraint correlation matrix based on the target constraint set in the target description file using a correlation analysis algorithm, and determining the target constraint weights using the constraint correlation matrix and the analytic hierarchy process (AHP) includes: The parsed text is identified using a text convolutional neural network model to obtain the design intent. The target constraint set and the design intent are integrated to obtain an integrated file, and the integrated file is converted into a target description file in JSON format. Based on the target constraint set in the target description file, the constraint correlation degree is determined using a correlation analysis algorithm, and a constraint correlation matrix is ​​constructed using the constraint correlation degree. The judgment matrix is ​​determined using the constraint correlation matrix, and the target constraint weights are determined based on the judgment matrix and the analytic hierarchy process (AHP).

4. The method for generating Verilog code for integrated circuit design based on a large language model according to claim 1, characterized in that, The step of fusing the target constraint weights into the target constraint set, performing a feasibility assessment on the resulting fused constraint set, and determining the effective constraint set based on the assessment result includes: The target constraint weights are fused into the target constraint set to obtain the fused constraint set; Determine the feasible regions of constraints in the fused constraint set, and determine whether the intersection of the feasible regions of constraints is an empty set; If the intersection of the feasible regions of the constraints is not an empty set, then it is determined that there is no constraint conflict, and the fused constraint set is determined as a valid constraint set.

5. The method for generating Verilog code for integrated circuit design based on a large language model according to claim 1, characterized in that, The process involves generating candidate architecture schemes, including architectural parameters, based on the effective constraint set and using the thought chain technique; predicting various performance indicators of the candidate architecture schemes using the XGBoost regression model to obtain indicator prediction results; performing multi-objective optimization based on the indicator prediction results and the candidate architecture schemes using a non-dominated sorting genetic algorithm to obtain a Pareto optimal solution set; and determining the target architecture scheme using the objective constraint weights, the Pareto optimal solution set, and the TOPSIS method. This includes: Based on the set of effective constraints and the preset architecture reasoning prompt template, and using the thinking chain technology, candidate architecture schemes including architecture parameters are generated. A performance dataset including historical hardware design schemes is constructed, and the XGBoost regression model is trained using the performance dataset to obtain the target regression model; The performance of the candidate architecture scheme is predicted based on the target regression model to obtain the indicator prediction results corresponding to the candidate architecture scheme. The confidence interval of the indicator is determined by using a Bayesian neural network. The performance prediction result is determined based on the indicator prediction results and the indicator confidence interval. Based on the performance prediction results, a target optimization function is defined, including each optimization objective. Based on the target optimization function, a non-dominated sorting genetic algorithm and a penalty function method are used to perform multi-objective optimization on the candidate architecture scheme to obtain a Pareto optimal solution set. Based on the target constraint weights and using the TOPSIS method to sort the Pareto optimal solution set, an architecture scheme ranking result including a comprehensive score is obtained. Based on the architecture scheme ranking result, the candidate architecture scheme with the highest comprehensive score is determined as the target architecture scheme.

6. The method for generating Verilog code for integrated circuit design based on a large language model according to claim 1, characterized in that, The process involves determining initial Verilog code based on the architecture type and preset code template library of the target architecture scheme, performing syntax checks on the initial Verilog code, and then performing syntax repair and code style conversion on the initial Verilog code based on the check results and the code style characteristics corresponding to the integrated circuit user terminal, using a sequence-to-sequence model to obtain the target Verilog code. This includes: Based on the architecture type of the target architecture scheme and the preset code template library, a corresponding combined template is determined; the code template library includes basic templates, architecture templates, and optimization templates; The target architecture parameters corresponding to the target architecture scheme are filled into the combined template using a preset template engine and a preset parameter mapping rule set to obtain the initial Verilog code; The initial Verilog code is syntax-checked using a preset syntax checker and an abstract syntax tree to obtain an error report. Based on the error report, the initial Verilog code is then syntax-corrected to obtain the corrected Verilog code. The historical code of the user terminal of the integrated circuit is analyzed using a clustering algorithm to obtain code style features. Based on the code style features, the repaired Verilog code is subjected to code style conversion using a sequence-to-sequence model to obtain the target Verilog code.

7. The method for generating Verilog code for integrated circuit design based on a large language model according to any one of claims 1 to 6, characterized in that, After obtaining the target Verilog code by performing syntax repair and code style conversion on the initial Verilog code based on the inspection results and the code style features corresponding to the integrated circuit user terminal, using a sequence-to-sequence model, the process further includes: The synthesis report of the target Verilog code is collected using EDA tools, and the actual performance data is extracted from the synthesis report. A performance prediction error library is constructed based on the actual performance data and indicator prediction results. The XGBoost regression model is then updated based on the performance prediction error library and using the stochastic gradient descent algorithm.

8. A Verilog code generation device for integrated circuit design based on a large language model, characterized in that, include: The constraint set determination module is used to perform semantic parsing of the input language of the integrated circuit user terminal using a large language model, and determine the performance index set based on the parsing results. Based on the performance index set and a preset constraint template library, template matching and transformation are performed using regular expressions to obtain numerical constraints. Based on the numerical constraints and a preset statistical method, the target constraint set is determined. The weight fusion module is used to determine the hardware design intent using a text convolutional neural network and the parsing results, convert the target constraint set and the hardware design intent into a format to obtain a target description file, determine the constraint correlation matrix based on the target constraint set in the target description file and using a correlation analysis algorithm, determine the target constraint weights using the constraint correlation matrix and the analytic hierarchy process, fuse the target constraint weights into the target constraint set, perform a feasibility judgment on the obtained fused constraint set, and determine the effective constraint set based on the judgment result. The target solution determination module is used to generate candidate architecture solutions including architecture parameters based on the effective constraint set and using the thinking chain technique, predict the performance indicators of the candidate architecture solutions using the XGBoost regression model to obtain indicator prediction results, perform multi-objective optimization based on the indicator prediction results and the candidate architecture solutions using the non-dominated sorting genetic algorithm to obtain the Pareto optimal solution set, and determine the target architecture solution using the target constraint weights and the Pareto optimal solution set and the TOPSIS method. The target code determination module is used to determine the initial Verilog code based on the architecture type of the target architecture scheme and a preset code template library, perform syntax checking on the initial Verilog code, and perform syntax repair and code style conversion on the initial Verilog code based on the check results and the code style characteristics corresponding to the integrated circuit user terminal, using a sequence-to-sequence model, to obtain the target Verilog code.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the Verilog code generation method for integrated circuit design based on a large language model as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the Verilog code generation method for integrated circuit design based on a large language model as described in any one of claims 1 to 7.

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