Chip Trojan horse detection and shielding system and method based on multiple confusion links

Abstract

The invention discloses a chip Trojan horse detection and shielding system and method based on multiple confusion links, and relates to the technical field of integrated circuit safety. According to the method, a plurality of confusion links which are large in structural difference, identical in function and similar in time delay are designed for sensitive critical paths in a chip. A write-only unreadable register is adopted to store link selection information, so that an attacker is prevented from stealing or tampering a currently activated path by means of scanning a chain, debugging an interface and the like; a dual-stage operation mechanism is adopted, a test stage is combined with high-precision delay measurement and anomaly analysis to accurately identify a path in which Trojan is implanted, and a formal stage is dynamically switched to a Trojan-free path based on safety link information stored in a register, so that a chip is ensured to automatically avoid malicious logic during operation, and active defense instead of passive detection is realized. The method is superior to a traditional hardware Trojan horse protection scheme in detection precision, operation safety and implementation cost, and an efficient, reliable and easy-to-integrate solution is provided for chip safety.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit security technology, and in particular to a chip Trojan detection and shielding system and method based on multi-path obfuscation links, which is applicable to security protection in the integrated circuit design and manufacturing process. Background Technology

[0002] With the continuous globalization of integrated circuit design and manufacturing, various links in the chip supply chain (such as design, manufacturing, packaging, and testing) may be distributed in different countries and regions, leading to severe challenges to hardware security. Hardware Trojans, as a malicious circuit modification method, can be implanted during chip manufacturing or design stages, triggering under specific conditions and causing information leakage, functional tampering, or even system paralysis (Bhunia, Hsiao, Banga, & Narasimhan, 2014). Because hardware Trojans (Jin & Makris, 2008) typically possess high concealment and complex triggering conditions, traditional detection methods often struggle to effectively identify them, placing immense pressure on hardware security protection.

[0003] Currently, hardware Trojan detection technologies are mainly divided into two categories: pre-silicon verification and post-silicon testing. Pre-silicon verification relies on formal verification and simulation testing, but since hardware Trojans may only activate under specific conditions, the simulation coverage is limited, making it difficult to guarantee comprehensive detection (Tehranipoor & Koushanfar, 2010). Physical detection methods, such as side-channel analysis and destructive reverse engineering, can detect some abnormal features, but they are costly and may affect the normal function of the chip (Jin & Makris, 2008). In addition, these methods can usually only be used for detection after chip manufacturing is complete, and cannot dynamically shield the influence of Trojans during runtime.

[0004] In recent years, some studies have attempted to detect hardware Trojans through timing analysis, such as monitoring delay changes or abnormal signals in critical paths (Zhang et al., 2016). However, even if the presence of a Trojan is detected, existing technologies still lack an effective dynamic shielding mechanism and cannot automatically switch to a safe path during chip operation, leaving the system potentially vulnerable to Trojan threats (Xiao, Forte, & Tehranipoor, 2016). Therefore, a better design system is needed to address the following technical issues: (1) effectively shielding implanted malicious logic without affecting chip functionality; (2) reducing the probability of Trojans being implanted in critical signal paths. Summary of the Invention

[0005] The purpose of this invention is to provide a chip Trojan detection and shielding system and method based on multi-path obfuscation links. Through a dynamic path selection mechanism, it can effectively shield implanted malicious logic without affecting chip functionality and reduce the probability of Trojans being implanted in critical signal paths.

[0006] The present invention adopts the following technical solution:

[0007] A chip Trojan detection and shielding system based on multi-path obfuscation links includes: a multi-path obfuscation link module, used to provide multiple circuit paths with the same function, a propagation delay difference of less than a predetermined threshold, and structural differences for sensitive critical paths in the chip, wherein the original circuit is a decoy circuit; a link selection control module, connected to the multi-path obfuscation link module, used to receive control signals and dynamically select one circuit path from the multi-path obfuscation link module as the output; and a control module, connected to the link selection control module, used to perform Trojan detection on the multi-path obfuscation link module during the testing phase, and generate the control signal based on the detection results, so as to control the link selection control module to select a safe circuit path that has not been implanted with Trojans during the formal operation phase.

[0008] Furthermore, the multiple circuit paths in the multi-path obfuscation link module achieve structural diversity by employing different combinations of logic gates, wiring strategies, or redundant designs.

[0009] Furthermore, the link selection control module includes: a multiplexer, whose input is connected to the output of each circuit path in the multiplexed link module, and whose output serves as the system output; and a data register, used to store the control signal, whose output is connected to the control terminal of the multiplexer, and used to control the selection state of the multiplexer.

[0010] Furthermore, the data register is a write-only, non-readable register to prevent the currently selected path information from being read via the scan chain or debug interface.

[0011] Furthermore, during the testing phase, the control module writes the control signal containing the secure path number into the data register using a secure write protocol.

[0012] Furthermore, the secure write protocol includes digital signature verification of the control data written to the data register.

[0013] Furthermore, the control module is executed during the testing phase and specifically includes: a delay measurement unit, used to measure the propagation delay of each circuit path in the multi-path obfuscation link module; and a Trojan analysis unit, used to identify paths with abnormal delays through statistical analysis based on the propagation delay of each circuit path, in order to determine whether a hardware Trojan exists.

[0014] Furthermore, the delay measurement unit is an on-chip time-to-digital converter or is connected to an external test device.

[0015] Furthermore, the control module is also used to periodically trigger re-detection during the formal operation phase and update the control signal according to the new detection results in order to dynamically switch the safety circuit path.

[0016] Furthermore, the control module is also configured to select one of multiple safety circuit paths as the current output path using a randomization strategy.

[0017] A chip trojan detection and shielding method based on multi-path obfuscated links, applied to any of the above-described systems, the method comprising: during the testing phase, measuring the propagation delay of multiple pre-set obfuscated links in the chip that have the same function, a propagation delay difference less than a predetermined threshold, but structural differences; based on the propagation delay measurement results, identifying and determining secure links that have not been implanted with hardware trojans by analyzing the delay characteristics of each link; writing a selection control signal indicating the secure link into a data register; and during the formal operation phase, controlling a multiplexer to dynamically select the secure link based on the selection control signal in the data register, so as to shield paths that may be implanted with trojans.

[0018] Furthermore, the propagation delay measurement of the obfuscated link includes measurements under different voltage and temperature conditions to improve detection robustness.

[0019] Furthermore, the step of identifying safe links by analyzing the delay characteristics of each link includes: using statistical analysis algorithms to identify paths whose delays exceed the range of process fluctuations as abnormal paths.

[0020] Furthermore, writing the selection control signal into the data register includes writing via an encrypted communication protocol.

[0021] Furthermore, the method also includes: during the formal operation phase, periodically re-executing the steps of propagation delay measurement, security link identification, and register update to achieve dynamic monitoring and link switching.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] 1. Increase the difficulty of implanting hardware Trojans and reduce the probability of critical paths being attacked.

[0024] By designing multiple obfuscated links with significantly different structures but identical functions, attackers are forced to make it difficult to tamper with all paths simultaneously, greatly increasing the complexity and cost of implanting malware. The decoy circuit design guides attackers to prioritize implanting malware on the original path, while the backup links, due to their structural differences and stealth, are more difficult to attack successfully, thus effectively reducing the risk of critical paths being compromised.

[0025] 2. A two-stage operation mechanism enables dynamic detection and real-time shielding.

[0026] The testing phase combines high-precision delay measurement and anomaly analysis to accurately identify the path where malware has been implanted, offering higher detection efficiency and accuracy compared to traditional static detection methods (such as pre-silicon simulation or physical reverse engineering). In the formal testing phase, based on the secure link information stored in registers, the system dynamically switches to a malware-free path, ensuring the chip automatically avoids malicious logic during operation, achieving proactive defense rather than passive detection.

[0027] 3. Register control mechanisms ensure security during operation.

[0028] Write-only registers are used to store link selection information to prevent attackers from stealing or tampering with the currently active path through methods such as scanning the chain or debugging the interface. The register data is configured by trusted software or a security module, and combined with an optional hardware signature verification mechanism, it further prevents malicious tampering and ensures the reliability and security of link switching.

[0029] 4. Compatible with existing chip design flows, easy to implement and deploy.

[0030] Multi-channel obfuscation can be implemented using standard cell libraries and EDA tools without modifying existing chip manufacturing processes, reducing the cost of technology implementation. It supports multiple hardware platforms such as ASICs and FPGAs, and can be flexibly applied to critical circuits such as cryptographic coprocessors and security control modules, demonstrating broad applicability.

[0031] 5. Enhance system reliability and fault tolerance.

[0032] Optional dynamic monitoring and randomized switching strategies can periodically check link status during operation to prevent Trojans from activating under specific conditions and improve long-term security. When an anomaly is detected in the current link, the system can automatically switch to a backup path to ensure functional continuity, making it suitable for high-reliability scenarios.

[0033] 6. Overall Benefits

[0034] This invention employs a triple protection mechanism of multi-path obfuscation link induction, two-stage dynamic detection, and register security control. It outperforms traditional hardware Trojan protection schemes in terms of detection accuracy, operational security, and implementation cost, providing an efficient, reliable, and easily integrated solution for chip security. Attached Figure Description

[0035] Figure 1 A schematic diagram of the overall system of the present invention.

[0036] Figure 2 A schematic diagram of the modular multi-path obfuscation link of the present invention.

[0037] Figure 3 A schematic flowchart illustrating an embodiment of the method of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand and implement the present invention, the chip Trojan detection and shielding system based on multi-path obfuscation links described in the present invention will be described in detail below with reference to specific embodiments.

[0039] A chip-based Trojan detection and shielding system and method based on multi-path obfuscation links, such as... Figure 3 As shown:

[0040] 1. Design phase, such as Figure 1 As shown:

[0041] During the chip design phase, for critical and sensitive paths (such as encryption modules, security control units, etc.), the following operations are performed:

[0042] Multi-path obfuscation link design: such as Figure 2 As shown, multiple obfuscated links with the same function but different structures are generated using logic synthesis tools (such as Synopsys DesignCompiler). For example, different combinations of logic gates are used (such as replacing equivalent logic with NAND / NOR); different routing strategies are adopted (such as adding redundant buffers or inverter chains); and asymmetric routing is used during layout to increase physical layer differences.

[0043] Static timing analysis (STA) ensures that the propagation delays of each obfuscated link are similar (with differences controlled within ±5%), thus avoiding timing violations caused by delay differences.

[0044] Decoy circuit optimization: The original circuit, as a decoy link, can have its protection strength appropriately reduced (e.g., by reducing randomization processing) to attract attackers to prioritize implanting Trojans into this path.

[0045] For sensitive critical paths within the chip (such as encryption modules and security control units), multiple obfuscated links with significantly different structures but identical functions and similar delays are designed. The original circuit serves as a decoy circuit, designed to induce attackers to implant malware in that path first. The backup links employ different logic structures or layout routing methods to increase the difficulty for attackers to simultaneously tamper with all links. Each obfuscated link must meet the following requirements:

[0046] Functional consistency: All links output the same result under normal input conditions;

[0047] Delay similarity: The propagation delays of each link are similar to avoid timing anomalies caused by delay differences;

[0048] Structural diversity: Employing different combinations of logic gates, wiring strategies, or redundant designs increases the difficulty for attackers to reverse engineer.

[0049] 2. Manufacturing stage

[0050] The following hardware modules need to be integrated during the chip manufacturing stage:

[0051] Link selection control module

[0052] This module consists of a multiplexer (MUX) and a data register, used to dynamically switch between different obfuscated links. Its specific functions are as follows:

[0053] Multiplexer (MUX): Receives the output signals of all confused links and selects one of them as the final output according to the control word in the register;

[0054] Data register: Stores link control data written by software, used to indicate the clean link (the link that has not been infected with malware) that should be selected at the moment.

[0055] To enhance security, registers can be designed to be write-only, preventing attackers from obtaining information about currently active links by scanning the chain or debugging the interface.

[0056] Multiplexer (MUX): Employing a low-latency, high-reliability MUX design (such as based on transmission gates or tree-structured selection) ensures that the switching process does not affect the timing of critical paths. The control terminal of the MUX is connected to a security register to prevent unauthorized access and tampering.

[0057] Data registers: Write-only registers are used to prevent attackers from stealing the currently selected link information through chain scanning or debugging interfaces. An optional integrated hardware signature verification module ensures that written link control data is authenticated (e.g., HMAC verification).

[0058] 3. Testing Phase

[0059] Before the chip leaves the factory or during power-on initialization, it enters the testing phase. The specific process is as follows:

[0060] Delay measurement: Acquire propagation delay data of each obfuscated link using on-chip measurement circuitry (such as a time-to-digital converter, TDC) or external test equipment (such as an oscilloscope or ATE instrument). Measurements should cover various operating voltage and temperature conditions (such as ±10% voltage fluctuation, 0°C to 85°C) to improve detection robustness.

[0061] Trojan analysis: Measurement data is received through software API interfaces (such as JTAG or dedicated security bus), and anomalies are analyzed using the following algorithms:

[0062] Statistical analysis: By comparing the delay distribution of each link, abnormal paths that exceed the range of process fluctuations (such as sudden increase in delay, signal distortion, 3σ principle) are identified, and it is determined whether there is any Trojan horse implantation.

[0063] Register configuration: The analysis results (i.e., the link IDs without malware) are stored in the data register via a secure write protocol (such as encrypted communication). Optional support for multiple register backups is available to address the risk of single point of failure.

[0064] 4. Formal Operation Phase

[0065] After the chip enters normal operating mode, it performs the following operations:

[0066] Automatic link switching: The multiplexer automatically selects a verified secure link based on the control word stored in the register, blocking paths that may be compromised by malware. The switching process must be completed within a single clock cycle to avoid introducing additional latency.

[0067] Dynamic monitoring (optional): During operation, a re-detection mechanism can be periodically triggered (e.g., re-measuring link latency every 24 hours) to address potential Trojan activation or aging effects. Upon detecting an anomaly, automatic switch to a backup link is initiated, and the security processor is notified of the interruption.

[0068] Optional enhancements

[0069] To further enhance system security, the following technologies can be combined:

[0070] Randomized switching strategy: After the testing phase, different clean links are randomly selected to prevent attackers from predicting the currently used path through long-term observation;

[0071] Hardware signature verification: Digital signature verification is performed on the control data written to the register to prevent attackers from tampering with the link selection signal;

[0072] Fault tolerance mechanism: When an anomaly is detected in the current link, the system automatically switches to a backup link to ensure continuous operation.

[0073] 5. Examples

[0074] Taking an AES encryption chip as an example, the specific implementation of this invention is illustrated below:

[0075] Design phase: Design three obfuscation links in the S-box module of AES, which are implemented using combinational logic, lookup table (LUT) and pipeline structure respectively, to ensure functional consistency and latency difference ≤50ps.

[0076] Manufacturing stage: Integrate a 4:1 multiplexer and a 128-bit security register, which is written via AES-GCM encryption protocol.

[0077] During the testing phase, the on-chip TDC was used to measure the latency of each link, and an abnormal increase (+15% latency) was found in link 2. The numbers of links 1 and 3 were written to the register through the security API.

[0078] In full operation: MUX selects link 1 as the primary path, and switches to link 3 if an anomaly is detected.

[0079] 6. Optional extensions

[0080] Randomized switching: Randomly rotating the switches in the secure link (e.g., switching every hour) increases the difficulty for attackers to predict.

[0081] Fault tolerance and redundancy: Designed with N+1 backup links to support multiple failovers.

[0082] Through the above implementation methods, the present invention can achieve efficient detection and dynamic blocking of hardware Trojans throughout the entire lifecycle of design, manufacturing, testing and operation, combining security and practicality.

Claims

1. A chip Trojan detection and shielding system based on multi-path confusion link, characterized in that, The system comprises: a plurality of obfuscated link modules for providing a plurality of circuit paths with same function, less than a predetermined threshold of propagation delay difference and structural difference for a sensitive critical path in a chip, wherein the original circuit is a decoy circuit; a link selection control module connected with the plurality of obfuscated link modules for receiving a control signal and dynamically selecting one circuit path in the plurality of obfuscated link modules as an output; a control module connected with the link selection control module for Trojan detection of the plurality of obfuscated link modules in a test phase and generating the control signal according to the detection result to control the link selection control module to select a secure circuit path without Trojan implantation in an official running phase.

2. The system according to claim 1, wherein, The plurality of circuit paths in the plurality of obfuscated link modules achieve structural diversity by using different logic gate combinations, wiring strategies or redundancy designs.

3. The system according to claim 1, wherein, The link selection control module comprises: a multiplexer with input ends connected with output ends of each circuit path in the plurality of obfuscated link modules and an output end as a system output; and a data register for storing the control signal and with an output end connected with a control end of the multiplexer for controlling a gating state of the multiplexer.

4. The system according to claim 3, wherein, The data register is a write-only non-readable register to prevent reading of the currently selected path information through a scan chain or a debugging interface.

5. The system according to claim 3, wherein, The control module writes the control signal containing a secure path number into the data register through a secure writing protocol in the test phase.

6. The system according to claim 5, wherein, The secure writing protocol comprises digital signature verification of control data written into the data register.

7. The system according to claim 1, wherein, The control module is executed in the test phase and specifically comprises: a delay measurement unit for measuring propagation delays of each circuit path in the plurality of obfuscated link modules; and a Trojan analysis unit for identifying a path with abnormal delay through statistical analysis according to the propagation delays of each circuit path to determine whether there is a hardware Trojan.

8. The system according to claim 7, wherein, The delay measurement unit is an on-chip time-to-digital converter or an external test device.

9. The system according to claim 1, wherein, The control module is further configured to periodically trigger re-detection in the official running phase and update the control signal according to new detection results to dynamically switch secure circuit paths.

10. The system of claim 1, wherein, The control module is further configured to select one secure circuit path as a current output path by using a randomization strategy.

11. A chip Trojan detection and shielding method based on a multi-path confusion link, characterized in that, The method applied to the system of any one of claims 1-10 comprises: in a test phase, measuring propagation delays of a plurality of obfuscated links with same function, less than a predetermined threshold of propagation delay difference and structural difference in a chip; based on the propagation delay measurement results, identifying and determining secure links without hardware Trojan implantation by analyzing delay characteristics of each link; writing a selection control signal indicating the secure links into a data register; and in an official running phase, controlling a multiplexer to dynamically select the secure links based on the selection control signal in the data register to shield paths possibly implanted with Trojans.

12. The method of claim 11, wherein, The propagation delay measurement of the obfuscated links comprises measurement under different voltage and temperature conditions to improve detection robustness.

13. The method of claim 11, wherein the method further comprises: The identifying the safe link by analyzing delay characteristics of each link comprises: using a statistical analysis algorithm to identify a path with a delay exceeding a process fluctuation range as an abnormal path.

14. The method of claim 11, wherein, The writing the selection control signal into the data register comprises writing through an encryption communication protocol.

15. The method of claim 11, wherein, The method further comprises: periodically re-executing the steps of propagating delay measurement, identifying the safe link and updating the register in an official operation stage, so as to realize dynamic monitoring and link switching.

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