A wafer defect detection method and system based on YOLO-Label comparison

Abstract

The application provides a wafer defect detection method and system based on YOLO-Label comparison, comprising: obtaining a wafer image to be detected, performing adaptive accelerated non-local mean filtering denoising and adaptive multi-scale gradient enhancement Canny edge detection on the wafer image to be detected, and obtaining a binary edge image; inputting the binary edge image into a pre-trained target detection model to obtain target positioning information in the YOLO-Label format, wherein the model is obtained by training a YOLOv8n network that is lightened by Ghost convolution and is adapted to a single channel, using a wafer binary image sample set; comparing the target positioning information of the image to be detected with standard positioning information of a defect-free image, extracting feature points of a bounding box, calculating an Euclidean distance matrix, and based on threshold matching, determining missing defects or redundant defects. The application can realize high-precision, high-efficiency and high-robustness wafer defect automatic detection with less labeled data under complex imaging conditions, and significantly improves the detection speed and integrity.

Description

Technical Field

[0001] This invention relates to the fields of image processing and deep learning technology, and in particular to a wafer defect detection method and system based on YOLO-Label matching. Background Technology

[0002] In the semiconductor manufacturing industry, wafer processing yield is a core indicator determining production costs and product reliability. Scanning electron microscopes are key equipment for observing nanoscale defects on wafer surfaces, and the massive amounts of high-resolution images they generate have created an urgent need for automated defect detection technologies.

[0003] Currently, mainstream automated inspection technologies mainly rely on two types of solutions: one is the die-to-die comparison method based on traditional image processing. This method locates defects through complex image registration and pixel-level difference analysis. Although intuitive, it has extremely high computational complexity and is highly sensitive to changes in imaging conditions such as illumination and noise, resulting in insufficient detection accuracy and low efficiency, making it difficult to meet the requirements of online real-time inspection. The other is the target detection method based on deep learning, such as the YOLO series of algorithms. Although these methods have fast recognition speed, their performance heavily depends on large-scale, high-quality labeled datasets. In scenarios such as semiconductor manufacturing, where labeling costs are extremely high and defect morphologies are diverse, model training is difficult, and they are prone to missed detections and false detections on wafer images with low signal-to-noise ratios and complex textures, resulting in insufficient robustness. Furthermore, neither traditional methods nor deep learning methods have effectively resolved the fundamental contradiction of the difficulty in simultaneously achieving detection accuracy, processing efficiency, and system robustness. Traditional bare-film to bare-film comparison is too time-consuming, deep learning is too picky about data and environment, and simple image preprocessing is prone to losing key details or introducing artifacts. As a result, the existing technology system often fails to meet the complex and ever-changing detection tasks in actual production lines.

[0004] Therefore, the industry urgently needs an innovative solution that can break free from the dependence on massive amounts of labeled data and ideal imaging environments, and can efficiently, accurately and stably complete the detection of various defects. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a wafer defect detection method and system based on YOLO-Label alignment to solve the problems of insufficient detection accuracy and completeness, low processing efficiency that cannot meet real-time requirements, and poor system robustness that depends on ideal imaging conditions in existing wafer defect detection methods.

[0006] On one hand, the present invention provides a wafer defect detection method based on YOLO-Label alignment, the method comprising:

[0007] Acquire an image of the wafer to be inspected;

[0008] The image of the wafer to be detected is subjected to denoising and edge enhancement processing to obtain a binary edge image representing the outline of the wafer pattern;

[0009] The binary edge image is input into a pre-trained target detection model to obtain target localization information in YOLO-Label format output by the target detection model; wherein, the target detection model is obtained by training a lightweight modified YOLOv8n network using a wafer binary image sample set, the lightweight modification including replacing some standard convolutions of the standard YOLOv8n network with Ghost convolutions and adapting the number of input channels to a single channel;

[0010] The target positioning information of the wafer image to be inspected is compared with the standard target positioning information corresponding to the defect-free wafer image, and the location and type of defects in the wafer image to be inspected are determined based on the comparison results.

[0011] In some embodiments of the present invention, denoising the image of the wafer to be inspected includes:

[0012] The image of the wafer to be inspected is filtered and denoised using an adaptive accelerated nonlocal mean filtering algorithm.

[0013] In some embodiments of the present invention, an adaptively accelerated nonlocal mean filtering algorithm is used, including:

[0014] Based on the periodic texture features and local regional characteristics of the wafer image, the search radius of different regions is dynamically allocated to accelerate the filtering process.

[0015] In some embodiments of the present invention, the image of the wafer to be inspected is subjected to denoising and edge enhancement processing, including:

[0016] An adaptive multi-scale gradient-enhanced Canny edge detection algorithm is used to extract edges from the denoised wafer image to obtain the binary edge image.

[0017] In some embodiments of the present invention, an adaptive multi-scale gradient enhancement Canny edge detection algorithm is employed, including:

[0018] The maximum inter-class variance method is used to adaptively set the high and low thresholds for edge detection, and gradient enhancement is performed in multiple directions to distinguish real edges from noise.

[0019] In some embodiments of the present invention, comparing the target positioning information with standard target positioning information corresponding to a defect-free wafer image includes:

[0020] Preset feature points of each target bounding box are extracted from the target positioning information of the wafer image to be inspected and the standard target positioning information of the defect-free wafer image, respectively.

[0021] Calculate the distance matrix between the feature points of the wafer image to be inspected and the feature points of the defect-free wafer image;

[0022] Based on a preset distance threshold, and according to the matching results of the distance matrix, it is determined whether there are missing or redundant defects in the wafer image to be detected.

[0023] In some embodiments of the present invention, the preset feature point is the coordinates of the upper left corner vertex of the bounding box.

[0024] In some embodiments of the present invention, the wafer binary image sample set is obtained by denoising, edge enhancement and image segmentation of the original wafer image, and includes at least one defect morphology among lithographic failure, scratches, dirt, particles and holes.

[0025] On the other hand, the present invention also provides a wafer defect detection system based on YOLO-Label matching, including a processor, a memory, and a computer program / instructions stored in the memory. The processor is used to execute the computer program / instructions. When the computer program / instructions are executed, the system implements the steps of any of the methods mentioned above.

[0026] On the other hand, the present invention also provides a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implement the steps of any of the methods mentioned above.

[0027] This invention provides a wafer defect detection method and system based on YOLO-Label alignment, achieving a significant overall performance improvement in the field of wafer defect detection. Specific beneficial effects include:

[0028] High detection accuracy and completeness: Through an innovative defect determination mechanism based on YOLO-Label comparison, it can accurately locate both missing and redundant defects simultaneously, solving the pain point of traditional methods being insensitive to missing defects. Combined with high-quality edge feature extraction at the front end and a high-precision lightweight target detection model (Ghost-Light-YOLOv8n network), it achieves complete capture of multiple defect morphologies.

[0029] Significantly improved processing efficiency: By adopting a dynamically accelerated filtering algorithm, Ghost-Light-YOLOv8n network structure, and a comparison method based on location information, the computational efficiency of each stage from preprocessing, identification to decision-making is significantly improved, reducing the defect detection time of a single image from seconds to sub-seconds, fully meeting the stringent requirements of online real-time detection.

[0030] The system is highly robust: the adaptive threshold setting and multi-scale enhancement mechanism in the preprocessing stage enable the system to adapt to complex industrial environmental changes such as uneven illumination and noise interference. It can maintain a stable high detection rate even under low signal-to-noise ratio conditions, reducing the dependence on ideal imaging conditions and massive labeled data.

[0031] The solution has outstanding practical value in engineering: the whole solution forms a fully automated processing chain from image input to defect reporting, which greatly improves processing speed and stability while ensuring high accuracy, and provides semiconductor manufacturing production lines with an efficient, reliable and deployable defect detection solution.

[0032] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, and will also become apparent in part to those skilled in the art upon studying the description, or may be learned by practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the description and drawings.

[0033] Those skilled in the art will understand that the objectives and advantages achievable with the present invention are not limited to those specifically described above, and that the above and other objectives achievable with the present invention will become clearer from the following detailed description. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, are not intended to limit the scope of the invention. In the drawings:

[0035] Figure 1 This is a schematic diagram of the steps of a wafer defect detection method based on YOLO-Label alignment in one embodiment of the present invention.

[0036] Figure 2 This is a schematic flowchart of a wafer defect detection method based on YOLO-Label alignment in one embodiment of the present invention.

[0037] Figure 3 This is a comparison chart of the denoising effects of different filtering algorithms in one embodiment of the present invention.

[0038] Figure 4 This is a comparison diagram of the effects of different edge detection methods in one embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of defect detection by comparison in one embodiment of the present invention, wherein (a) is a schematic diagram of standard target positioning information corresponding to a defect-free wafer image, (b) is a schematic diagram of target positioning information of the wafer image to be detected, (c) is a schematic diagram of defect detection obtained after comparison, and (d) is a schematic diagram of the corresponding real wafer defect. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0041] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0042] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0043] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0044] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar parts, or the same or similar steps.

[0045] It should be emphasized here that the step markers mentioned below are not a limitation on the order of the steps, but should be understood as meaning that the steps can be executed in the order mentioned in the embodiments, or in a different order than in the embodiments, or several steps can be executed simultaneously.

[0046] To address the shortcomings of existing wafer defect detection methods, such as insufficient detection accuracy and completeness, low processing efficiency failing to meet real-time requirements, and poor system robustness dependent on ideal imaging conditions, this invention provides a wafer defect detection method based on YOLO-Label alignment, such as... Figure 1 As shown, the method includes the following steps S101~S104:

[0047] Step S101: Obtain an image of the wafer to be inspected.

[0048] Step S102: Denoise and edge enhancement processing is performed on the wafer image to be detected to obtain a binary edge image representing the wafer pattern contour.

[0049] Step S103: Input the binary edge image into the pre-trained target detection model to obtain target localization information in YOLO-Label format output by the target detection model. The target detection model is obtained by training a lightweight modified YOLOv8n network using a wafer binary image sample set. The lightweight modification includes replacing some standard convolutions of the standard YOLOv8n network with Ghost convolutions and adapting the number of input channels to a single channel.

[0050] Step S104: Compare the target positioning information of the wafer image to be inspected with the standard target positioning information corresponding to the defect-free wafer image, and determine the location and type of defects in the wafer image to be inspected based on the comparison results.

[0051] like Figure 2 The diagram shown is a flowchart of a wafer defect detection method based on YOLO-Label matching.

[0052] In step S101, an image of the wafer to be inspected is acquired, providing a raw digital carrier containing all surface information (including normal patterns and various defects) for all subsequent processing steps.

[0053] In some embodiments, the wafer image to be inspected is primarily derived from a scanning electron microscope (SEM), but is not limited to SEM images. Any digital image capable of providing sufficient resolution to clearly depict the geometric contours of the wafer surface pattern can be used as the wafer image to be inspected as input to this invention.

[0054] Raw wafer images (especially SEM images) obtained directly often have characteristics such as high noise, complex periodic textures, non-uniform lighting, and diverse defect morphologies and varying sizes. These factors make it extremely difficult to stably and accurately locate defects directly from raw wafer images. Therefore, this invention provides a wafer defect detection method based on YOLO-Label matching to solve the above-mentioned technical problems.

[0055] In step S102, the wafer image to be inspected is subjected to denoising and edge enhancement processing to obtain a binary edge image representing the wafer pattern outline. The core purpose of step S102 is to suppress noise and enhance edges, ultimately outputting a binary edge image that retains only the clear outline of the wafer pattern.

[0056] In some embodiments, the adaptive accelerated nonlocal mean (AA-NLM) filtering algorithm is used to denoise the wafer image to be inspected.

[0057] Specifically, this algorithm is an improvement upon the traditional nonlocal mean algorithm. Its core operation is that, for each pixel in the image to be processed, the algorithm searches for all regions within a defined search window that have a similar local neighborhood structure to that pixel. It calculates the grayscale similarity weight between the center pixels of these similar regions and the current pixel, and then performs a weighted average to obtain the new denoised value for that pixel. This method effectively utilizes the redundant information within the image itself (such as the periodic patterns of a wafer), preserving edge and texture details exceptionally well while removing noise.

[0058] To overcome the computationally intensive nature of traditional algorithms, this invention introduces an adaptive acceleration mechanism. This mechanism first calculates local feature maps of the image (such as gradient magnitude or variance) to distinguish between pattern edge regions and flat background regions. During non-local mean filtering, the system dynamically allocates the search radius based on the region type of each pixel. For example, for regions determined to be important edges, the system allocates a larger search radius (e.g., 5 pixels) to ensure sufficient similar blocks are found from periodic textures for high-quality filtering; for flat background regions, a very small search radius is allocated, such as 1 pixel, or even no search is performed, directly using the region's own information, thus avoiding a large amount of unnecessary redundant computation.

[0059] like Figure 3 As shown, the images compare the denoising effects of different filtering algorithms. (a) to (h) are the original image of the wafer to be detected and the images processed by Gaussian filtering, bilateral filtering, traditional NLM filtering, Gaussian-edge detection, bilateral-edge detection, and NLM-edge detection algorithms, respectively.

[0060] Experiments have shown that the adaptive accelerated nonlocal mean filtering algorithm of this invention improves the image signal-to-noise ratio by 8-10 dB after denoising, while reducing the computation time by about 85% compared with the traditional NLM algorithm.

[0061] In some embodiments, the adaptive multi-scale gradient enhancement Canny (OTSU-MSGE-Canny) edge detection algorithm is performed on the denoised clear grayscale image to extract the edges of the pattern and generate the final binary edge image.

[0062] Specifically, the performance of traditional Canny edge detectors is highly dependent on manually set high and low thresholds and is sensitive to noise, easily producing edge breaks or false edges in low signal-to-noise ratio scenarios such as wafer images. Therefore, this invention makes two innovative improvements: introducing adaptive threshold setting and multi-scale gradient enhancement.

[0063] In some embodiments, an adaptive threshold setting is introduced, including:

[0064] The gradient magnitude and direction of an image are calculated using differential operators such as the Sobel operator.

[0065] Subsequently, the Otsu's method (Otsu's method) is used to automatically determine the optimal global threshold for distinguishing edges from non-edges. Specifically, the algorithm iterates through all possible grayscale thresholds in the gradient image and calculates the inter-class variance after dividing pixels into foreground (edge ​​candidates) and background classes using the grayscale threshold as the boundary. The threshold that maximizes the inter-class variance is the optimal segmentation threshold. Based on this, the high and low thresholds required by the Canny algorithm can be automatically set. For example, when the optimal segmentation threshold T is calculated... best When the value is 50, the system automatically adjusts the low threshold T. low Set to 0.75T best That is, the low threshold T low The value is 37.5; the high threshold T is set. high Set as 1.5T best That is, the high threshold T high The value is 75. This mechanism completely eliminates the need for manual parameter tuning, enabling the algorithm to adapt to different imaging conditions.

[0066] In some embodiments, before applying the above threshold for edge determination, a multi-scale gradient enhancement mechanism is introduced to improve the ability to distinguish true edges, including:

[0067] The gradient neighborhood of each pixel is analyzed in multiple directions (e.g., 0°, 45°, 90°, 135°). Specifically, for each direction, a weighted sum of gradients within a certain neighborhood (e.g., a 3x3 window) is calculated, with the weights ensuring consistency between the gradient direction of the center pixel and its neighborhood directions. Then, a non-linear enhancement function (e.g., a sigmoid function or a custom threshold function) is applied to these multi-directional gradient responses. This function is designed to significantly enhance points with strong, continuous responses in multiple directions (corresponding to true edges), while effectively suppressing points that only appear in a single direction or have isolated responses (corresponding to noise).

[0068] like Figure 4The figure shows a comparison of the performance of different edge detection methods, including Sobel, Roberts, Prewitt, traditional Canny, and the adaptive multi-scale gradient enhancement Canny edge detection algorithm (OTSU-MSGE-Canny) of this invention. The Sobel algorithm has a recall rate of 73.76% and a signal-to-noise ratio (SNR) of 45.67 dB; the Roberts algorithm has a recall rate of 66.05% and an SNR of 45.04 dB; the Prewitt algorithm has a recall rate of 75.37% and an SNR of 45.66 dB; the traditional Canny algorithm has a recall rate of 18.19% and an SNR of 39.49 dB; and the OTSU-MSGE-Canny algorithm provided by this invention has a recall rate of 92.41% and an SNR of 48.45 dB.

[0069] Finally, the enhanced gradient image is used to perform initial edge point filtering using the adaptively set high threshold from the previous step, resulting in strong edges. Then, a low threshold is used to find connected weak edge points in the neighborhood of the strong edges, completing the edge connection. Finally, all pixels identified as edges are set to white, and non-edge pixels are set to black, outputting a binary edge image with clear and continuous edges and almost no noise.

[0070] In step S103, the binary edge image is input into the pre-trained target detection model to obtain target localization information in YOLO-Label format output by the target detection model.

[0071] First, the structure and training of the model will be explained.

[0072] The basic model selected for this invention is YOLOv8n, a target detection network that achieves a good balance between speed and accuracy. In order to make it more suitable for the specific task of wafer defect detection and meet the stringent real-time requirements of industrial scenarios, two key structural modifications were made, collectively referred to as lightweight modifications.

[0073] First, computational efficiency was optimized. Some standard convolutional layers in the network's backbone and neck were replaced with Ghost convolutional modules. Standard convolutional layers require learning a separate set of convolutional kernels for each output channel, resulting in significant computational and parameter requirements. Ghost convolution employs a more efficient strategy: it first generates a subset of intrinsic feature maps using a small number of standard convolutions, then applies a series of inexpensive, linear transformations (such as pointwise convolutions) to these feature maps to generate more feature maps in a phantom manner. Finally, the intrinsic and phantom feature maps are concatenated to form a complete output channel. This design significantly reduces the model's computational complexity and parameter count while maintaining rich feature representation. This modification greatly reduces the model's computational burden.

[0074] Secondly, input adaptation optimization is performed. Standard object detection networks are typically designed to process three-channel color (RGB) images. However, the input of this invention is a preprocessed single-channel binary edge image. Directly using a three-channel network would introduce a large amount of redundant computation for images lacking color information. Therefore, the number of input channels of the network is adapted from 3 to 1, removing redundant structures related to color processing, making the network architecture perfectly match the data type of the input, and further improving inference efficiency.

[0075] After the above modifications, the resulting lightweight YOLOv8n network achieves a significant reduction in the number of parameters and computational cost while maintaining high recognition accuracy, and a substantial improvement in inference speed. To reflect its lightweight characteristics and core improvements, it is referred to as the Ghost-Light-YOLOv8n network in this invention. This lightweight network provides the core model foundation for subsequent efficient and accurate target localization.

[0076] In some embodiments, the training method for the object detection model includes:

[0077] A binary image sample set for wafers is constructed. The preparation process of this dataset is consistent with the aforementioned preprocessing step S102: by performing adaptive accelerated nonlocal mean filtering and adaptive multi-scale gradient enhanced Canny edge detection on the original wafer image, such as a scanning electron microscope image, binary edge images are obtained and segmented into uniform sizes (e.g., 512×512 pixels) as needed. This dataset comprehensively covers common defect types in semiconductor manufacturing, including but not limited to lithography failures, scratches, dirt, particle contamination, and voids.

[0078] During the training phase, a key definition of the model's task objective was established: the model's learning objective is not to distinguish between normal patterns and defects, but rather to uniformly identify all connected, salient white regions in a binary image as targets. This means that whether it's a complete circuit pattern or an abnormal white block caused by a defect (such as edge remnants left by missing patterns, newly added particles, or scratches), the model will output a localization bounding box for it. This design strips away complex semantic classification, allowing the model to focus on the geometric presence detection and localization of targets.

[0079] Experiments have shown that the Ghost-Light-YOLOv8n network converges after being fully trained using a wafer binary image sample set (e.g., 100 epochs with a batch size of 8). Performance evaluations show that this lightweight model achieves a significant efficiency improvement while maintaining high accuracy: on the test set, its average accuracy (mAP@0.5) reaches 97.57%, a loss of only 0.07% compared to the original YOLOv8n's 97.64%; while the inference speed is improved to 156 FPS, an improvement of approximately 28.9% compared to the original model's 121 FPS.

[0080] In the application phase, the binary edge image generated in step S102 is input into the trained target detection model, and the model performs forward inference.

[0081] The core function of the model is to output target localization information, which uses the industry-standard YOLO-Label format. For each target (white area) detected in the image, YOLO-Label provides a line of data, typically including: target category, x-coordinate of the target bounding box center point, y-coordinate of the center point, width of the bounding box, and height of the bounding box. These coordinates and dimensions are all normalized (relative to the image width and height), forming a standardized location description that is independent of image resolution.

[0082] In step S104, the target location information of the wafer image to be inspected is compared with the standard target location information corresponding to the defect-free wafer image. Based on the comparison result, the location and type of defects in the wafer image to be inspected are determined. The purpose of this step is to use the extracted location information and efficient logical operations to accurately determine the existence, location, and type of defects, thereby completing the closed loop from detection to determination. This step completely eliminates the high-complexity calculation of pixel-by-pixel comparison in the traditional D2D (die-to-die) method, achieving a leap in efficiency.

[0083] The target positioning information of the wafer image to be inspected is the target positioning information corresponding to the wafer to be inspected obtained through steps S101 to S103. The standard target positioning information corresponding to the defect-free wafer image is pre-stored, corresponding to the standard target positioning information of the defect-free standard wafer image under the same design rule. This standard target positioning information can be obtained by processing the known good (Golden Die) image through steps S101 to S103 (image acquisition, preprocessing, model inference) and stored in the database.

[0084] In some embodiments, the comparison process includes the following steps:

[0085] First, perform feature point extraction and representation simplification. For the convenience of calculation, a representative feature point is extracted from each target localization information (i.e., each bounding box). The selection of this feature point should comprehensively reflect the position and size information of the target.

[0086] In a preferred embodiment, the upper left vertex coordinates of the bounding box are selected as the feature point. This selection is because in the wafer image, the patterns usually have a regular arrangement, the upper left vertex position is relatively stable, and the calculation is simple. Of course, the center point or other geometric points that can uniquely determine the position of the bounding box can also be used as alternative solutions.

[0087] Secondly, perform distance calculation and matching association. Calculate the Euclidean distance between all feature points in the target localization information of the wafer image to be detected and all feature points in the corresponding standard target localization information of the defect-free wafer image, forming a distance matrix D. Then, perform a matching determination according to a preset distance threshold T (for example, T = 0.03, which is determined through experiments and can tolerate small positioning deviations). If D(i,j) < T, it is considered that the i-th target in the wafer image to be detected successfully matches the j-th target in the defect-free wafer image, corresponding to a normal and correctly positioned pattern.

[0088] Finally, perform defect logic determination and classification. Based on the above matching results, defects can be quickly and clearly determined through set difference operations:

[0089] Extra defects (such as dirt, particles, abnormal protrusions or incorrect patterns): In the target localization information of the wafer image to be detected, all targets corresponding to feature points that cannot find matching objects in the standard target localization information (that is, for this target, the distances to all standard targets are greater than the threshold T) are determined as extra defects. This indicates that there are additional targets in the image to be detected that are not in the standard image.

[0090] Missing defects (such as pattern missing or holes caused by lithography failure): In the standard target localization information, all standard targets that cannot find matching objects in the target localization information of the wafer image to be detected are determined as missing defects. This indicates that the targets that should be in the standard image are missing or not fully presented in the image to be detected.

[0091] As Figure 5 shown, (a) is a schematic diagram of the standard target localization information corresponding to the defect-free wafer image, (b) is a schematic diagram of the target localization information of the wafer image to be detected. After comparison, (c) is a schematic diagram of defect detection, and (d) is a schematic diagram of the corresponding real wafer defect. Among them, Fig0 represents the defect-free wafer, and Fig1 represents the wafer to be detected.

[0092] In some embodiments, the matching process itself also implicitly detects defects with severe shape or size abnormalities. If the bounding box position (represented by feature points) of a target successfully matches a standard target, but the width or height of its bounding box differs significantly from the matched standard target, it can be marked as a deformation defect in this step.

[0093] In some embodiments, after the above logical determination is completed, the defect determination result is mapped back to the original image space of the wafer to be inspected. Specifically, based on the bounding box coordinates (given in YOLO-Label) corresponding to the target determined to be a defect, a positioning box with a category label (such as Missing or Extra) is drawn on the original image or the preprocessed image, thereby generating an intuitive defect detection report.

[0094] This YOLO-Label-based comparison method transforms the defect detection problem into a point set matching and set comparison problem with extremely low computational complexity. Experiments have shown that this method significantly reduces the D2D defect determination time for a single image from the second level (e.g., 3.2 seconds) of traditional pixel comparison methods to the sub-second level (e.g., 0.8 seconds), improving efficiency by over 60%, while maintaining extremely high accuracy. It can reliably detect both missing and redundant defects, which are difficult for traditional algorithms to handle simultaneously. This signifies that the technical solution of this invention has achieved fully automated, highly efficient, and highly accurate processing from image input to final defect reporting.

[0095] Corresponding to the above method, the present invention also provides a wafer defect detection system based on YOLO-Label comparison. The system includes a processor, a memory, and a computer program / instructions stored in the memory. The processor is used to execute the computer program / instructions. When the computer program / instructions are executed, the system implements the steps of the method described above.

[0096] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the aforementioned method. The computer-readable storage medium may be a tangible storage medium, such as random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, floppy disk, hard disk, removable storage disk, CD-ROM, or any other form of storage medium known in the art.

[0097] Those skilled in the art will understand that the exemplary components, systems, and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Whether implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. When implemented in hardware, it can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the desired tasks. The programs or code segments can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave.

[0098] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0099] In this invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations of the embodiments of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer defect detection method based on YOLO-Label alignment, characterized in that, The method includes: Acquire an image of the wafer to be inspected; The image of the wafer to be detected is subjected to denoising and edge enhancement processing to obtain a binary edge image representing the outline of the wafer pattern; The binary edge image is input into a pre-trained target detection model to obtain target localization information in YOLO-Label format output by the target detection model. The target detection model is obtained by training a lightweight modified YOLOv8n network using a wafer binary image sample set. The lightweight modification includes replacing some standard convolutions in the backbone and neck networks of the standard YOLOv8n network with Ghost convolution modules and adapting the number of input channels to a single channel. The wafer binary image sample set is obtained by denoising, edge enhancement, and image segmentation of the original wafer image, and is labeled with at least one defect morphology among lithographic failure, scratches, dirt, particles, holes, and deformation. The target positioning information of the wafer image to be inspected is compared with the standard target positioning information corresponding to the defect-free wafer image, and the location and type of defects in the wafer image to be inspected are determined based on the comparison results. The denoising process for the wafer image to be inspected includes: using an adaptive accelerated nonlocal mean filtering algorithm to filter and denoise the wafer image to be inspected, and dynamically allocating search radii for different regions based on the periodic texture features and local region characteristics of the wafer image to be inspected in order to accelerate the filtering process. Specifically, the search radius for the edge region is configured to be 5 pixels, and the search radius for the background region is configured to be 1 pixel or not searched. The process of denoising and edge enhancement of the wafer image to be inspected includes: using an adaptive multi-scale gradient enhancement Canny edge detection algorithm to extract edges from the denoised wafer image to be inspected; using the maximum inter-class variance method to adaptively set the high and low thresholds for edge detection; and calculating the gradient weighted sum in the neighborhood of a 3x3 window in four directions (0°, 45°, 90°, and 135°) to perform gradient enhancement to distinguish real edges from noise, thereby obtaining the binary edge image. The deformation defect morphology is such that the target positioning information matches the standard target positioning information, but there is a difference in the width or height of the bounding box.

2. The wafer defect detection method based on YOLO-Label alignment according to claim 1, characterized in that, The target positioning information is compared with the standard target positioning information corresponding to the defect-free wafer image, including: Preset feature points of each target bounding box are extracted from the target positioning information of the wafer image to be inspected and the standard target positioning information of the defect-free wafer image, respectively. Calculate the distance matrix between the feature points of the wafer image to be inspected and the feature points of the defect-free wafer image; Based on a preset distance threshold, and according to the matching results of the distance matrix, it is determined whether there are missing or redundant defects in the wafer image to be detected.

3. The wafer defect detection method based on YOLO-Label alignment according to claim 2, characterized in that, The preset feature point is the coordinates of the top left corner vertex of the bounding box.

4. A wafer defect detection system based on YOLO-Label matching, comprising a processor, a memory, and a computer program / instructions stored in the memory, characterized in that, The processor is used to execute the computer program / instructions, and when the computer program / instructions are executed, the system implements the steps of the method as described in any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method as described in any one of claims 1 to 3.

Images