Test scene rapid switching method and system of BMS-HIL test system

Abstract

The invention relates to the technical field of BMS testing, and discloses a rapid test scene switching method and system for a BMS-HIL test system, and the method comprises the steps: obtaining a test instruction through an upper computer, recognizing a test sequence and test data which are in one-to-one correspondence, and generating a switching instruction in sequence; the control center responds to the instruction and deploys the data packet to the matrix switch array and the HIL signal source, so that the HIL signal source is electrically connected with the current BMS controller; when the current BMS is tested, a switching instruction of the next BMS is prepared in advance, and after the test is completed, the next BMS is automatically switched to be tested through the matrix switch; the test duration can be adjusted according to the number of interfaces, the model of the controller is verified, and multiple groups of signal sources are configured for adaptive test. The method greatly shortens the switching time consumption, improves the test efficiency and continuity, and guarantees the accuracy and safety of the test.

Description

Technical Field

[0001] This application relates to the technical field of BMS testing, and in particular to a method and system for rapid switching of test scenarios in a BMS-HIL testing system. Background Technology

[0002] The Battery Management System (BMS) is a core electronic control unit in new energy vehicles, energy storage equipment, and other fields. It is responsible for real-time monitoring of key parameters of the battery pack, such as voltage, current, and temperature, and performs functions such as battery state estimation, charge / discharge control, fault diagnosis, and protection. Its performance directly determines the safety, reliability, and lifespan of the battery system, and is one of the core technologies for ensuring the stable operation of new energy equipment, playing a vital role in promoting the high-quality development of the new energy industry. Battery Management System (BMS) Hardware-in-the-Loop (BIL) testing is a highly efficient verification technology. Its basic principle is to connect the physical BMS control center to a virtual simulation environment. Through a real-time simulation platform, it simulates the operating conditions of the battery system and the entire vehicle, outputs various sensor signals to the BMS, and collects the BMS's control commands for closed-loop verification. This testing method can replace traditional real-vehicle road tests and bench tests, significantly reducing testing costs and shortening the verification cycle. It also covers extreme operating conditions and fault scenarios, improving the comprehensiveness and safety of BMS performance testing. In existing technologies, BMS-HIL testing systems typically rely on manually changing hard-wired connections when switching between different BMS controller models or testing scenarios to meet different needs. For example, when switching between different types of sensor signal inputs, actuator output interfaces, power supply paths, or CAN / LIN communication interfaces, test personnel must manually plug and unplug terminals and adjust wiring harness connections, which is cumbersome and time-consuming, severely impacting testing efficiency and continuity. Summary of the Invention

[0003] To improve the testing efficiency of BMS-HIL testing, this application provides a method and system for quickly switching test scenarios in a BMS-HIL testing system.

[0004] Firstly, this application provides a method for rapidly switching test scenarios in a BMS-HIL test system, employing the following technical solution: A method for rapidly switching test scenarios in a BMS-HIL test system includes the following steps: The host computer obtains test instructions, identifies test sequences and test data from the test instructions, and the sequence elements in the test sequence correspond one-to-one with the data packets in the test data. The host computer extracts sequence elements in sequence according to the test sequence and performs the test. It extracts the corresponding data packets based on the sequence elements and generates a switching instruction, which is then sent to the control center. In response to a switching command, the control center retrieves the corresponding data packet from the host computer and deploys the data packet to the matrix switch array. The matrix switch has at least one input port and at least two output ports. The input port is connected to the HIL device signal source, one output port is connected to the first BMS controller, and the other output port is connected to the second BMS controller. The control center also deploys the data packet to the HIL device signal source. After the HIL device signal source and matrix switch array are deployed, the HIL device signal source and the first BMS controller are electrically connected, and the HIL device signal source and the second BMS controller are disconnected. During the HIL test of the first BMS controller, the host computer extracts the next sequence element and the corresponding next data packet. The next sequence element corresponds to the second BMS controller, and a switching instruction corresponding to the second BMS controller is generated. After the first BMS controller completes the test, the control center controls the matrix switch array to disconnect the signal sources of the first BMS controller and the HIL device, and sends the newly generated switching command to the control center. In response to the newly generated switching command, the control center obtains the corresponding data packet and deploys the next corresponding data packet to the matrix switch array and the HIL device signal source. The HIL device signal source and the second BMS controller are electrically connected to perform the HIL test of the second BMS controller. After the test is completed, the control center controls the matrix switch array to disconnect the signal sources of the second BMS controller and the HIL device.

[0005] By adopting the above technical solution, the host computer accurately identifies test commands and sequentially allocates test sequences and corresponding data packets. With the help of the control center, the data packets are deployed to the matrix switch array and HIL device signal source. The matrix switch array enables automatic switching between the HIL device signal source and different BMS controllers. Furthermore, during the current BMS controller test, the data packets and switching commands corresponding to the next test sequence are prepared in advance. This effectively replaces the scenario switching method in the existing technology that relies on manual plugging and unplugging of terminals and adjusting wiring harness connections. This not only significantly reduces the cumbersome and time-consuming operation during scenario switching and ensures the continuity of testing, but also reduces the probability of errors caused by manual operation, thereby significantly improving the overall efficiency of BMS-HIL testing. At the same time, it can smoothly complete the orderly testing of multiple BMS controllers.

[0006] Furthermore, the method includes the following steps: When the current BMS controller enters the test, obtain the number of interfaces of the next BMS controller; The operation duration is calculated based on the interface data and the set interface operation time value. The current test duration of the current BMS controller for HIL testing is adjusted according to the positive correlation of the operation duration.

[0007] By adopting the above technical solution, we can flexibly adapt to the interface differences of different BMS controllers, reserve the adaptation time required for the next test scenario switch in advance, and avoid the test gap period that occurs after the current controller test ends due to waiting for the deployment operation of the next controller interface. This not only makes the test process more closely and smoothly connected and reduces the overall test process bottleneck, but also allows for reasonable allocation of the test duration of a single controller according to the actual switch preparation needs, avoiding wasted time or insufficient preparation, and further ensuring the continuity of testing.

[0008] Furthermore, the method includes the following steps: Get the number of first interfaces of the first BMS controller, and get the number of second interfaces of the second BMS controller; The first operation duration is calculated based on the first interface data and the set interface operation time value, and the second operation duration is calculated based on the second interface data and the interface operation time value. The first test duration of the HIL test of the first BMS controller is adjusted according to the positive correlation of the second operation duration, and the second test duration of the HIL test of the second BMS controller is adjusted according to the positive correlation of the first operation duration.

[0009] By adopting the above technical solution, a precise bidirectional adaptation between the testing and switching preparation of the two BMS controllers is achieved. This ensures that when the first BMS controller is tested, there is sufficient time to complete the switching preparation work related to the interface with the second BMS controller, and also allows the second BMS controller to adapt to the preparation time required for the subsequent switching of the first BMS controller.

[0010] Furthermore, before the HIL device signal source and the second BMS controller are electrically connected, the following steps are also included: The control center is electrically connected to the second BMS controller via a matrix switch array, and the control center obtains the model data of the second BMS controller; The model data is compared with the model data recorded in the data packet. If the comparison result is inconsistent, the control center issues a controller abnormality alarm.

[0011] By adopting the above technical solution, the problem of mismatch between the second BMS controller and the data packet model corresponding to the test to be performed can be accurately identified in advance. This avoids the distortion of test data and invalid test results due to model mismatch, or potential damage to the BMS controller and HIL equipment caused by mismatch test. At the same time, timely alarms can enable staff to quickly deal with model abnormality issues, reducing the time and resource waste caused by rework due to subsequent test errors.

[0012] Furthermore, the method includes the following steps: Based on the controller's abnormal alarm, the controller sends a controller query request to the host computer and sends the model data to the host computer; the host computer queries the model data from the preset model database according to the controller query request; If model data is found, record the alarm information and clear the controller's abnormal alarm. Generate a sequence element and corresponding data packet based on the model data. Insert the sequence element into the test sequence as the next sequence element, and insert the data packet into the test data as the next data packet. The host computer updates the switching instruction based on the next sequence element and the next data packet, and replaces the previous switching instruction responded to by the controller center with the updated switching instruction.

[0013] By adopting the above technical solution, automated adaptation and process repair after an alarm are achieved, eliminating the need for manual intervention to check the model and rebuild the test sequence. This not only significantly shortens the time spent on anomaly handling and avoids long-term interruptions in the test process due to alarms, but also ensures that subsequent tests proceed based on the correct instructions of the adapted controller model, guaranteeing the continuity of the test sequence.

[0014] Furthermore, the method includes the following steps: The matrix switch has at least two input ports and at least two output ports; HIL equipment signal sources are set up with at least two groups, including at least a first group of signal sources and a second group of signal sources; When the first BMS controller performs HIL testing, the matrix switch array controls the first group of signal sources to be electrically connected to the first BMS controller; when the second BMS controller performs HIL testing, the second group of signal sources is electrically connected to the second BMS controller.

[0015] By adopting the above technical solution, the problems of frequent parameter adjustment and switching delays in single-group signal source reuse scenarios are avoided, and the risk of signal interference caused by the sharing of signal sources between different BMS controller tests is reduced. At the same time, each BMS controller corresponds to a dedicated signal source, and the parameters can be deployed in advance according to its test requirements. There is no need to temporarily adjust the signal source parameters when switching tests. This not only reduces the probability of parameter configuration errors and ensures the accuracy of test data, but also allows the preparation of another set of signal sources to be completed simultaneously during the current BMS controller test, which greatly shortens the waiting time for test scenario switching and further enhances the continuity of the test process.

[0016] Furthermore, the method includes the following steps: The matrix switch array controls the first group of signal sources to be electrically connected to the first BMS controller; when the first BMS controller is performing HIL testing, the control center connects to the second group of signal sources through the matrix switch array, deploys the second group of signal sources, and then disconnects the electrical connection with the second group of signal sources. The control center then connects to the second BMS controller through the matrix switch array to compare the second BMS controller. If the comparison is successful, wait for the first end signal of the first BMS controller test to end. Based on the first received signal, the control center controls the second group of signal sources of the control matrix switch array to be electrically connected to the second BMS controller.

[0017] By adopting the above technical solution, the gap period of starting the next test preparation work after the first BMS test is completed is effectively avoided, and the overall time consumption of scene switching is greatly reduced. At the same time, the comparison and verification of the second BMS controller in advance can help to identify problems such as model mismatch in advance, avoid test interruption or invalid data due to controller abnormality after switching, and ensure test accuracy.

[0018] Furthermore, the method includes the following steps: The switching speed of the matrix switch array is adjusted in a negative correlation with the number of signal sources of the HIL device.

[0019] By adopting the above technical solutions, the switching rhythm of the matrix switch can be precisely matched with the operational load brought about by the number of signal sources: when there are many signal sources, the switching operation needs to handle more signal connection and port matching work simultaneously. Appropriately slowing down the switching speed can avoid problems such as unstable signal transmission and untimely parameter configuration caused by excessively fast operation, and ensure the accuracy of signal connection; when there are few signal sources, the switching operation load is reduced, and speeding up the switching speed can reduce unnecessary waiting time and improve scene switching efficiency.

[0020] Secondly, this application provides a rapid test scenario switching system for a BMS-HIL testing system, which adopts the following technical solution: A rapid test scenario switching system for a BMS-HIL test system includes a processor, wherein the processor executes the steps of the rapid test scenario switching method for a BMS-HIL test system as described in any one of the above claims. Attached Figure Description

[0021] Figure 1 This is a step-by-step diagram of a method for quickly switching test scenarios in a BMS-HIL testing system.

[0022] Figure 2 This is a schematic diagram of the BMS controller's fast switching principle.

[0023] Figure 3This is a BMS-HIL test system architecture diagram that includes relay matrix and host computer scenario management functions. Detailed Implementation

[0024] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0025] This application discloses a method for rapid switching of test scenarios in a BMS-HIL test system, applicable to the batch R&D testing of multiple BMS controllers (such as BMS-01 for compact electric vehicles, BMS-02 for mid-size SUVs, and BMS-17 for pure electric microcars) in the field of new energy vehicles. It is particularly effective for composite scenarios of "normal operating condition testing + fault simulation testing", solving the problems of long switching time, low efficiency and easy error caused by manual plugging and unplugging of wiring in the prior art.

[0026] The hardware system configuration for this embodiment is as follows, ensuring that the method is reproducible: Host computer: It adopts an industrial-grade Core i7-12700K processor computer, equipped with Windows 10 Professional Edition operating system and self-developed BMS-HIL test management software (supports CAPL format scenario configuration, model library management, and real-time data monitoring), and gigabit Ethernet communication interface (latency ≤10ms). Control Center: Employs an FPGA chip (model XilinxArtix-7XC7A35T), integrating an SPI communication interface (transmission rate 10Mbps), a CAN bus interface (compliant with ISO11898-2 standard), and a GPIO interface (for controlling matrix switches and audible and visual alarm modules). Matrix switch array: The OMRONG6K-2F-Y type relay matrix is ​​selected, which supports 16 inputs and 32 outputs. The single relay response delay is ≤10ms. It supports the on / off control of analog (0-400V / 0-500A), digital (0-5V) and CAN / LIN bus signals. HIL device signal sources include: a battery simulator (output voltage 0-400V, accuracy ±0.05%; output current 0-500A, accuracy ±0.1%), a load simulator (current range 0-500A), a temperature / pressure sensor simulator (output 4-20mA current signal, simulating temperature -40℃~85℃ and pressure 0-1MPa), and a CAN / LIN bus signal generator (CAN baud rate 125kbps-1Mbps, LIN baud rate 9.6kbps-19.2kbps). BMS controller: The test objects are BMS-01 (8 analog interfaces, 6 digital interfaces, 2 CAN interfaces), BMS-02 (12 analog interfaces, 8 digital interfaces, 2 CAN interfaces + 1 LIN interface), BMS-17 (6 analog interfaces, 4 digital interfaces, 1 CAN interface), etc., all of which support EEPROM storage of model identifiers (format "BMS-XX-VX.X").

[0027] This embodiment takes "BMS-01→BMS-02 continuous test" as an example, referring to... Figures 1-3 The basic switchover process is explained in detail, with the specific steps as follows: Step 1: The host computer acquires and parses the test commands. Testers use the visual interface of the host computer test management software to select the preset "BMS-01 and BMS-02 continuous test task" and configure the test parameters: Test type: Routine charge-discharge cycle test (voltage 280-380V for BMS-01, 300-400V for BMS-02) + "Individual cell voltage undervoltage" fault simulation test (threshold 2.5V for BMS-01, 2.6V for BMS-02). Single controller benchmark test duration: 25 minutes; Data sampling frequency: 100Hz.

[0028] After receiving the above test instructions, the host computer extracts the test sequence and test data through its built-in "instruction parsing module": Test sequence: contains 2 sequence elements, namely "S1 (BMS-01 test)" and "S2 (BMS-02 test)", and each sequence element is bound to a BMS controller; Test data: Contains two data packets. "P1 (bound to S1)" records the test parameters of BMS-01 (battery simulator voltage 280-380V, current 0-300A, temperature simulation -10℃~55℃, CAN baud rate 500kbps, undervoltage fault triggering conditions); "P2 (bound to S2)" records the test parameters of BMS-02 (battery simulator voltage 300-400V, current 0-400A, temperature simulation -20℃~65℃, CAN baud rate 1Mbps + LIN baud rate 19.2kbps, undervoltage fault triggering conditions). Mapping relationship: The sequence elements and data packets are matched one-to-one through unique identifiers (such as S1 corresponding to ID "Test-001" and P1 corresponding to ID "Data-001").

[0029] Step 2: The host computer generates a switching command and sends it to the control center. The host computer extracts the first sequence element S1 according to the test sequence order, calls the data packet P1 bound to it, and generates a switching instruction C1 (identified as "Cmd-001") through the "instruction generation module". The instruction contains two types of core information: Matrix switch on / off control parameters: Define the conduction path as follows: "Battery simulator output → matrix switch input port 1 → output port 1 (BMS-01 power interface)", "Temperature sensor simulator → matrix switch input port 8 → output port 1 (BMS-01 signal acquisition interface)", "CAN signal generator → matrix switch input port 12 → output port 1 (BMS-01 CAN interface)", and keep the other ports disconnected. HIL device signal source configuration parameters: specify the battery simulator output voltage range of 280-380V, current ramp-up rate of 5A / s, temperature simulator output of 4-20mA corresponding to -10℃~55℃, and CAN signal generator baud rate of 500kbps.

[0030] The host computer sends the switching command C1 and the complete data packet P1 (in XML format, including parameter identifier, value range, and check bit) to the control center via gigabit Ethernet. The actual communication delay is 8ms, which meets the real-time requirements.

[0031] Step 3: The control center deploys the data package and configures the hardware devices. Reference Figure 2 After receiving the switching command C1, the control center (FPGA) initiates the "dual-path parallel deployment logic": Matrix switch array deployment: The on / off control parameters in P1 are written into the control register (address 0x00-0x0F) of the matrix switch via the SPI communication interface (rate 10Mbps) to configure the conduction relationship of the input-output ports. The deployment time is ≤300ms. HIL device signal source deployment: The signal source configuration parameters in P1 are sent to each HIL module via CAN bus (ISO11898-2). After receiving the command, the battery simulator adjusts the output voltage to 280V standby and the temperature simulator is calibrated to 25℃ (initial value). The deployment time is ≤2s.

[0032] During deployment, the control center receives "configuration complete feedback frames" from each hardware module in real time. For example, the battery simulator feedback frame ID 0x680, with data segment 0x01 indicating that the configuration has taken effect. When all modules report "configuration complete", the hardware deployment is considered complete.

[0033] Step 4: Establish the connection between the HIL device and the first BMS controller and start the test. After the control center confirms that the hardware deployment is complete, it sends a "path connection command" (GPIO outputs a high level to the matrix switch control pin) to control the matrix switch array to close the preset connection path in step 2, so as to achieve a stable electrical connection between the HIL device signal source and the power interface, signal acquisition interface, and CAN communication interface of the first BMS controller (BMS-01), with a connection time of ≤500ms; at the same time, the matrix switch remains disconnected from all ports of the second BMS controller (BMS-02) (output port 2 is all low level) to avoid cross signal interference.

[0034] The control center sends a "test ready signal" (CAN frame ID 0x600, data segment 0x01) to the host computer. After receiving the signal, the host computer immediately sends a "start test command". The BMS-01 officially enters the HIL test: the HIL signal source outputs simulated operating condition signals according to the P1 parameter. After receiving the signal, the BMS-01 feeds back charging and discharging control commands (such as charging cut-off current 5A). The host computer collects the feedback data of the BMS-01 in real time (sampling frequency 100Hz) and stores it in the local database.

[0035] Step 5: Prepare the switching instructions for the second BMS controller in advance. During the HIL test performed by BMS-01 (the host computer monitoring showed that the test had been running for 8 minutes and the data was normal), the host computer initiated a "multi-threaded processing mechanism": Main thread: Continuously monitor the test progress of BMS-01 (17 minutes remaining), real-time data (such as individual unit voltage deviation ≤0.02V) and equipment operating status (no overload / overheating) to ensure the test proceeds normally; Sub-thread: Synchronously extract the next sequence element S2 in the test sequence, call the bound data packet P2, and generate the switching instruction C2 (identified as "Cmd-002") according to the logic of step 2. The instruction includes the conduction path of the matrix switch "input port 1 → output port 2 (BMS-02 power interface)" and "input port 9 → output port 2 (BMS-02LIN interface)", as well as the parameters of the HIL signal source adapted to BMS-02 (such as the battery simulator voltage 300V standby).

[0036] After the switching instruction C2 is generated, it is temporarily stored in the instruction buffer area of ​​the control center (capacity 32KB, supports multiple instructions queuing). The buffer area uses CRC check to ensure instruction integrity and avoid transmission errors.

[0037] Step 6: Automatically switch to the second BMS test after the first BMS test is completed. Reference Figure 2When the BMS-01 test reaches the preset baseline duration of 25 minutes, and the host computer confirms that both the "charge-discharge cycle + fault simulation" are completed, the host computer immediately sends a "switch trigger command" (CAN frame ID 0x601, data segment 0x01) to the control center: 1. The control center first sends a "path disconnect command" (GPIO outputs a low level to the control pin of matrix switch input port 1 to output port 1) to disconnect all connections between the HIL device signal source and BMS-01. The disconnection time is ≤800ms. 2. The control center retrieves the switching instruction C2 from the buffer, responds to the instruction and obtains the data packet P2 from the host computer through the SPI interface, and deploys the configuration parameters in P2 to the matrix switch array (updating the conduction path of output port 2) and the HIL device signal source (adjusting the battery simulator to 300V and starting the LIN signal generator). The deployment time is ≤2.5s. 3. After deployment, the control center controls the matrix switch array to close the corresponding path between the HIL device signal source and BMS-02 (input port 1 → output port 2, input port 9 → output port 2), with a conduction time ≤500ms; 4. The control center sends a "switch ready signal" to the host computer, and the host computer sends a "start test command", and BMS-02 enters the HIL test.

[0038] After the BMS-02 test is completed (25 minutes), the control center controls the matrix switch array to disconnect its connection with the HIL device signal source again. The entire "BMS-01→BMS-02" test process ends. The total switching time (from BMS-01 disconnection to BMS-02 conduction) was measured to be 4.2 seconds, which is 214 times more efficient than the traditional manual switching (which takes about 15 minutes).

[0039] To further optimize the switching method, the following steps are also included: 3.1 Implementation of Dynamic Adjustment of Test Duration (Adapting to Interface Differences) This embodiment uses the "BMS-03 (current controller) → BMS-04 (next controller)" test as an example to illustrate the test duration adjustment mechanism. The specific steps are as follows: Step 3.1.1 Obtain the number of interfaces between the current and next BMS controller. Before testing, a "BMS Model - Number of Interfaces" mapping table is preset in the "BMS Parameter Library" module of the host computer test management software. The key configurations are as follows: BMS-03 (current controller): 8 analog interfaces (voltage / temperature acquisition), 6 digital interfaces (status feedback), 2 CAN communication interfaces, for a total of 16 interfaces; BMS-04 (next controller): 12 analog interfaces, 8 digital interfaces, 3 CAN communication interfaces, 1 LIN communication interface, for a total of 24 interfaces.

[0040] When the system executes the HIL test start command of BMS-03, the host computer automatically extracts the number of interfaces of BMS-04 (24) from the mapping table through the "interface parameter call module" and synchronizes the data to the parameter buffer area of ​​the control center (address 0x10-0x1F) through SPI communication.

[0041] Step 3.1.2 Calculate the interface operation time of the next BMS controller. In the host computer software, a "time value for interface operation" is preset: Based on the characteristics of the OMRONG6K-2F-Y matrix switch selected in this embodiment, and combined with 100 actual test data, the average deployment time for a single interface is set to 0.2 seconds (including 0.05 seconds for relay switching, 0.1 seconds for signal calibration, and 0.05 seconds for path detection). This value is stored in the "System Parameter Configuration" module of the host computer and can be dynamically adjusted according to hardware performance (this embodiment keeps it fixed).

[0042] The host computer calls the "duration calculation algorithm" and calculates the operation duration according to the formula "operation duration = number of interfaces × time consumption per interface": Operation duration = 24 × 0.2 = 4.8 seconds, the calculation result is accurate to 0.1 seconds and stored in the "duration adjustment buffer" of the host computer.

[0043] Step 3.1.3 Adjust the test duration of the current BMS controller in a positive correlation. 1. Determine the benchmark test duration: Based on the test requirements of BMS-03 (routine charge and discharge cycle test), the preset benchmark duration is 20 minutes (1200 seconds). This duration can cover the core function verification of BMS-03 (3 charge and discharge cycles + 2 fault simulations). 2. Calculate the adjustment increment: Based on the "positive correlation adjustment rule of operation time", set the adjustment coefficient to 1.2 (to ensure sufficient preparation time and avoid gaps caused by insufficient preparation), and calculate according to the formula "adjustment increment = operation time × adjustment coefficient": Adjustment increment = 4.8 × 1.2 ≈ 5.8 seconds, rounded to 6 seconds; 3. Update test duration: The host computer automatically adjusts the test duration of BMS-03 to "baseline duration + adjustment increment = 1200 + 6 = 1206 seconds (20 minutes and 06 seconds)" and sends the adjusted duration parameter to the control center via the CAN bus. The control center synchronously updates the test timing control logic of the HIL device (such as adjusting the total number of data samplings from 120,000 to 120,600).

[0044] Step 3.1.4 Perform post-adjustment testing and connection verification. BMS-03 performs HIL testing for a test duration of 1206 seconds, and the host computer monitors the test progress in real time. When there are 6 seconds left in the test, the control center starts the interface deployment preparation of BMS-04 based on the preset operation duration (4.8 seconds) (such as the pre-switching of the relays on the matrix switch output port 2 and the pre-configuration of HIL signal source parameters).

[0045] After BMS-03 completed 1206 seconds of testing, the interface deployment of BMS-04 was completed synchronously (taking 4.8 seconds). The system immediately triggered a switching command, seamlessly connecting to the testing of BMS-04 without any gap. The actual switching interval was ≤0.2 seconds, solving the lag problem of "waiting for interface deployment after the test" in the traditional method.

[0046] 3.2 Implementation of BMS Model Pre-verification and Anomaly Handling This embodiment uses the mismatch scenario of "BMS-08 (expected) → BMS-09 (actual access)" as an example to illustrate the model verification and anomaly handling mechanism. The specific steps are as follows: Step 3.2.1 Model pre-verification before HIL testing 1. Establish a dedicated verification path: Before testing, configure a "dedicated model verification path" in the host computer software: The model detection signal output terminal (GPIO pin 10) of the control center (FPGA) is connected through matrix switch input port 10, and the model data feedback terminal (EEPROM read pin) of BMS-09 is connected through matrix switch output port 15, forming an independent path of "control center → matrix switch input 10 → output 15 → BMS-09". This path is completely isolated from the test signal path to avoid interference. 2. Triggering Path On-line: When the system completes the BMS-07 test and enters the BMS-08 test preparation stage, the host computer sends a "Model Verification Start Command" (CAN frame ID 0x602, data segment 0x01) to the control center. After the control center responds, it controls the matrix switch input 10 and output 15 to close. The on-line time is ≤300ms. 3. Obtaining BMS model data: The control center sends a model data read request frame (ID0x610, data segment 0x01) to BMS-09 via the CAN bus (speed 500kbps). After receiving the frame, BMS-09 retrieves the model identifier "BMS-09-V1.0" from the EEPROM and encapsulates it into a feedback frame (ID0x690, data segment is the byte stream corresponding to the ASCII code "BMS-09-V1.0" 0x420x4D0x530x2D0x300x390x2D0x560x310x2E0x30), and transmits it back to the control center through a dedicated channel. The data transmission time is ≤100ms.

[0047] Step 3.2.2 Model Data Comparison and Abnormal Alarm Triggering 1. Retrieve expected model data: The control center obtains the corresponding BMS-08 test data packet from the host computer via the SPI interface and extracts the "expected model field" (content is "BMS-08-V2.1"). 2. Execute comparison logic: The control center has a built-in string comparison algorithm to compare the actual model "BMS-09-V1.0" with the expected model "BMS-08-V2.1". It finds that the characters "09" and "08" and "V1.0" and "V2.1" are inconsistent, and determines that "the comparison result is inconsistent". 3. Triggering an abnormal alarm: The control center activates a dual-channel alarm system ("hardware + software"): Hardware alarm: The control center controls the external sound and light alarm module (buzzer + red LED) through the GPIO interface. The buzzer sounds continuously at a frequency of 1kHz, and the LED flashes at a frequency of 1 time / second. Software alarm: The control center sends a "model mismatch alarm command" (CAN frame ID 0x620, data segment 0x01) to the host computer. The host computer software pops up an alarm window, displaying the mismatch details (actual model "BMS-09-V1.0", expected model "BMS-08-V2.1", mismatch field location), and automatically records the alarm time (accurate to milliseconds) and device number (SN code of BMS-09 "BMS09202405001") to the test log.

[0048] Step 3.2.3 Automated Adaptation and Process Repair After Alarm 1. Sending query request and model data: Based on the alarm signal, the control center sends a controller query request (CAN frame ID 0x621, data segment 0x01) to the host computer, and simultaneously sends the actual model data of BMS-09 "BMS-09-V1.0"; 2. Model Query: After receiving the data, the host computer queries "BMS-09-V1.0" from the preset "BMS Model Library" (which stores parameters of 20+ mainstream BMS models), confirms the existence of the model, and extracts its core parameters (10 analog interfaces, 7 digital interfaces, 2 CAN interfaces, and battery simulator voltage 290-390V). 3. Recording and clearing alarms: The host computer automatically writes the alarm information to the test log (marked "Model mismatch - adapted") and sends an "alarm clearing command" (CAN frame ID 0x622, data segment 0x01). After receiving the command, the control center turns off the audible and visual alarm module. 4. Generate adaptation sequence and data packet: The host computer generates a new sequence element "S3 (BMS-09 test)" and the corresponding data packet "P3" (containing HIL signal source configuration and matrix switch path parameters) based on the parameters of BMS-09. 5. Update test sequence and switching command: The host computer inserts S3 into the original test sequence (the original sequence "S1→S2" is updated to "S1→S3→S2"), inserts P3 into the test data list, and generates a new switching command "C3" based on S3 and P3. The new command is sent to the control center via Ethernet to replace the original switching command "C2" (the command adapted to BMS-08). The command update takes ≤500ms.

[0049] After the repair is completed, the system can continue to advance the BMS-09 test based on the new instructions without manual intervention. The total time for anomaly handling is ≤3 seconds, which is 600 times more efficient than traditional manual troubleshooting (about 30 minutes).

[0050] 3.3 Implementation of Adaptation for Multiple HIL Signal Sources This embodiment uses the example of "two sets of HIL signal sources being adapted to BMS-13 and BMS-14 respectively" to illustrate the multi-signal source adaptation mechanism. The specific steps are as follows: Step 3.3.1 Hardware Deployment of Matrix Switch and HIL Signal Source 1. Matrix switch port configuration: Connect the two input ports (Input1, Input2) of the matrix switch to the signal aggregation terminals of the two HIL signal sources respectively, and connect the two output ports (Output1, Output2) to the signal acquisition interfaces of BMS-13 and BMS-14 respectively. Input1 → First HIL signal source (compatible with BMS-13); Input2 → Second HIL signal source (compatible with BMS-14); Output1 → Signal acquisition interface of BMS-13 (including analog, digital and CAN interfaces). Output2 → Signal acquisition interface of BMS-14 (including analog, digital and CAN+LIN interfaces). 2. HIL Signal Source Group Configuration: Two groups of signal sources are independently powered and controlled, with the following parameter configurations: The first set of signal sources (compatible with BMS-13): battery simulator (voltage 280-380V, current 0-300A), temperature simulator (-10℃~55℃), CAN signal generator (500kbps). The second set of signal sources (compatible with BMS-14): battery simulator (voltage 300-400V, current 0-400A), temperature simulator (-20℃~65℃), CAN+LIN signal generator (CAN 1Mbps, LIN 19.2kbps).

[0051] Step 3.3.2 Signal path control during the first BMS test 1. Issuing the activation command: When the system starts the test task of BMS-13, the host computer generates a switching command (Cmd-010) for "Input1→Output1" and sends it to the control center; 2. Matrix switch execution control: The control center responds to the command, controls the relays of matrix switch Input1 and Output1 to close, and the relays of Input2 and Output2 to open, establishing the electrical connection between the first set of signal sources and BMS-13, with a conduction time ≤500ms; 3. Test execution: The first group of signal sources outputs test signals according to preset parameters (such as simulating charging conditions: voltage rises from 280V to 380V, current 200A). After receiving the signals, the BMS-13 feeds back control commands, and the host computer collects data in real time. There is no signal interference during the test (voltage fluctuation ≤0.02V).

[0052] Step 3.3.3 Signal path switching and parallel preparation during the second BMS test 1. The second group of signal sources was deployed in advance: In the 10th minute of the BMS-13 test, the host computer sub-thread sent a configuration command to the second group of signal sources, adjusting its battery simulator to 300V standby and calibrating its temperature simulator to 25℃. The deployment time was ≤2s. 2. Switch to the second BMS test: After the BMS-13 test is completed, the control center disconnects the connection between Input1 and Output1 (time ≤ 800ms), and at the same time closes the relays of Input2 and Output2 (time ≤ 500ms) to establish the electrical connection between the second set of signal sources and BMS-14; 3. Perform the test: The second group of signal sources outputs signals according to the adapted parameters, and the BMS-14 starts the test. At the same time, the parameters of the first group of signal sources are reset synchronously (such as the battery simulator is restored to 280V) to prepare for the next round of BMS-13 testing.

[0053] In this embodiment, the dedicated adaptation of the two signal sources avoids the parameter adjustment delay of single-source multiplexing (the adjustment of traditional single-source multiplexing takes about 5 seconds), the total switching time is ≤1.3 seconds, and the signal interference rate is reduced from 15% of the traditional multiplexing scheme to 0%.

[0054] 3.4 Implementation of Matrix Switch Switching Speed ​​Adjustment This embodiment uses a scenario with "1 group, 2 groups, and 4 groups of HIL signal sources" as an example to illustrate the switching speed adjustment mechanism. The specific steps are as follows: Step 3.4.1 Preset switching speed reference parameters and adjustment algorithm 1. Baseline parameter configuration: Preset in the host computer software: Matrix switch reference switching speed: 50ms / channel (reference time for single-channel relay "click-on / click-off", based on measured data from OMRONG6K-2F-Y); Negative correlation adjustment coefficient: 1.4 (for every additional group of signal sources, the switching workload increases by approximately 30%, the optimal coefficient verified through 100 tests). 2. Adjustment formula: Actual switching speed = reference switching speed × (adjustment coefficient)^(number of HIL signal sources - 1). This formula is embedded in the "speed adjustment algorithm module" of the host computer.

[0055] Step 3.4.2 Identify the number of signal sources in the current HIL device. 1. Quantity reporting mechanism: Each HIL signal source has a built-in device identification module (stores the group number). Before the test starts, the control center sends a "quantity query command" (ID0x630, data segment 0x01) through the CAN bus, and each group of signal sources returns the group number (such as 1, 2, 3, 4). 2. Quantity statistics: The control center summarizes the group number information, calculates the current number of signal sources (e.g., 2 groups for scenario 1, 4 groups for scenario 2), and uploads the data to the host computer.

[0056] Step 3.4.3 Calculate and issue the switching speed adjustment command 1. Scenario 1 (2 sets of signal sources): Calculate the actual switching speed: 50 × 1.4^(2-1) = 70 ms / channel; The host computer generates an adjustment command (target speed 70ms / channel, effective ports 1-8). After receiving the command, the control center writes the parameters into the matrix switch control register and configures the action delay of the relay drive circuit (35ms delay before activation and 35ms delay before deactivation). 2. Scenario 2 (4 signal sources): Calculate the actual switching speed: 50 × 1.4^(4-1) = 50 × 2.744 = 137.2 ms / channel; Command issued: The host computer generates adjustment commands (target speed 137.2ms / channel, effective ports 1-16), and the control center configures relay action delays (68.6ms delay before activation and 68.6ms delay before deactivation).

[0057] Step 3.4.4 Switching effect verification Scenario 1 (Group 2): The matrix switch performs 8-channel port switching at 70ms / channel, with a total time of 560ms. The signal transmission is stable (voltage fluctuation ≤0.02V) and there is no parameter configuration delay. Scenario 2 (4 groups): The matrix switch performs 16-channel port switching at 137.2ms / channel, with a total time of ≈2195ms. Compared with the traditional fixed speed (50ms / channel), the signal configuration error rate is reduced from 18.75% to 0%, which solves the problem of "instability caused by fast switching" in multi-signal source scenarios.

[0058] The method in this embodiment has good scalability: when a third BMS controller (such as BMS-20) is added, it is only necessary to expand the output ports of the matrix switch (from 32 channels to 64 channels), add a third set of HIL signal sources, and add the parameters of BMS-20 to the host computer model library. No modification to the core logic is required, resulting in low adaptation cost and short cycle. This application also discloses a rapid test scenario switching system for a BMS-HIL test system, including a processor, wherein the processor executes the steps of the rapid test scenario switching method for a BMS-HIL test system as described in any of the above embodiments.

Claims

1. A method for rapid switching of test scenarios in a BMS-HIL test system, characterized in that, Includes the following steps: The host computer obtains test instructions, identifies test sequences and test data from the test instructions, and the sequence elements in the test sequence correspond one-to-one with the data packets in the test data. The host computer extracts sequence elements in sequence according to the test sequence and performs the test. It extracts the corresponding data packets based on the sequence elements and generates a switching instruction, which is then sent to the control center. In response to a switching command, the control center retrieves the corresponding data packet from the host computer and deploys the data packet to the matrix switch array. The matrix switch has at least one input port and at least two output ports. The input port is connected to the HIL device signal source, one output port is connected to the first BMS controller, and the other output port is connected to the second BMS controller. The control center also deploys the data packet to the HIL device signal source. After the HIL device signal source and matrix switch array are deployed, the HIL device signal source and the first BMS controller are electrically connected, and the HIL device signal source and the second BMS controller are disconnected. During the HIL test of the first BMS controller, the host computer extracts the next sequence element and the corresponding next data packet. The next sequence element corresponds to the second BMS controller, and a switching instruction corresponding to the second BMS controller is generated. After the first BMS controller completes the test, the control center controls the matrix switch array to disconnect the signal sources of the first BMS controller and the HIL device, and sends the newly generated switching command to the control center. In response to the newly generated switching command, the control center obtains the corresponding data packet and deploys the next corresponding data packet to the matrix switch array and the HIL device signal source. The HIL device signal source and the second BMS controller are electrically connected to perform the HIL test of the second BMS controller. After the test is completed, the control center controls the matrix switch array to disconnect the signal sources of the second BMS controller and the HIL device.

2. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 1, characterized in that, The method includes the following steps: When the current BMS controller enters the test, obtain the number of interfaces of the next BMS controller; The operation duration is calculated based on the interface data and the set interface operation time value. The current test duration of the current BMS controller for HIL testing is adjusted according to the positive correlation of the operation duration.

3. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 1, characterized in that, The method includes the following steps: Get the number of first interfaces of the first BMS controller, and get the number of second interfaces of the second BMS controller; The first operation duration is calculated based on the first interface data and the set interface operation time value, and the second operation duration is calculated based on the second interface data and the interface operation time value. The first test duration of the HIL test for the first BMS controller is adjusted in a positive correlation with the second operation duration, and the second test duration of the HIL test for the second BMS controller is adjusted in a positive correlation with the first operation duration.

4. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 1, characterized in that, Before the HIL device signal source and the second BMS controller are electrically connected, the following steps are also included: The control center is electrically connected to the second BMS controller via a matrix switch array, and the control center obtains the model data of the second BMS controller; The model data is compared with the model data recorded in the data packet. If the comparison result is inconsistent, the control center issues a controller abnormality alarm.

5. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 4, characterized in that, The method includes the following steps: Based on the controller's abnormal alarm, the controller sends a controller query request to the host computer and sends the model data to the host computer; the host computer queries the model data from the preset model database according to the controller query request; If model data is found, record the alarm information and clear the controller's abnormal alarm. Generate a sequence element and corresponding data packet based on the model data. Insert the sequence element into the test sequence as the next sequence element, and insert the data packet into the test data as the next data packet. The host computer updates the switching instruction based on the next sequence element and the next data packet, and replaces the previous switching instruction responded to by the controller center with the updated switching instruction.

6. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 1, characterized in that, The method includes the following steps: The matrix switch has at least two input ports and at least two output ports; HIL equipment signal sources are set up with at least two groups, including at least a first group of signal sources and a second group of signal sources; When the first BMS controller performs HIL testing, the matrix switch array controls the first group of signal sources to be electrically connected to the first BMS controller. When the second BMS controller performs HIL testing, the second set of signal sources is electrically connected to the second BMS controller.

7. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 6, characterized in that, The method includes the following steps: The matrix switch array controls the first group of signal sources to be electrically connected to the first BMS controller; when the first BMS controller is performing HIL testing, the control center connects to the second group of signal sources through the matrix switch array, deploys the second group of signal sources, and then disconnects the electrical connection with the second group of signal sources. The control center then connects to the second BMS controller through the matrix switch array to compare the second BMS controller. If the comparison is successful, wait for the first end signal of the first BMS controller test to end. Based on the first received signal, the control center controls the second group of signal sources of the control matrix switch array to be electrically connected to the second BMS controller.

8. The method for rapid switching of test scenarios in the BMS-HIL test system according to claim 6, characterized in that, The method includes the following steps: The switching speed of the matrix switch array is adjusted in a negative correlation with the number of signal sources of the HIL device.

9. A rapid test scenario switching system for a BMS-HIL test system, characterized in that, The system includes a processor that performs the steps of the rapid test scenario switching method for the BMS-HIL test system as described in any one of claims 1-8.

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