Eye pattern generation method based on channel simulation, storage medium and electronic equipment

Abstract

The invention discloses an eye pattern generation method based on channel simulation, a storage medium and electronic equipment, and the method comprises the steps: carrying out the channel simulation according to a target channel parameter, a signal source parameter and an initial code pattern sequence, and generating jitter-free initial eye pattern data; obtaining a deterministic jitter parameter and a random jitter parameter, and generating a deterministic jitter time sequence based on the obtained deterministic jitter parameter and the initial code pattern sequence; generating a random jitter time sequence based on the obtained random jitter parameter; synthesizing the deterministic jitter time sequence and the random jitter time sequence to generate a total jitter time sequence offset sequence; and modulating time sequence information in the initial eye pattern data by using the total jitter time sequence offset sequence to generate a target eye pattern. Simulation of deterministic jitter and random jitter is added in the channel simulation process, and the consistency of the simulation result and the signal characteristic of a real communication scene is greatly improved.

Description

Technical Field

[0001] This application relates to the field of signal simulation technology, and in particular to an eye diagram generation method, storage medium, and electronic device based on channel simulation. Background Technology

[0002] In the field of high-speed serial communication, channel simulation, as a key means of evaluating channel transmission performance, is widely used in the design and verification stages of products such as chips, circuit boards, and communication modules. Eye diagrams, as an output of channel simulation, can intuitively reflect the amplitude distortion and timing deviations of signals after transmission through the channel. They are an important basis for judging whether signal integrity meets communication standards used for connecting peripherals, such as PCIe, Universal Serial Bus (USB), and Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0003] However, existing simulation tools (such as Keysight ADS and Cadence Sigrity) mainly generate basic eye diagrams based on the inherent linear characteristics of the channel, such as scattering parameters (S-parameters), insertion loss, return loss, crosstalk, and reflection. While these basic eye diagrams can reflect the filtering and distortion effects of the channel itself, they cannot simulate the jitter phenomena that exist in actual communication scenarios.

[0004] Therefore, there is an urgent need in this field for a method that can integrate the high-fidelity simulation of deterministic and random jitter into the channel simulation process; and can directly embed the jitter effect during the eye diagram generation process, thereby providing more realistic simulation results for performance evaluation and margin analysis to meet the design and verification needs of high-speed communication systems. Summary of the Invention

[0005] To address the aforementioned issues, this application provides an eye diagram generation method, storage medium, and electronic device based on channel simulation.

[0006] In a first aspect, this application provides an eye diagram generation method based on channel simulation, comprising: Channel simulation is performed based on the target channel parameters, signal source parameters, and initial code pattern sequence to generate jitter-free initial eye diagram data; Based on the acquired deterministic jitter parameters and the initial code pattern sequence, a deterministic jitter time sequence is generated; Based on the obtained random jitter parameters, a random jitter time series sequence is generated; The deterministic jitter time series sequence and the random jitter time series sequence are combined to generate a total jitter time series offset sequence; The timing information in the initial eye diagram data is modulated using the total jitter timing offset sequence to generate the target eye diagram.

[0007] In one implementation, the eye diagram generation method based on channel simulation further includes: The deterministic jitter parameters are obtained by receiving user input configuration of deterministic jitter types and corresponding parameters; wherein, the deterministic jitter types include data-dependent jitter and periodic jitter; the data-dependent jitter includes inter-symbol interference jitter and duty cycle distortion jitter; The random jitter parameter is obtained by receiving user input configuration of statistical distribution type and distribution parameters; wherein, the statistical distribution type includes Gaussian distribution.

[0008] In one implementation, before generating the deterministic jitter time sequence based on the acquired deterministic jitter parameters and the initial code pattern sequence, the method further includes: Obtain the target performance metrics of the target eye map, wherein the target performance metrics include target eye height and target eye width; Using the deterministic jitter parameter and the random jitter parameter as optimization variables; and utilizing the pre-established performance prediction relationship, the predicted eye diagram performance is obtained based on the values ​​of the target channel parameter and the optimization variables; By optimizing the search, the value of the optimization variable that minimizes the difference between the predicted eye diagram performance and the target performance index is found, and it is used as the combination of the deterministic jitter parameter and the random jitter parameter. The performance prediction relationship is an empirical model, which is pre-trained based on historical simulation data; the optimization search algorithm includes gradient descent, genetic algorithm, and Bayesian optimization.

[0009] In one implementation, the generation of a deterministic jitter time series further includes: The transition edges and their context bits of the initial code pattern sequence are analyzed to determine the transition mode to which each transition edge belongs; Based on a preset deterministic jitter model, a corresponding timing jitter value is assigned to each of the transition modes; Based on the timing jitter value, a deterministic jitter timing sequence synchronized with the initial code pattern sequence is generated.

[0010] In one implementation, the generation of random jitter time series sequences further includes: Acquire the target signal output from the channel simulation and extract the waveform features of the target signal; Based on the waveform characteristics, determine the distribution parameters of the random jitter statistical model; In response to the detection of a level change in the signal source parameters, a random jitter value is generated and injected based on the distribution parameters using a random number generation algorithm to generate the random jitter timing sequence.

[0011] In one implementation, the step of synthesizing the deterministic jitter time series sequence and the random jitter time series sequence to generate a total jitter time series offset sequence further includes: According to a preset configuration order, the deterministic jitter time series sequence and the random jitter time series sequence are synthesized to generate the total jitter time series offset sequence; wherein, the configuration order includes deterministic jitter priority superposition, random jitter priority superposition, and simultaneous superposition of deterministic jitter and random jitter; During the synthesis process, the deterministic jitter timing sequence and / or the random jitter timing sequence are adjusted according to a preset coupling rule to simulate the interaction between the deterministic jitter and the random jitter.

[0012] Secondly, this application provides an electronic device, comprising: The channel simulation module is configured to perform channel simulation based on the target channel parameters, signal source parameters and initial code sequence, and generate jitter-free initial eye diagram data. The jitter generation module is configured to generate a deterministic jitter time series sequence based on the acquired deterministic jitter parameters and the initial code pattern sequence; and to generate a random jitter time series sequence based on the acquired random jitter parameters. The jitter overlay module is configured to synthesize the deterministic jitter time series sequence with the random jitter time series sequence to generate a total jitter time series offset sequence. The eye diagram generation module is also configured to modulate the timing information in the initial eye diagram data using the total jitter timing offset sequence to generate a target eye diagram.

[0013] In one implementation, the electronic device further includes: an interaction module configured for user input of deterministic jitter type and corresponding parameters, and statistical distribution type and distribution parameters of random jitter; wherein the deterministic jitter type includes data-related jitter and periodic jitter; the data-related jitter includes inter-symbol interference jitter and duty cycle distortion jitter; and the statistical distribution type includes Gaussian distribution.

[0014] In one implementation, the electronic device further includes: a processing module configured to acquire a target performance index of the target eye diagram, using the deterministic jitter parameter and the random jitter parameter as optimization variables; using a pre-established performance prediction relationship, to obtain a predicted eye diagram performance based on the values ​​of the target channel parameter and the optimization variables; and through optimization search, to find the value of the optimization variable that minimizes the difference between the predicted eye diagram performance and the target performance index, as a combination of the deterministic jitter parameter and the random jitter parameter.

[0015] Thirdly, this application provides a storage medium storing a computer program or instructions thereon, wherein when the computer program or instructions are executed by a processor, the steps of the eye diagram generation method based on channel simulation described in any of the above claims are implemented.

[0016] Fourthly, this application provides an electronic device, further comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the eye diagram generation method based on channel simulation described in any of the above claims.

[0017] Compared with the prior art, this application has at least one of the following beneficial effects: This application adds the simulation of deterministic jitter and random jitter during the channel simulation process, so that the simulated eye diagram can present the timing and amplitude erosion caused by jitter, which greatly improves the consistency between the simulation results and the signal characteristics of the real communication scenario.

[0018] This application includes a jitter eye diagram, which enables channel performance evaluation to cover jitter factors, providing a reliable data foundation for design decisions of products such as chips, circuit boards, and communication modules, and reducing R&D risks and costs.

[0019] This application achieves seamless integration of channel simulation and jitter analysis, supporting the completion of the entire "setup-simulation-analysis" process in the same environment without the need for additional tools for secondary processing, thus improving simulation efficiency and ease of operation.

[0020] This application not only allows for the input and configuration of deterministic and random jitter parameters, enabling flexible adjustments to adapt to different communication standards and application scenarios; it also allows for the reverse derivation of combinations of deterministic and random jitter parameters based on the target eye diagram performance, providing closed-loop verification and optimization for link design and improving simulation efficiency.

[0021] This application supports multiple deterministic jitter types, random jitter distribution models, and flexible parameter configuration, and is fully compatible with mainstream high-speed communication standards such as PCIe, USB, and DDR, effectively reducing the technical threshold and usage costs for users.

[0022] This application simulates the coupling effect between jitter, channel characteristics, and signal code patterns through a time-dependent nonlinear superposition strategy, thereby making the morphological characteristics and statistical distribution of the simulated eye diagram closer to the actual measurement results. Attached Figure Description

[0023] The accompanying drawings used in the description of the embodiments of this application are briefly introduced below: Figure 1 This is a flowchart of an eye diagram generation method based on channel simulation provided in an embodiment of this application; Figure 2This is a partial flowchart of an eye diagram generation method based on channel simulation provided in an embodiment of this application; Figure 3 This is a flowchart illustrating step S300 provided in an embodiment of this application; Figure 4 This is another flowchart illustrating step S300 provided in an embodiment of this application; Figure 5 This is a block diagram of an electronic device provided in an embodiment of this application; Figure 6 This is a schematic diagram of an eye diagram without jitter provided in an embodiment of this application; Figure 7 This is a schematic diagram of an eye diagram with jitter provided in an embodiment of this application; Figure 8 This is a schematic diagram of an eye diagram with unreasonable jitter added, provided in an embodiment of this application. Detailed Implementation

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the specific implementation methods of this application will be described below with reference to the accompanying drawings. The drawings and implementation methods described below are merely some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings and implementation methods without creative effort. Any adjustments and improvements made without departing from the concept of this application are within the protection scope of this application.

[0025] To keep the drawings concise, only the parts relevant to this application are shown schematically in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some parts with the same structure or function are only shown schematically in some drawings, and there may actually be more or fewer parts with the same structure or function.

[0026] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first" and "second," are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the number of related objects. The terms "installation" and "connection" should be interpreted broadly; for example, "installation" can mean direct installation or installation via other components; "connection" can mean direct connection or connection via other components.

[0027] In the field of high-speed serial communication, channel simulation, as a key means of evaluating channel transmission performance, is widely used in the design and verification stages of products such as chips, circuit boards, and communication modules. Eye diagrams, as an output of channel simulation, can intuitively reflect the amplitude distortion and timing deviations of signals after transmission through the channel, and are an important basis for judging whether signal integrity meets communication standards such as PCIe, USB, and DDR.

[0028] However, existing simulation tools (such as Keysight ADS and Cadence Sigrity) mainly generate basic eye diagrams based on the inherent linear characteristics of the channel, such as scattering parameters (S-parameters), insertion loss, return loss, crosstalk, and reflection. While these basic eye diagrams can reflect the filtering and distortion effects of the channel itself, they cannot simulate the jitter phenomena that exist in actual communication scenarios.

[0029] In practice, jitter is a core factor affecting the timing tolerance and bit error rate of communication systems, mainly including deterministic jitter and random jitter. Deterministic jitter is caused by deterministic factors such as data-correlated jitter (including inter-symbol interference and duty cycle distortion), periodic interference, and bounded uncorrelated jitter, exhibiting repeatability and predictability. Random jitter, on the other hand, is caused by random factors such as thermal noise, power supply noise, and shot noise, and its statistical characteristics typically conform to a Gaussian distribution. In practical systems, the final eye diagram shape of the signal is the result of the combined effects of channel characteristics and various types of jitter.

[0030] The eye diagrams generated by existing channel simulation processes represent the response of an ideal, jitter-free signal passing through the channel. This leads to discrepancies between simulation results and actual test scenarios, failing to accurately reflect the eye diagram closure, jitter bathtub curve, and corresponding bit error rate risk under jitter influence. On one hand, the lack of jitter-simulated eye diagrams fails to capture the actual erosion of timing and amplitude margins by jitter. Using these results for performance evaluation (such as eye height and eye width measurements) may misjudge channel performance, resulting in insufficient design margins and revealing problems during later testing, thus increasing product development cycles, costs, and tape-out risks. On the other hand, while some specialized tools support independent jitter analysis, this typically requires exporting the simulation results to another dedicated jitter analysis tool for secondary processing after channel simulation. This fragmented process is not only complex but also fails to achieve real-time, dynamic linkage between jitter parameters and channel simulation.

[0031] Therefore, there is an urgent need in this field for a method that can integrate the high-fidelity simulation of deterministic and random jitter into the channel simulation process; and can directly embed the jitter effect during the eye diagram generation process, thereby providing more realistic simulation results for performance evaluation and margin analysis to meet the design and verification needs of high-speed communication systems.

[0032] To address the aforementioned technical issues, this application provides an eye diagram generation method based on channel simulation. This method integrates deterministic and random jitter simulation during the channel simulation process, achieving a seamless transition from channel simulation to jitter analysis. It supports the entire "setup-simulation-analysis" process within the same environment, eliminating the need for additional tools and improving simulation efficiency and ease of operation. Furthermore, the simulated eye diagram can visualize the timing and amplitude erosion caused by jitter, significantly enhancing the consistency between simulation results and signal characteristics in real-world communication scenarios. The inclusion of a jitter-infused eye diagram allows channel performance evaluation to encompass jitter factors, providing a reliable data foundation for design decisions in chips, circuit boards, and communication modules, thereby reducing R&D risks and costs.

[0033] The following explanation is based on the accompanying drawings: like Figure 1 As shown, an eye diagram generation method based on channel simulation includes: S100. Perform channel simulation based on target channel parameters, signal source parameters and initial code sequence to generate jitter-free initial eye diagram data. S300. Based on the acquired deterministic jitter parameters and the initial code pattern sequence, generate a deterministic jitter time sequence; S400. Based on the acquired random jitter parameters, generate a random jitter time series sequence; S500. Combine the deterministic jitter time series sequence with the random jitter time series sequence to generate the total jitter time series offset sequence. S600: Modulate the timing information in the initial eye diagram data using the total jitter timing offset sequence to generate the target eye diagram.

[0034] In this embodiment, the target channel parameters are obtained by extracting the frequency domain characteristics of the physical link to be evaluated. The physical link includes printed circuit board traces, cables, or connectors; its frequency domain characteristics are characterized by scattering parameters, including performance indicators such as channel loss, impedance, and crosstalk coefficient. Signal source parameters are set, such as signal amplitude, code rate, and modulation scheme. The signal source parameters, initial code sequence, and target channel parameters are injected into the channel model, and it is driven to perform time-domain or frequency-domain simulation based on traditional algorithms such as convolution or circuit-level simulation; the response output waveform of the target signal after passing through the target channel is calculated. Clock recovery and synchronization are performed on the simulated output waveform, and the waveform is cut and superimposed at unit intervals to generate a statistical eye diagram. The timing and amplitude information of this eye diagram is extracted to form structured "initial eye diagram data." This data does not introduce any jitter during generation and only reflects the inherent linear impairments (such as insertion loss and return loss) experienced by the signal source after passing through the target channel. Figure 6 The resulting jitter-free base eye diagram is shown.

[0035] The user interface can receive configurations for both deterministic and random jitter parameters. For example, it can receive user-selected or input deterministic jitter types and corresponding parameters. Deterministic jitter types include, but are not limited to: data-related jitter (including inter-symbol interference jitter and duty cycle distortion jitter) and periodic interference jitter. Specifically, inter-symbol interference jitter refers to the jitter amplitude caused by inter-symbol interference; duty cycle distortion jitter refers to the difference in width between the rising and falling edges; and periodic interference jitter refers to the amplitude and frequency of sinusoidal jitter. Corresponding parameters include amplitude and period. The user interface can also receive user-selected or input statistical distribution types and parameters, typically a Gaussian distribution. Distribution parameters include standard deviation and expected value. Furthermore, the user interface supports starting / pausing the simulation, viewing the channel simulation progress, and viewing the target eye diagram and performance metrics.

[0036] Based on the deterministic jitter parameters and the initial code pattern sequence, a deterministic jitter timing sequence is generated. Taking inter-symbol interference jitter (DDJ) as an example, the edge-jumping patterns in the PRBS code stream (such as the first 3 bits followed by the last bit) are analyzed. According to a preset DDJ model related to channel loss (which defines fixed timing offsets for different patterns), a deterministic jitter value is assigned to each edge-jumping pattern, thus forming a deterministic jitter timing sequence with a length equal to the code pattern and a definite value. Based on the random jitter parameters, a random jitter timing sequence conforming to a specified Gaussian distribution is generated using a random number generator (such as using the Monte Carlo method), and its length matches the number of unit intervals to be simulated. The generated deterministic jitter timing sequence and the random jitter timing sequence are superimposed according to a preset synthesis rule to obtain the total jitter timing offset sequence; for example, the total jitter timing offset sequence equals the deterministic jitter timing sequence plus the random jitter timing sequence.

[0037] The initial eye diagram data is read, which is a series of waveform sampling points arranged in time. Each sampling point includes the initial timing and voltage amplitude relative to an ideal clock. The total jitter timing offset sequence is mapped to the corresponding unit interval, and the timing of all sampling points within that unit interval is modulated. The modulated timing of each sampling point is equal to the sum of its initial timing and the total jitter timing offset corresponding to its unit interval. Eye diagram overlay analysis is performed on the modulated new waveform data to directly generate "eye diagram simulation data with jitter," reflecting the final eye diagram of the signal on the target channel after overlaying the specified jitter.

[0038] The generated eye diagram simulation data undergoes post-processing to optimize its visualization and analysis quality. This post-processing includes: removing simulation noise through smoothing filtering; eliminating outlier data points using statistical methods; and performing high-density interpolation sampling on the central region of the eye diagram to obtain a final eye diagram with clearer contours and more prominent features. Based on the processed eye diagram simulation data, the target eye diagram is drawn, and key performance indicators, such as eye height, eye width, and jitter histogram, are measured and labeled. Figure 7 The target eye diagram contains jitter and is output in image format (such as PNG or SVG). Performance metrics are output in table or text format for easy subsequent analysis and report generation.

[0039] In one implementation, the deterministic jitter parameters are obtained by receiving user input configuration of deterministic jitter types and corresponding parameters; wherein, the deterministic jitter types include data-dependent jitter and periodic jitter; the data-dependent jitter includes inter-symbol interference jitter and duty cycle distortion jitter.

[0040] The randomness jitter parameter is obtained by receiving user input configuration of statistical distribution type and distribution parameters; among which, the statistical distribution type includes Gaussian distribution.

[0041] In this embodiment, "total jitter" (TJ) consists of "random jitter" (RJ) and "deterministic jitter" (DJ). Random jitter (RJ) is generally distributed using a Gaussian distribution, with the standard deviation and expected value set as parameters. Deterministic jitter (DJ) includes periodic jitter (PJ) and data-dependent jitter (DDJ). Data-dependent jitter (DDJ) includes duty cycle distortion jitter (DCD) and inter-symbol interference jitter (ISI).

[0042] The graphical user interface (GUI) or command-line interface presents a parameter configuration area for deterministic jitter (DJ) to the user; this area allows users to input or select the deterministic jitter type and parameters. Taking data-dependent jitter (DDJ) as an example, its inter-symbol interference (ISI) jitter provides an "ISI Jitter" option on the interface; when selected, the interface displays the corresponding parameter input boxes; parameters typically include jitter amplitude (in picoseconds, ps), used to define the maximum timing offset caused by the history of the data pattern. Its duty cycle distortion (DCD) jitter provides a "DCD Jitter" option on the interface; when selected, the interface requires inputting the difference in width between the rising and falling edges, or specifying the offset of the rising and falling edges relative to the ideal position respectively.

[0043] In the same or different configuration areas, a parameter configuration area for random jitter (RJ) is presented to the user; this area allows the user to input or select the distribution type and distribution parameters. For Gaussian distribution, the interface provides "Gaussian Jitter" or "RJ" options; when selected, the interface parameter input box displays the standard deviation or maximum jitter amplitude to define the intensity of the random jitter.

[0044] In one implementation, such as Figure 2 As shown, before generating the deterministic jitter time series based on the acquired deterministic jitter parameters and the initial code pattern sequence, the process further includes: S200. Obtain the target performance metrics of the target eye diagram, including target eye height and target eye width. S201. Using deterministic jitter parameters and random jitter parameters as optimization variables, and utilizing a pre-established performance prediction relationship, the predicted eye diagram performance is obtained based on the values ​​of the target channel parameters and optimization variables. The performance prediction relationship is an empirical model, which is pre-trained based on historical simulation data.

[0045] S202. By optimizing the search, find the values ​​of the optimization variables that minimize the difference between the predicted eye diagram performance and the target performance index, and use them as a combination of deterministic jitter parameters and random jitter parameters; the optimization search algorithms include gradient descent, genetic algorithm, and Bayesian optimization.

[0046] In this embodiment, the target performance indicators of the desired eye diagram, set by the user, are received through a graphical user interface or configuration file. These target performance indicators include at least the target eye height and target eye width; for example, "eye height must be no less than 80 mV" and "eye width must be no less than 0.7 UI". The characteristic parameters of the physical channel to be evaluated, i.e., the target channel parameters, are obtained, which define the fixed environment for signal transmission.

[0047] The deterministic and random jitter parameters to be determined are defined as optimization variables. A pre-trained performance prediction model is invoked, which establishes a mapping from "channel and jitter parameters" to "eye diagram performance." This model is trained on massive amounts of historical simulation data, specifically by performing full-link simulations on diverse channel models and jitter parameter combinations (deterministic and random jitter parameters), collecting corresponding real eye diagram performance metrics (such as eye height and eye width), and using this data to train a machine learning model (e.g., a neural network) to learn and internalize the relationship between channel, jitter, and eye diagram performance.

[0048] The optimization process is executed iteratively through an algorithm. Each iteration includes the following steps: First, the algorithm generates a set of candidate jitter parameters based on historical data; the candidate jitter parameters are input into a performance prediction model to obtain the predicted eye diagram performance, and the difference between this and the target performance is calculated as the loss value; the algorithm updates its search strategy based on this loss value. This loop continues until the loss value is lower than the preset tolerance or the maximum number of iterations is reached. At the end of the loop, the combination of jitter parameters with the minimum loss is output as the optimal solution. During the optimization process, for any set of candidate jitter parameters (i.e., deterministic jitter parameters and random jitter parameters), there is no need to run a time-consuming full physical simulation. Simply inputting (target channel parameters, jitter parameter combination) into the machine learning model yields the predicted eye diagram performance. If the added jitter parameters are unrealistic or deviate excessively from physical reality, the generated simulated eye diagram will be severely distorted or completely closed, making it impossible to effectively define or measure key indicators such as eye height and eye width, thus rendering the simulation results worthless. Figure 8 As shown.

[0049] This embodiment achieves a fundamental shift from experience-based trial-and-error simulation to target-based automated optimization by inversely deriving jitter parameters based on target eye diagram performance. Users only need to set the desired eye diagram performance (such as eye height and eye width) to inversely solve for the optimal or feasible combination of jitter parameters that meets that performance requirement. This significantly reduces the professional threshold and time cost of simulation configuration; at the same time, this closed-loop process also greatly improves the reliability and efficiency of design verification.

[0050] In one implementation, such as Figure 3 As shown, the generation of a deterministic jitter time series in step S300 further includes: S310. Analyze the transition edges and their context bits of the initial code pattern sequence to determine the transition mode to which each transition edge belongs; S320. Based on a preset deterministic jitter model, assign a corresponding timing jitter value to each transition mode; S330. Based on the timing jitter value, generate a deterministic jitter timing sequence that is synchronized with the initial code pattern sequence.

[0051] In this embodiment, during the channel simulation process, an excitation signal needs to be input into the channel model to generate an initial (jitter-free) eye diagram. This excitation signal is driven by a specific digital code pattern sequence, namely the initial code pattern sequence, where each symbol takes the value of logic '0' or '1'. This sequence typically uses a standardized test code pattern, such as a pseudo-random binary sequence or a periodic square wave, or it can be a custom code pattern defined by the user according to specific requirements.

[0052] The initial code pattern sequence is scanned sequentially to identify all locations where logical state changes occur, i.e., transition edges. These include rising edges from '0' to '1' and falling edges from '1' to '0'. For each detected signal transition edge, bits within a certain range before and after the transition edge are extracted to form its "context". Combining the context bits with the direction information of the transition edge constitutes a unique transition pattern. For example, the pattern "000↑1" (representing three consecutive 0s followed by a rising edge and then a 1) and the pattern "111↓0" (representing three consecutive 1s followed by a falling edge and then a 0) are two different typical patterns.

[0053] The built-in deterministic jitter model defines the mapping relationship from transition patterns to timing offsets. This model is pre-established based on the target channel characteristics. During processing, for each identified transition edge and its pattern, the corresponding jitter value (in ps, positive or negative represents delay or advance) is obtained from the model. Subsequently, a deterministic jitter timing sequence synchronized with the original code pattern is generated. Each position in the deterministic jitter timing sequence corresponds to a time point. If the point is a transition edge, the jitter value obtained from the query is filled in; otherwise, zero is filled in. Ultimately, this deterministic jitter timing sequence ensures that each data edge can be applied a timing offset consistent with its physical cause.

[0054] In one implementation, such as Figure 4 As shown, the generation of random jitter time series sequences in step S400 further includes: S410. Obtain the target signal output from the channel simulation and extract the waveform features of the target signal; S420. Based on the waveform characteristics, determine the distribution parameters of the random jitter statistical model; S430. Based on the distribution parameters, generate a random jitter time series sequence associated with the initial code pattern sequence.

[0055] In this embodiment, channel simulation is performed based on the target channel parameters and signal source parameters to obtain the target signal after channel simulation. This target signal is the response output waveform of an ideal signal without jitter after passing through the channel. The target signal is analyzed to extract waveform features; these features include at least one or more of the following: Instantaneous slope: Calculate the first derivative of the waveform at each sampling point; this directly determines the magnitude of timing disturbances caused by fixed voltage noise. Instantaneous amplitude: Obtain the voltage value of the waveform at each sampling point; this reflects the difference in the circuit's sensitivity to noise at different operating points.

[0056] The random jitter statistical model assumes that random jitter follows a specific statistical distribution, such as a Gaussian distribution; and defines its distribution parameters. Taking the Gaussian distribution as an example, its distribution parameters are the mean and variance. The mean is usually set to 0, while the variance directly determines the intensity of the jitter.

[0057] Based on the extracted waveform features, the distribution parameters in the random jitter statistical model are adjusted according to predefined rules, especially the distribution parameters controlling the jitter intensity. For example, a slope-dependent rule establishes an inverse relationship between the jitter variance and the absolute value of the instantaneous slope, simulating that the same voltage noise produces a smaller timing offset when the signal edge changes rapidly and a larger timing offset when the change is slow. A conditional triggering rule applies random jitter only near the effective transition edge, or increases the variance when the signal amplitude approaches the decision threshold, to simulate the phenomenon of increased noise sensitivity of the circuit in the metastable region.

[0058] By calculating the dynamic distribution parameters for each time point or signal unit, random jitter is modeled as a non-stationary process whose statistical characteristics change with the signal state. A parameter-controllable random number generator is used to generate jitter samples based on the dynamic parameters corresponding to each time point. This process is repeated for all time points to generate a random jitter sequence. Each value in this sequence is determined by the signal characteristics at the corresponding time point; therefore, it is a conditional sequence strongly correlated with the original signal, rather than an independent and identically distributed sequence.

[0059] In one implementation, generating a random jitter time-series sequence associated with an initial code pattern sequence includes: In response to the detection of a level change in the target signal, a random jitter value is generated and injected based on the distributed parameters using a random number generation algorithm to generate a random jitter time sequence.

[0060] In this embodiment, the target signal is continuously monitored, and the voltage transition edges that cross the logic threshold are detected in real time, with the transition time and direction recorded. For each detected transition edge, local signal features (such as slope) at that moment are acquired to determine its distribution parameters. Using these distribution parameters as conditions, a random number generation is triggered to obtain a single random jitter value. This single random jitter value is bound to the corresponding transition time, considered as the timing offset at that moment. The jitter values ​​generated by all transition edges are stored in a sequence in chronological order to construct a random jitter timing sequence. For stable signal periods, no jitter or only a very small amount of jitter may be injected.

[0061] In one implementation, the deterministic jitter time series sequence is synthesized with the random jitter time series sequence to generate a total jitter time series offset sequence, and the method further includes: According to the preset configuration order, deterministic jitter time series sequences and random jitter time series sequences are synthesized to generate a total jitter time series offset sequence; wherein, the configuration order includes deterministic jitter priority superposition, random jitter priority superposition, and synchronous superposition; During the synthesis process, the deterministic jitter time series and / or random jitter time series are adjusted according to the preset coupling rules to simulate the interaction between deterministic jitter and random jitter.

[0062] In this embodiment, the jitter overlay configuration order is obtained by receiving a user-specified configuration or from a configuration file. This configuration order defines the order in which deterministic jitter sequences and random jitter sequences are combined, providing at least three preset configuration orders: Deterministic jitter priority overlay (DJ priority overlay), which applies the complete deterministic jitter timing offset first, then overlays the random jitter timing offset; Random jitter priority overlay (RJ priority overlay), which applies the complete random jitter timing offset first, then overlays the deterministic jitter timing offset; and Synchronous overlay, which directly merges corresponding points of the deterministic and random jitter timing sequences in a single-step operation (usually the default or basic mode). Users can choose the overlay order according to the actual communication scenario; for example, the "RJ priority overlay" mode is selected in a strong random noise environment, while the "DJ priority overlay" mode is selected in a strong deterministic interference environment.

[0063] Simultaneously, a preset coupling rule is obtained to define the interaction between deterministic and random jitter, thereby more realistically simulating the interaction of various jitter sources in a real chip. For example, the coupling rule can be set to increase the variance of the random jitter distribution accordingly when the deterministic jitter amplitude exceeds a set threshold, in order to simulate the noise amplification effect. The coupling rule can be embodied in a mathematical function, a conditional judgment table, or a lightweight physics model. To ensure processing consistency, the deterministic jitter sequence and the random jitter sequence must be completely aligned in the time domain, that is, they must be of equal length and their indices must strictly correspond, with each index representing a unit interval or a sampling time.

[0064] Subsequently, the characteristics of the jitter sequence are analyzed according to the coupling rules, and the sequence is dynamically adjusted to simulate the interaction. For example, if the coupling rules define the influence of deterministic jitter amplitude on the intensity of random jitter, then the values ​​of the random jitter sequence are scaled proportionally to the deterministic jitter amplitude. After adjustment, the updated sequence is recalculated in the original synthesis order to obtain the total jitter time-series offset sequence that includes the coupling effect between jitters.

[0065] In some embodiments, such as Figure 5 As shown, an electronic device includes a channel simulation module 100 configured to perform channel simulation based on target channel parameters, signal source parameters and an initial code pattern sequence, and generate jitter-free initial eye diagram data.

[0066] The jitter generation module 300 is configured to generate a deterministic jitter time series sequence based on the acquired deterministic jitter parameters and the initial code pattern sequence; and to generate a random jitter time series sequence based on the acquired random jitter parameters. As a preferred embodiment, the jitter generation module 300 includes a deterministic jitter generation submodule for generating the deterministic jitter time series sequence and a random jitter generation submodule for generating the random jitter time series sequence.

[0067] The jitter overlay module 400 is configured to synthesize a deterministic jitter time series sequence with a random jitter time series sequence to generate a total jitter time series offset sequence. The eye diagram generation module 600 is also configured to modulate the timing information in the initial eye diagram data using the total jitter timing offset sequence to generate the target eye diagram.

[0068] In some embodiments, an electronic device further includes an interaction module 200 configured to allow a user to input configuration of deterministic jitter type and corresponding parameters, as well as statistical distribution type and distribution parameters of random jitter.

[0069] In some embodiments, an electronic device further includes: a processing module 500 configured to acquire a target performance index of a target eye diagram, using deterministic jitter parameters and random jitter parameters as optimization variables; using a pre-established performance prediction relationship, and based on the values ​​of the target channel parameters and the optimization variables, to obtain a predicted eye diagram performance; and through optimization search, to find the value of the optimization variable that minimizes the difference between the predicted eye diagram performance and the target performance index, as a combination of deterministic jitter parameters and random jitter parameters.

[0070] In this embodiment, a PCIe 5.0 high-speed communication channel is used as the application scenario, and the jitter parameters are configured as follows: Deterministic jitter: Inter-symbol interference is used, with an amplitude of 12 ps, which meets the typical requirements of the PCIe 5.0 specification for deterministic jitter. Random jitter: Follows a Gaussian distribution, with a standard deviation of 6 ps, reaching the maximum value allowed by the PCIe 5.0 specification. Jitter synthesis mode: Synchronous superposition mode is used.

[0071] Users input target channel parameters, signal source parameters, and the aforementioned jitter configuration parameters through a graphical user interface. The storage module saves all input parameters, initializes each functional module (such as the channel simulation module and jitter generation module), and loads the corresponding algorithm library and model.

[0072] The channel simulation module reads the target channel parameters and signal source parameters, runs the simulation to generate test signal waveforms, and generates basic eye diagram data without any jitter by performing periodic superposition analysis on the waveforms.

[0073] The jitter generation module reads the jitter configuration parameters and performs the following operations: Generating a deterministic jitter sequence: Based on the inter-symbol interference (ISI) model, it analyzes the code pattern sequence of the test signal (such as combinations like "101" and "010"), calculates the corresponding timing offset for each symbol transition edge (ranging from -12 ps to +12 ps, with the specific value strictly related to the preceding and following code patterns), and generates a DJ timing offset array. Generating a random jitter sequence: Using the Monte Carlo algorithm, it generates a Gaussian distributed random number sequence with a mean of 0 and a standard deviation of 6 ps, and performs 3σ truncation to form an RJ timing offset array.

[0074] If the user sets a target eye diagram performance (such as target eye height and eye width), the reverse optimization process will be initiated. The processing module calls an automatic parameter search algorithm (such as Bayesian optimization) to automatically adjust and evaluate different DJ / RJ parameter combinations within the preset physical constraints, so that the final eye diagram performance generated by the simulation converges to the target value set by the user, and outputs the optimal jitter parameter combination that meets the requirements.

[0075] The jitter overlay module reads the basic eye diagram data, DJ sequence, and RJ sequence. In "synchronous overlay" mode, for each sampling point, its original time series is added to the corresponding DJ and RJ offsets to obtain the total jitter offset, thereby generating the original eye diagram data with jitter.

[0076] The eye diagram generation module processes the raw data to improve quality, for example: noise reduction using moving average filtering to remove isolated sampling points with abnormal amplitudes (such as points with offsets exceeding ±50 ps); synchronization calibration, performing timing synchronization calibration on the eye diagram according to the PCIe 5.0 clock specification to ensure accurate alignment of the eye diagram center; and contour generation, supplementing data points through interpolation algorithms to draw a clear, jitter-free simulated eye diagram and automatically calculating key metrics, namely eye height and eye width.

[0077] In a preferred embodiment, the electronic device also includes an output module configured to export the final simulated eye diagram in a standard waveform format (such as tr0). Users can view the results through an interactive interface, intuitively compare the morphological differences between the basic eye diagram and the jitter-inducing eye diagram, and evaluate whether the channel meets design requirements under specified jitter pressure based on indicators such as eye height and eye width.

[0078] By comparing the simulation output of this embodiment with the actual PCIe 5.0 hardware test results, the effectiveness and advantages of this application are verified: the generated simulated eye diagram with jitter has a deviation of less than 2% from the actual test results in key indicators such as eye height and eye width, which is far below the engineering acceptable range of 5%, proving the high fidelity of the simulation model.

[0079] This embodiment automates the entire process from parameter configuration, jitter generation, overlay synthesis to result analysis. Compared to the traditional "channel simulation + independent jitter analysis" mode that requires separate tools and manual operation, simulation efficiency is improved by orders of magnitude. Furthermore, through reverse optimization, it can directly answer design margin questions, greatly enhancing design insight.

[0080] In some embodiments, an electronic device further includes: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement a channel simulation-based eye diagram generation method.

[0081] The above division of units is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these units can be implemented by a processor calling software; for example, an electronic device includes a processor connected to memory, which stores instructions. The processor calls the instructions stored in memory to implement any of the above methods or to realize the functions of each unit. The processor can be, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory can be internal or external to the device. Alternatively, these units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, in some embodiments, the hardware circuit is an application-specific integrated circuit (ASIC), which implements the functions of some or all units by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby realizing the functions of some or all units. All units of the above devices can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs with the remaining parts implemented through hardware circuits.

[0082] Furthermore, embodiments of this application also provide a storage medium including instructions stored thereon, which, when invoked by a processor, execute any of the eye diagram generation methods based on channel simulation in the above embodiments.

[0083] The computer-readable storage media described above may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0084] It should be noted that the above embodiments can be freely combined as needed. The above are only some embodiments of this application. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be considered within the protection scope of this application.

Claims

1. An eye diagram generation method based on channel simulation, characterized in that, include: Channel simulation is performed based on the target channel parameters, signal source parameters, and initial code pattern sequence to generate jitter-free initial eye diagram data; Based on the acquired deterministic jitter parameters and the initial code pattern sequence, a deterministic jitter time sequence is generated; Based on the obtained random jitter parameters, a random jitter time series sequence is generated; The deterministic jitter time series sequence and the random jitter time series sequence are combined to generate a total jitter time series offset sequence; The timing information in the initial eye diagram data is modulated using the total jitter timing offset sequence to generate the target eye diagram.

2. The eye diagram generation method based on channel simulation according to claim 1, characterized in that, Also includes: The deterministic jitter parameters are obtained by receiving user input configuration of deterministic jitter types and corresponding parameters; wherein, the deterministic jitter types include data-dependent jitter and periodic jitter; the data-dependent jitter includes inter-symbol interference jitter and duty cycle distortion jitter; The random jitter parameter is obtained by receiving user input configuration of statistical distribution type and distribution parameters; wherein, the statistical distribution type includes Gaussian distribution.

3. The eye diagram generation method based on channel simulation according to claim 1, characterized in that, Before generating the deterministic jitter time series based on the acquired deterministic jitter parameters and the initial code pattern sequence, the method further includes: Obtain the target performance metrics of the target eye map, wherein the target performance metrics include target eye height and target eye width; Using the deterministic jitter parameter and the random jitter parameter as optimization variables; and utilizing the pre-established performance prediction relationship, the predicted eye diagram performance is obtained based on the values ​​of the target channel parameter and the optimization variables; By optimizing the search, the value of the optimization variable that minimizes the difference between the predicted eye diagram performance and the target performance index is found, and it is used as the combination of the deterministic jitter parameter and the random jitter parameter. The performance prediction relationship is an empirical model, which is pre-trained based on historical simulation data; the optimization search algorithm includes gradient descent, genetic algorithm, and Bayesian optimization.

4. The eye diagram generation method based on channel simulation according to any one of claims 1 to 3, characterized in that: The generation of deterministic jitter time series further includes: The transition edges and their context bits of the initial code pattern sequence are analyzed to determine the transition mode to which each transition edge belongs; Based on a preset deterministic jitter model, a corresponding timing jitter value is assigned to each of the transition modes; Based on the timing jitter value, a deterministic jitter timing sequence synchronized with the initial code pattern sequence is generated; The generation of random jitter time series sequences further includes: Acquire the target signal output from the channel simulation and extract the waveform features of the target signal; Based on the waveform characteristics, determine the distribution parameters of the random jitter statistical model; In response to the detection of a level transition in the signal source parameters, a random jitter value is generated and injected based on the distribution parameters using a random number generation algorithm to generate the random jitter timing sequence associated with the initial code pattern sequence.

5. The eye diagram generation method based on channel simulation according to any one of claims 1 to 3, characterized in that, The method of synthesizing the deterministic jitter time series sequence and the random jitter time series sequence to generate a total jitter time series offset sequence further includes: According to a preset configuration order, the deterministic jitter time series sequence and the random jitter time series sequence are synthesized to generate the total jitter time series offset sequence; wherein, the configuration order includes deterministic jitter priority superposition, random jitter priority superposition, and simultaneous superposition of deterministic jitter and random jitter; During the synthesis process, the deterministic jitter timing sequence and / or the random jitter timing sequence are adjusted according to a preset coupling rule to simulate the interaction between the deterministic jitter and the random jitter.

6. An electronic device, characterized in that, include: The channel simulation module is configured to perform channel simulation based on the target channel parameters, signal source parameters and initial code sequence, and generate jitter-free initial eye diagram data. The jitter generation module is configured to generate a deterministic jitter time series sequence based on the acquired deterministic jitter parameters and the initial code pattern sequence; and to generate a random jitter time series sequence based on the acquired random jitter parameters. The jitter overlay module is configured to synthesize the deterministic jitter time series sequence with the random jitter time series sequence to generate a total jitter time series offset sequence; The eye diagram generation module is also configured to modulate the timing information in the initial eye diagram data using the total jitter timing offset sequence to generate a target eye diagram.

7. The electronic device according to claim 6, characterized in that, Also includes: The interaction module is configured for user input of deterministic jitter type and corresponding parameters, as well as statistical distribution type and distribution parameters of random jitter; wherein, the deterministic jitter type includes data-related jitter and periodic jitter; the data-related jitter includes inter-symbol interference jitter and duty cycle distortion jitter; and the statistical distribution type includes Gaussian distribution.

8. The electronic device according to claim 6 or 7, characterized in that, Also includes: The processing module is configured to acquire the target performance index of the target eye map, using the deterministic jitter parameter and the random jitter parameter as optimization variables; Using a pre-established performance prediction relationship, the predicted eye diagram performance is obtained based on the target channel parameters and the values ​​of the optimization variables. Through optimization search, the value of the optimization variable that minimizes the difference between the predicted eye diagram performance and the target performance index is found, and used as the combination of the deterministic jitter parameter and the random jitter parameter.

9. A storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by the processor, they implement the steps of the eye diagram generation method based on channel simulation as described in any one of claims 1-5.

10. An electronic device, further comprising: The method includes a memory, one or more processors, and a computer program stored in the memory, characterized in that the processor executes the computer program to implement the steps of the eye diagram generation method based on channel simulation as described in any one of claims 1-5.

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