A power device

Abstract

The application provides a power device, which comprises an active region, and the active region has a plurality of cell structures arranged in parallel. A single cell structure comprises a P-type substrate, an epitaxial layer, three trenches, a gate oxide layer, a polysilicon column, an N-type emitter region, an emitter metal layer and an insulating layer. The epitaxial layer is formed on the P-type substrate, and the epitaxial layer comprises an N-type epitaxial layer and a P-type body region formed on the top of the N-type epitaxial layer. The three trenches extend downward from the surface of the epitaxial layer into the N-type epitaxial layer, and the gate oxide layer is formed on the surface of the epitaxial layer and the wall surface of the trenches. The polysilicon filled in the three trenches forms three polysilicon columns, the middle polysilicon column is a real gate, and the two sides are false gates. The N-type emitter region is formed in the P-type body region and located on both sides of the top of the real gate, and the emitter metal layer is formed above the epitaxial layer, electrically connected with the N-type emitter region and the false gate, and insulated and separated from the real gate. The power device of the application can strengthen the charge balance effect, relieve the local electric field concentration, and reduce the conduction loss and on-state voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a power device. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite power device composed of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and BJT (Bipolar Junction Transistor). It has the advantages of high input impedance and low on-state voltage drop, and is suitable for high-voltage and high-current control scenarios, covering multiple high-growth markets such as photovoltaic power generation, electric vehicles, industrial frequency conversion, and charging piles.

[0003] However, in high-voltage systems, IGBTs need to withstand higher voltages and temperatures, increasing on-resistance and affecting long-term reliability. Especially in some IGBT structures, to reduce cell size, the spacing between gates may be closer, leading to more pronounced changes in charge density around the gates, poorer charge balance, and exacerbated charge concentration effects. This makes them more prone to electric field imbalance, significantly lowering the withstand voltage threshold and even causing breakdown. Furthermore, current technologies also increase manufacturing complexity when reducing cell size. Summary of the Invention

[0004] The purpose of this application is to provide a power device that can enhance charge balance, effectively alleviate the problem of local electric field concentration, thereby increasing the breakdown voltage of the device, reducing the possibility of leakage current, increasing the power density of the device, reducing conduction loss and on-state voltage, and improving the long-term operating reliability of the device in high voltage and high current scenarios.

[0005] This application provides a power device including an active region comprising multiple cell structures arranged in parallel in sequence. Each cell structure includes a P-type substrate, an epitaxial layer, three trenches, a gate oxide layer, a polysilicon pillar, an N-type emitter region, an emitter metal layer, and an insulating layer.

[0006] An epitaxial layer is formed on a P-type substrate; the epitaxial layer includes an N-type epitaxial layer and a P-type body region formed on top of the N-type epitaxial layer. Three trenches extend downward from the surface of the epitaxial layer into the N-type epitaxial layer, and gate oxide layers are formed on the surface of the epitaxial layer and the walls of the trenches. Polysilicon is filled in the three trenches to form three polysilicon pillars, with the middle polysilicon pillar serving as the true gate and the polysilicon pillars on either side of the middle polysilicon pillar serving as dummy gates.

[0007] The N-type emitter region is formed in the P-type body region and is located on both sides of the top of the true gate. The emitter metal layer is formed on top of the epitaxial layer and is electrically connected to the N-type emitter region and the dummy gate. It is insulated from the true gate by an insulating layer.

[0008] In one feasible approach, the two dummy gates on either side of the true gate are arranged symmetrically.

[0009] In one feasible embodiment, contact channels are provided in the insulating layers on both sides of the top of the true gate, extending to the surface of the P-type body region, and the emitter metal layer is electrically connected to the N-type emitter region through the contact channels.

[0010] In one feasible scheme, two adjacent cell structures are designated as a first cell structure and a second cell structure, respectively; the tops of adjacent dummy gates of the first cell structure and the second cell structure are electrically connected to the emitter metal layer through a common polysilicon layer.

[0011] In one feasible approach, a concave structure is provided on top of the co-connected polysilicon layer, and an emitter metal layer is filled into the concave structure to form an electrical connection with the co-connected polysilicon layer.

[0012] In one feasible approach, the bottom surfaces of the co-connected polysilicon layer at least partially cover the top surface of the dummy gate.

[0013] In one feasible embodiment, the insulating layer covers the sides of the co-connected polysilicon layer; or, the insulating layer covers the sides of the co-connected polysilicon layer and a portion of the top surface of the co-connected polysilicon layer.

[0014] In one feasible scheme, in two adjacent cell structures, the lateral spacing between adjacent dummy gates of the first cell structure and the second cell structure is L, where L = 1~8 μm.

[0015] In one feasible scheme, the lateral width of a single cell structure is M, where M = 1~20 μm.

[0016] In one feasible approach, the depth of the trench is H, where H = 3~10 μm.

[0017] In one feasible approach, the concentration of phosphorus-doped atoms in the N-type emitter region is 5 × 10⁻⁶. 12 ~8×10 12 pcs / cm 3 The concentration of boron doped atoms in the P-type body region is 2 × 10⁻⁶. 13 ~6×10 13 pcs / cm 3 .

[0018] In one feasible embodiment, the N-type epitaxial layer includes an N-type buffer layer and an N-type drift layer formed on the N-type buffer layer; the N-type buffer layer and the N-type drift layer have different doping concentrations.

[0019] In one feasible embodiment, the trench extends downward from the surface of the epitaxial layer into the N-type drift layer, with the bottom of the trench located below the P-type body region and above the N-type buffer layer.

[0020] Compared with the prior art, the beneficial effects of this application include at least the following: In the power device of this application, multiple cell structures are connected in parallel to form the active region. Each cell structure adopts a design combining a true gate and dummy gates arranged on both sides, which work together to optimize device performance. The true gate mainly undertakes the circuit switching control function, while the dummy gate plays an electric field balancing role through the field plate effect. This can suppress the charge concentration phenomenon generated when the true gate is working, avoid the imbalance of the surrounding electric field, help maintain the stability of the device's threshold voltage, and reduce the risk of local breakdown.

[0021] From the perspective of the working characteristics of a single cell structure, the dummy gates on both sides of the true gate exert an electric field coupling effect, which can more evenly disperse the charge distribution around the true gate, further enhance the charge balance effect, effectively alleviate the problem of local electric field concentration, thereby increasing the breakdown voltage (BV) of the device and reducing the possibility of leakage current.

[0022] From the perspective of the synergistic effect of adjacent cell structures, two adjacent true gates are spaced apart by two dummy gates. Compared with the design of a single dummy gate, the distance between the true gates can be reasonably increased, further weakening the charge concentration effect when the true gate is working, optimizing the overall electric field distribution, improving the stability of the device's withstand voltage threshold, and reducing the situation of reduced withstand voltage performance or premature breakdown caused by charge concentration.

[0023] Furthermore, the cell layout of the true gate and the dummy gates on both sides, combined with the structural design of the epitaxial layer and trench, can improve the power density of the device, reduce conduction losses and on-state voltage, and improve the long-term operational reliability of the device under high voltage and high current scenarios.

[0024] In a further embodiment, the emitter metal layer directly interacts with the adjacent dummy gates of two adjacent cells via a co-connected polysilicon layer. This is equivalent to using the entire top surface region or a portion of the top surface of the co-connected polysilicon layer as the electrical contact surface between the two adjacent dummy gates and the emitter metal layer. The co-connected polysilicon layer spans across the adjacent dummy gates, and its overall lateral width is significantly larger than that of a single dummy gate. Therefore, when creating contact holes in the insulating layer for electrical connection with the co-connected polysilicon layer, the lateral size of the contact holes can be relatively large. This significantly reduces the complexity of the manufacturing process, facilitates metal filling, and significantly reduces the risk of porosity, resistivity, and air breakdown.

[0025] Furthermore, since the emitter metal layer acts directly on two adjacent dummy gates through the co-connected polysilicon layer, the lateral spacing between the two adjacent dummy gates can be made smaller, which in turn reduces the lateral spacing of a single cell structure and helps to improve the cell density in power devices.

[0026] In this configuration, the tops of two adjacent dummy gates are electrically connected to the emitter metal layer through a common polysilicon layer. This is equivalent to increasing the adjustable range of the contact size between the emitter metal layer and the dummy gates through the common polysilicon layer, allowing those skilled in the art to adjust the spacing between two adjacent dummy gates within a larger lateral dimension range to meet different needs. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic cross-sectional view of the cellular structure of a power device as shown in an embodiment of this application.

[0029] Figure 2 This is a cross-sectional schematic diagram of a two-cell structure of a power device as shown in an embodiment of this application.

[0030] Figure 3 This is a partial structural diagram of two adjacent dummy gate locations shown in an embodiment of this application.

[0031] Figure 4 This is a schematic cross-sectional view of a power device with a collector metal layer as shown in an embodiment of this application.

[0032] In the figure: 10, cell structure; 101, first cell structure; 102, second cell structure; 1, P-type substrate; 2, epitaxial layer; 21, N-type buffer layer; 22, N-type drift layer; 23, P-type body region; 3, trench; 4, gate oxide layer; 5, polysilicon pillar; 51, true gate; 52, dummy gate; 521, co-connected polysilicon layer; 522, concave structure; 6, N-type emitter region; 7, emitter metal layer; 8, insulating layer; 81, contact channel; 9, collector metal layer. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] This embodiment provides a power device, which is an IGBT, including an active region with multiple sequentially connected parallel cell structures 10. The power device also includes a termination region located around the active region. The termination region's core function is to assist in optimizing the electric field distribution, mitigating electric field concentration at the edge of the active region, and avoiding the risk of voltage degradation or breakdown. This ensures the stable parallel operation of the multiple cell structures 10 in this embodiment. Those skilled in the art can configure the termination region according to conventional techniques; therefore, the specific structure of the termination region is not explained or limited in detail here.

[0036] In this embodiment, as Figure 1 As shown, the single cell structure 10 includes a P-type substrate 1, an epitaxial layer 2, three trenches 3, a gate oxide layer 4, a polysilicon pillar 5, an N-type emitter region 6, an emitter metal layer 7, and an insulating layer 8.

[0037] Epitaxial layer 2 is formed on P-type substrate 1; epitaxial layer 2 includes N-type epitaxial layer and P-type body region 23 formed on top of N-type epitaxial layer. Three trenches 3 extend downward from the surface of epitaxial layer 2 into N-type epitaxial layer, and gate oxide layer 4 is formed on the surface of epitaxial layer 2 and the walls of trenches 3.

[0038] Three polysilicon pillars 5 are formed by filling three trenches 3 with polysilicon. The middle polysilicon pillar is the true gate 51, and the polysilicon pillars on either side of the middle polysilicon pillar are dummy gates 52. An N-type emitter region 6 is formed in the P-type body region 23 and is located on both sides of the top of the true gate 51. An emitter metal layer 7 is formed above the epitaxial layer 2 and is electrically connected to the N-type emitter region 6 and the dummy gate 52. It is insulated from the true gate 51 by an insulating layer 8.

[0039] It should be noted that the cell structure 10 is defined as a repetitive functional unit, and the basis for division can be flexibly set by those skilled in the art, and is not intended as an absolute limitation on the technical solution.

[0040] It should also be noted that G, E, and C marked in the figure correspond to the three electrode ports of the device: G is the gate port, which is electrically connected to the true gate 51 and is used to input control signals; E is the emitter port, which is electrically connected to the emitter metal layer 7 and is the port from which current flows out of the device; C is the collector port, which is electrically connected to the P-type substrate 1 and is the port from which current flows into the device.

[0041] In the power device of this embodiment, multiple cell structures 10 are connected in parallel to form an active region. Each cell structure 10 adopts a design combining a true gate 51 and dummy gates 52 arranged on both sides. The two work together to optimize device performance. The true gate 51 mainly undertakes the circuit switching control function, while the dummy gates 52 play an electric field balancing role through the field plate effect. This can suppress the charge concentration phenomenon generated when the true gate 51 is working, avoid the imbalance of the surrounding electric field, help maintain the stability of the device's threshold voltage, and reduce the risk of local breakdown.

[0042] From the perspective of the working characteristics of a single cell structure 10, the dummy gates 52 on both sides of the true gate 51 exert an electric field coupling effect, which can more evenly disperse the charge distribution around the true gate 51, further enhance the charge balance effect, effectively alleviate the problem of local electric field concentration, thereby increasing the breakdown voltage (BV) of the device and reducing the possibility of leakage current generation.

[0043] From the perspective of the synergistic effect of adjacent cell structures 10, two adjacent true gates 51 are spaced apart by two dummy gates 52. Compared with the design of a single dummy gate, the distance between the true gates 51 can be reasonably increased, further weakening the charge concentration effect when the true gates 51 are working, optimizing the overall electric field distribution, improving the stability of the device's withstand voltage threshold, and reducing the situation of voltage performance degradation or premature breakdown caused by charge concentration.

[0044] In addition, the cell layout of the true gate 51 and the dummy gates 52 on both sides, together with the structural design of the epitaxial layer 2 and the trench 3, can improve the power density of the device, reduce conduction loss and on-state voltage, and improve the long-term reliability of the device in high voltage and high current scenarios.

[0045] In some embodiments, such as Figure 1 As shown, the two dummy gates 52 on both sides of the true gate 51 are arranged symmetrically. This design allows the dummy gates 52 on both sides of the true gate 51 to form a symmetrical electric field coupling effect, which can more evenly disperse the charge distribution around the true gate 51, further enhance the charge balance effect, effectively alleviate the problem of local electric field concentration, and thus be more conducive to improving the breakdown voltage (BV) of the device and reducing the possibility of leakage current.

[0046] In some embodiments, such as Figure 2 As shown, two adjacent cell structures 10 are respectively the first cell structure 101 and the second cell structure 102. The tops of the adjacent dummy gates 52 of the first cell structure 101 and the second cell structure 102 are electrically connected to the emitter metal layer 7 through a common polysilicon layer 521.

[0047] If the emitter metal layer 7 is connected to the dummy gate 52 through separate contact channels, the width of the contact hole opened in the insulating layer 8 will be very small if the emitter metal layer 7 is inserted into the polysilicon of a single dummy gate 52. This not only increases the difficulty of the process and is not conducive to metal filling, but also increases the risk of porosity, leading to increased resistivity. Under high voltage and high current operating conditions, this will cause concentrated heat generation.

[0048] In this embodiment, the emitter metal layer 7 directly acts on two adjacent dummy gates 52 through the co-connected polysilicon layer 521. This is equivalent to using the entire top surface region or a portion of the top surface region of the co-connected polysilicon layer 521 as the electrical contact surface between the two adjacent dummy gates 52 and the emitter metal layer 7. The co-connected polysilicon layer 521 spans across the adjacent dummy gates 52, and its overall lateral width is significantly larger than that of a single dummy gate 52. Therefore, when forming contact holes in the insulating layer 8 that are electrically connected to the co-connected polysilicon layer 521, the lateral size of the contact holes can be relatively larger. This significantly reduces the difficulty of the process, facilitates metal filling, and significantly reduces the risk of porosity, resistivity, and air breakdown.

[0049] Furthermore, since the emitter metal layer 7 directly acts on two adjacent dummy gates 52 through the co-connected polysilicon layer 521, the lateral spacing between the two adjacent dummy gates 52 can be made smaller, which in turn can reduce the lateral spacing of a single cell structure 10, thus helping to improve the cell density in power devices.

[0050] The tops of two adjacent dummy gates 52 are electrically connected to the emitter metal layer 7 through a common polysilicon layer 521. This is equivalent to increasing the adjustable range of the contact size between the emitter metal layer 7 and the dummy gates 52 through the common polysilicon layer 521, so that those skilled in the art can adjust the spacing between two adjacent dummy gates 52 within a larger lateral dimension range to meet different needs.

[0051] For example, in some embodiments, such as Figure 2 As shown, in two adjacent cell structures 10, the lateral spacing of the adjacent dummy gates 52 of the first cell structure 101 and the second cell structure 102 is L, which can optionally be 1~8um. For example, L=1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, etc.

[0052] In some embodiments, the top lateral width of the co-connected polysilicon layer 521 can be greater than or equal to twice the top lateral width of the dummy gate 52.

[0053] In some embodiments, such as Figure 2As shown, a concave structure 522 can be provided on the top of the co-connected polysilicon layer 521, and the emitter metal layer 7 is filled into the concave structure 522 to form an electrical connection with the co-connected polysilicon layer 521.

[0054] The concave structure 522 provided on the top of the co-connected polysilicon layer 521 can effectively increase the contact area between the emitter metal layer 7 and the co-connected polysilicon layer 521 when the emitter metal layer 7 is filled into the concave structure 522 to form an electrical connection, thereby improving the stability and reliability of the electrical connection.

[0055] In some embodiments, such as Figure 3 As shown, the top of the co-connected polysilicon layer 521 may not have a concave structure 522. For example, when the lateral spacing L between two adjacent dummy gates 52 is greater than a predetermined value L0, the top surface of the co-connected polysilicon layer 521 has sufficient area to form a stable electrical connection with the emitter metal layer 7, and in this case, the concave structure 522 may not be provided. Alternatively, if the lateral spacing L between two adjacent dummy gates 52 is less than or equal to the predetermined value L0, the top surface of the co-connected polysilicon layer 521 is relatively smaller, and in this case, a concave structure 522 can be provided to increase the contact area with the emitter metal layer 7, thereby improving connection stability and reliability. The predetermined value L0 can be 4~6µm, for example, 4µm, 4.5µm, 5µm, 5.5µm, 6µm, etc. In a preferred embodiment, regardless of the size of the lateral spacing L between two adjacent dummy gates 52, the concave structure 522 is preferentially provided on the top surface of the co-connected polysilicon layer 521.

[0056] In some embodiments, such as Figure 2 and Figure 3 As shown, the bottom surfaces of the co-connected polysilicon layer 521 at least partially cover the top surfaces of the dummy gate 52. It should be noted that the co-connected polysilicon layer 521, the true gate 51, and the dummy gate 52 are formed in the same process, and the partial top surfaces of the dummy gate 52 covering the bottom surfaces of the co-connected polysilicon layer 521 are formed by a material removal process.

[0057] In some embodiments, the insulating layer 8 covers the sides of the co-connected polysilicon layer 521. Or as... Figure 2 and Figure 3 As shown, the insulating layer 8 covers the side surface of the co-connected polysilicon layer 521 and part of the top surface of the co-connected polysilicon layer 521.

[0058] In some embodiments, such as Figure 2 As shown, the lateral width of a single cell structure 10 is M, which can optionally be 1~20um. For example, M=3um, 5um, 8um, 10um, 13um, 15um, 18um, 20um, etc.

[0059] In some embodiments, such as Figure 2As shown, the depth of trench 3 is H, which can optionally be 3~10um. For example, H=3um, 5um, 8um, 10um, etc.

[0060] It should be noted that those skilled in the art can design and adjust the spacing and depth of the dummy gate 52 as needed, thereby adjusting the hole density around the trench to reduce conduction losses and adjust the on-state voltage (Vcesat).

[0061] In some embodiments, such as Figure 1 As shown, contact channels 81 are provided in the insulating layers 8 on both sides of the top of the true gate 51. The contact channels 81 extend to the surface of the P-type body region 23, and the emitter metal layer 7 is electrically connected to the N-type emitter region 6 through the contact channels 81.

[0062] In some embodiments, optionally, the concentration of phosphorus doped in the N-type emitter region 6 is 5 × 10⁻⁶. 12 ~8×10 12 pcs / cm 3 The concentration of boron doped atoms in the P-type body region 23 is 2 × 10⁻⁶. 13 ~6×10 13 pcs / cm 3 .

[0063] In some embodiments, such as Figure 1 , Figure 2 and Figure 3 As shown, the N-type epitaxial layer includes an N-type buffer layer 21 and an N-type drift layer 22 formed on the N-type buffer layer 21; the doping concentrations of the N-type buffer layer 21 and the N-type drift layer 22 are different.

[0064] The N-type drift layer 22 serves to withstand voltage, while the N-type buffer layer 21 is responsible for cutting off the electric field, consuming holes, reducing the thickness of the N-type drift layer 22, and improving the switching speed. The dual N-type epitaxial layers have different doping rates, which can be adjusted as needed. Furthermore, the trench 3 extends downwards from the surface of the epitaxial layer 2 into the N-type drift layer 22. The bottom of the trench 3 is located below the P-type body region 23 and above the N-type buffer layer 21, but does not extend into the N-type buffer layer 21, which makes the electric field more stable and the withstand voltage more stable.

[0065] In some embodiments, such as Figure 4 As shown, the power device also includes a collector metal layer 9, which is disposed on the back side of the P-type substrate 1.

[0066] The above description is only a partial embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power device, comprising an active region, said active region comprising a plurality of sequentially arranged parallel cell structures (10); characterized in that, A single cell structure (10) includes: P-type substrate (1); An epitaxial layer (2) is formed on the P-type substrate (1); the epitaxial layer (2) includes an N-type epitaxial layer and a P-type body region (23) formed on top of the N-type epitaxial layer. Three trenches (3) extend downward from the surface of the epitaxial layer (2) into the N-type epitaxial layer; A gate oxide layer (4) is formed on the surface of the epitaxial layer (2) and the wall of the trench (3); Polysilicon pillars (5) are formed by filling polysilicon in the three trenches (3), with the middle polysilicon pillar being the true gate (51) and the polysilicon pillars on both sides of the middle polysilicon pillar being the false gates (52). The N-type emitter region (6) is formed in the P-type body region (23) and located on both sides of the top of the true gate (51); An emitter metal layer (7) is formed above the epitaxial layer (2), electrically connected to the N-type emitter region (6) and the dummy gate (52), and is insulated from the real gate (51) by an insulating layer (8); The two adjacent cell structures (10) are respectively the first cell structure (101) and the second cell structure (102); the top of the adjacent dummy gate (52) of the first cell structure (101) and the second cell structure (102) is electrically connected to the emitter metal layer (7) through a common polysilicon layer (521); The top surface lateral width of the co-connected polysilicon layer (521) is greater than or equal to twice the top surface lateral width of the dummy gate (52); A concave structure (522) is provided on the top of the co-connected polysilicon layer (521), and the emitter metal layer (7) is filled into the concave structure (522) to form an electrical connection with the co-connected polysilicon layer (521); The bottom surfaces of the co-connected polysilicon layer (521) cover a portion of the top surface of the dummy gate (52); The lateral spacing between the adjacent dummy gates (52) of the first cell structure (101) and the second cell structure (102) is L, where L is less than or equal to a predetermined value L0, and the predetermined value L0 is 4um to 6um.

2. The power device according to claim 1, characterized in that, The two dummy gates (52) on both sides of the true gate (51) are arranged symmetrically.

3. The power device according to claim 1, characterized in that, Contact channels (81) are provided in the insulating layer (8) on both sides of the top of the true gate (51). The contact channels (81) extend to the surface of the P-type body region (23). The emitter metal layer (7) is electrically connected to the N-type emitter region (6) through the contact channels (81).

4. The power device according to claim 1, characterized in that, The insulating layer (8) covers the sides of the co-connected polysilicon layer (521); or, The insulating layer (8) covers the side surface of the co-connected polysilicon layer (521) and part of the top surface of the co-connected polysilicon layer (521).

5. The power device according to claim 1, characterized in that, The lateral width of a single cell structure (10) is M, where M = 1~20 μm.

6. The power device according to claim 1, characterized in that, The depth of the trench (3) is H, where H = 3~10 μm.

7. The power device according to claim 1, characterized in that, The concentration of phosphorus atoms doped in the N-type emitter region (6) is 5 × 10⁻⁶. 12 ~8×10 12 pcs / cm 3 The concentration of boron doped atoms in the P-type body region (23) is 2 × 10⁻⁶. 13 ~6×10 13 pcs / cm 3 .

8. The power device according to claim 1, characterized in that, The N-type epitaxial layer includes an N-type buffer layer (21) and an N-type drift layer (22) formed on the N-type buffer layer (21). The doping concentration of the N-type buffer layer (21) is different from that of the N-type drift layer (22).

9. The power device according to claim 8, characterized in that, The trench (3) extends downward from the surface of the epitaxial layer (2) into the N-type drift layer (22), and the bottom of the trench (3) is below the P-type body region (23) and above the N-type buffer layer (21).

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