Narrowband signal receiving system and method

Abstract

The invention relates to the technical field of semiconductor radio frequency signal processing, and discloses a narrowband signal receiving system and method, and the system comprises a coarse frequency offset value capturing module, a carrier phase locking module, a digital domain carrier tracking module, a timing synchronization and multipath correction module, and a vector amplitude phase correction and equalization module. In the prior art, the technical problems of lock losing, judgment errors and high bit error rate caused by serious multipath interference and frequency offset drifting of narrow-band signals are difficult to solve in complex environments with multipath effect and high frequency offset, such as urban canyons, basements and warehouses. According to the invention, by introducing analog phase locking, digital fine tuning, dual-correlation symbol synchronization based on multi-path sensing and vector amplitude-phase combined compensation overall architecture with cooperation of analog and digital, the problems of synchronization failure and demodulation performance reduction caused by multi-path distortion in the prior art are avoided; and the sensitivity and the overall reliability of radio frequency signal receiving are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor radio frequency signal processing, and in particular to a narrowband signal receiving system and method. BACKGROUND

[0002] At present, ultra-narrowband wireless communication technologies such as narrowband Internet of Things have been widely applied in low-power and large-coverage scenarios such as smart cities, industrial automation, warehouse logistics, underground meter reading, and energy monitoring. However, in complex environments such as urban canyons, underground parking lots, subway tunnels, factories, and warehouses, radio frequency signal reception faces severe challenges. In complex environments, there are a large number of buildings, walls, metal reflectors, and other obstacles, which cause significant multipath effects of signals, form multiple delay components superimposed at the receiving end, and further cause inter-symbol interference and random phase drift of the carrier. In addition, the signal power of NB-IoT is extremely low, and once in a long-distance or through-wall coverage scenario, the signal strength is further attenuated, making the receiver face the severe condition of extremely low signal-to-noise ratio, and the traditional single phase-locked loop or fixed bandwidth Costas loop often fails to quickly capture and track large frequency offsets.

[0003] In the prior art, in order to ensure the stability of carrier recovery, the loop filter is usually designed to be narrow to suppress phase noise; but a too narrow bandwidth will significantly reduce the frequency tracking capability, causing the phase-locked loop to fail to adjust in time in the dynamic frequency offset or multipath fast fading scenario. On the contrary, if the loop bandwidth is increased to improve the frequency offset tolerance, more phase jitter will be introduced, causing the demodulation error vector magnitude to rise, and ultimately the bit error rate performance to deteriorate. Some existing improvement schemes attempt to introduce a digital equalizer or an adaptive filter to alleviate multipath interference, but complete reliance on back-end digital processing will lead to increased power consumption at the FPGA or DSP end, and when real-time requirements are high, it is difficult to cope with instantaneous phase flicker or rapid channel changes, especially in the case of limited power budget for NB-IoT nodes. Therefore, there is an urgent need for a narrowband signal receiving method that can achieve high-precision carrier phase recovery, symbol timing synchronization, and multipath suppression to improve the overall demodulation robustness, coverage capability, and long-term stability of the system. SUMMARY

[0004] In view of the above technical deficiencies, the purpose of the present application is to provide a narrowband signal receiving system and method, which aims to solve the technical problems of loss of lock, decision error, and high bit error rate caused by severe multipath interference and frequency offset drift of narrowband signals in complex environments such as urban canyons, basements, and warehouses.

[0005] To solve the above technical problems, the present application adopts the following technical scheme: the present application provides a narrowband signal receiving system,

[0006] The receiving system of the narrowband signal comprises:

[0007] A coarse frequency offset value acquisition module is configured to acquire a first radio frequency narrowband signal, amplify the first radio frequency narrowband signal to obtain a second radio frequency narrowband signal, perform down-conversion processing on the second radio frequency narrowband signal by using a local oscillator mixing method to obtain a down-converted signal and a baseband signal, perform sliding autocorrelation detection on the down-converted signal after sampling by using an ADC, determine a synchronization sequence starting point, and extract a preliminary frequency offset estimation value f based on the synchronization sequence starting point.

[0008] A carrier phase locking module is configured to determine a frequency offset pre-compensation value based on the preliminary frequency offset estimation value f, apply the frequency offset pre-compensation value, start an analog phase-locked loop control network PLL to enter a locking stage, and output a phase error and a locked carrier phase.

[0009] A digital domain carrier tracking module is configured to perform digital fine carrier tracking processing on the baseband signal by using a digital domain Costas loop tracking method based on the locked carrier phase, extract an instantaneous phase deviation estimation value, and perform a numerically controlled oscillator compensation on the baseband signal based on the instantaneous phase deviation estimation value to obtain a carrier phase stable signal.

[0010] A timing synchronization and multipath correction module is configured to perform error detection and synchronization compensation of symbol timing by using a multipath-aware double-correlation synchronization method based on the carrier phase stable signal to obtain a timing-aligned synchronization symbol signal.

[0011] A vector amplitude and phase correction and equalization module is configured to perform joint compensation on amplitude and phase vectors by using an analog vector amplitude and phase correction and a digital complex equalization method based on the synchronization symbol signal to obtain a final equalization output signal.

[0012] Preferably, in the carrier phase locking module, the step of starting the analog phase-locked loop control network PLL to enter the locking stage and outputting the phase error and the locked carrier phase specifically comprises: the analog phase-locked loop control network PLL comprises a phase discriminator layer, a second-order loop filter layer, and a voltage-controlled oscillator layer; the analog phase-locked loop control network PLL outputs the phase error through the phase discriminator layer, regulates the phase error by using the second-order loop filter layer, and simultaneously outputs a voltage-controlled voltage acting on the voltage-controlled oscillator layer; when the phase error is lower than a preset phase error threshold value, the locked carrier phase is obtained.

[0013] Preferably, in the carrier phase locking module, the determination of the phase error is achieved by using a Costas phase discriminator decision formula, and in the locking process of the phase error, the equivalent noise bandwidth existing in the analog phase-locked loop control network PLL is dynamically adjusted according to the mean square estimation value of the phase error.

[0014] Preferably, in the digital domain carrier tracking module, the phase error is monitored in the mean square during the compensation of the numerically controlled oscillator compensation of the baseband signal, and when the mean square value obtained by the mean square monitoring exceeds a preset phase deviation threshold, an adaptive adjustment strategy is triggered to automatically restart the lock loss fast recapture processing of the analog phase-locked loop control network PLL in step S20.

[0015] Preferably, in the digital domain carrier tracking module, the digital fine carrier tracking processing includes: constructing an error detection function , for the baseband signal, where n is the sampling serial number in the current symbol period; is the phase deviation estimation value corresponding to the n th sampling serial number; is the in-phase component of the received baseband signal; is the quadrature component of the received baseband signal; is the sign function, used to extract the positive and negative sign information of the input value; and the error detection function is window-averaged to output the instantaneous phase deviation estimation value.

[0016] Preferably, in the timing synchronization and multipath correction module, the multipath-aware double-correlation synchronization method specifically includes: obtaining early sampling data E, late sampling data L and on-time sampling data P of the carrier phase stable signal, and constructing a timing error function , , for the early sampling data E, the late sampling data L and the on-time sampling data P; the sign function is used; the short-interval correlation result and the wide-interval correlation result are calculated in parallel, and when the two results are inconsistent, it is judged that there is multipath interference, and the symbol timing phase compensation amount is dynamically adjusted through the synchronization sampling point method to align the sampling point to the main path maximum energy peak position.

[0017] Preferably, in the vector amplitude and phase correction and equalization module, the analog vector amplitude and phase correction specifically includes: finely adjusting the input and output branch amplitude and phase by using the vector modulator integrated in the analog radio frequency front end to realize the front-end analog pre-correction; the digital complex equalization specifically includes: calculating a channel gain estimation value based on the pilot symbol, and introducing the channel gain estimation value to the subsequent data symbol to realize the back-end digital flattening processing.

[0018] The application also provides a narrowband signal receiving method, which includes:

[0019] Step S10: acquire a first radio frequency narrow band signal, and perform low noise amplification on the first radio frequency narrow band signal to obtain a second radio frequency narrow band signal; and utilize a local oscillator mixing method to perform down conversion processing on the second radio frequency narrow band signal to obtain a down conversion signal and a baseband signal, perform sliding autocorrelation detection after the down conversion signal is sampled by an ADC, and determine a synchronization sequence starting point; based on the synchronization sequence starting point, a normalized phase correlation method is used to extract a preliminary frequency offset estimation value f;

[0020] Step S20: determine a frequency offset pre-compensation value based on the preliminary frequency offset estimation value f, apply the frequency offset pre-compensation value, start an analog phase-locked loop control network PLL to enter a locking stage, and output a phase error and a locked carrier phase;

[0021] Step S30: based on the locked carrier phase, a digital domain Costas loop tracking method is used to perform digital fine carrier tracking processing on the baseband signal, an instantaneous phase deviation estimation value is extracted, and a numerically controlled oscillator is compensated based on the instantaneous phase deviation estimation value to obtain a carrier phase stable signal;

[0022] Step S40: based on the carrier phase stable signal, a multipath perception double correlation synchronization method is used to perform error detection and synchronization compensation of symbol timing to obtain a timing aligned synchronization symbol signal;

[0023] Step S50: based on the synchronization symbol signal, an analog vector amplitude and phase correction and a digital complex equalization method are used to jointly compensate the amplitude and phase vector to obtain a final equalization output signal.

[0024] The application further provides a narrow band signal receiving device, comprising a memory, a processor, and a narrow band signal receiving program stored on the memory and executable on the processor, wherein the narrow band signal receiving program is implemented when the processor is executed to realize the narrow band signal receiving method.

[0025] The application further provides a computer program product comprising a narrow band signal receiving program, wherein the narrow band signal receiving program is implemented when the processor is executed to realize the narrow band signal receiving method.

[0026] The application has the beneficial effect that, compared with the prior art, in the complex environment of urban canyons, basements, warehouses and the like, the technical problem of loss of lock, decision error and high bit error rate caused by serious multipath interference and frequency offset drift of narrow band signals is difficult to solve, and the application introduces an overall architecture of analog phase-locked loop, digital fine tuning, double correlation symbol synchronization based on multipath perception, and analog and digital collaborative vector amplitude and phase joint compensation, avoids the problems of synchronization failure and demodulation performance degradation caused by multipath distortion in traditional technologies, and significantly improves the sensitivity and overall reliability of radio frequency signal reception. BRIEF DESCRIPTION OF DRAWINGS

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a first embodiment of a narrowband signal receiving system according to the present invention.

[0029] Figure 2 This is a schematic diagram of a narrowband signal receiving system according to the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1: As Figure 1 The diagram shown is a flowchart of the first embodiment of the narrowband signal receiving system of the present invention, which presents the first embodiment of the narrowband signal receiving system of the present invention.

[0032] In the first embodiment, the narrowband signal receiving system includes:

[0033] A coarse frequency offset acquisition module is used to acquire a first RF narrowband signal and amplify it with low noise to obtain a second RF narrowband signal. The second RF narrowband signal is then down-converted using a local oscillator mixing method to obtain a down-converted signal and a baseband signal. The down-converted signal is sampled by an ADC and then subjected to sliding autocorrelation detection to determine the starting point of the synchronization sequence. Based on the starting point of the synchronization sequence, a preliminary frequency offset estimate f is extracted using a normalized phase correlation method.

[0034] It should be noted that the local oscillator mixing method refers to using the local oscillator (LO) integrated in the RF front-end to shift the RF signal frequency to the intermediate frequency or baseband frequency band through a mixer. Specifically, it includes configuring a variable frequency local oscillator, designing a bandwidth matching filter, and a phase noise optimization circuit to ensure that the main signal components can still be correctly captured in multipath and large frequency offset scenarios. The normalized phase correlation method refers to further reducing the impact of noise on the phase estimation offset by normalizing the denominator energy on the basis of sliding autocorrelation detection. This includes calculating the ratio of the autocorrelation peak amplitude to the energy standard deviation, thereby improving the stability and accuracy of frequency offset estimation.

[0035] Understandably, the traditional autocorrelation method commonly used in existing technologies can produce multiple spurious peaks or even distortions in the correlation peak when encountering low signal-to-noise ratio, strong multipath fading, or frequency drift, leading to incorrect determination of the starting point. At the same time, the unnormalized autocorrelation method is easily affected by random amplitude fluctuations, resulting in deviations in the frequency offset estimate, and frequent loss of lock-in or tracking instability in the subsequent phase-locking process.

[0036] It should be understood that, compared to existing technologies, the normalized phase correlation method proposed in this invention introduces a sliding adaptive energy normalization coefficient in multipath and large frequency offset environments to automatically suppress the energy of the secondary path and the noise baseline, thereby reducing the volatility of frequency offset estimation and the probability of false synchronization. In traditional technologies, frequency offset estimation often suffers from the problem of bias accumulation, especially when the signal-to-noise ratio is below -110dBm, the frequency offset is greater than 1kHz, and the relative delay of the multipath exceeds 0.3 symbol periods, the probability of phase-locked loop failure exceeds 35%. However, this invention, by introducing energy normalization and dynamic weight correction, significantly suppresses the frequency offset estimation bias, reducing the probability of phase-locked loop failure to less than 5%. In addition, traditional technologies cannot dynamically adjust the reference energy according to channel conditions, resulting in a high false alarm rate of autocorrelation peak. This manifests as the correlator still incorrectly selecting the starting point of the secondary path even when the amplitude of a secondary path is only 3dB lower than that of the primary path. This invention effectively distinguishes between secondary and primary path peaks by normalizing and standardizing the energy within each sliding window and combining this with phase drift information. Even if the secondary path power is only 2dB lower than the primary path power, it can still correctly lock the primary path peak, achieving higher-precision synchronization. Based on test results in actual NB-IoT systems, under conditions of low signal-to-noise ratio (SNR=-12dB), initial frequency offset of approximately ±1.5kHz, and a maximum relative delay of 0.5 symbol periods for multipath propagation, this invention reduces the overall mean square error of frequency offset estimation (MSE) from the traditional 210Hz² to 65Hz², the carrier phase error from the traditional 7° to approximately 2°, the symbol synchronization offset from 0.15 symbol periods to 0.02 symbol periods, and the bit error rate (BER) is improved by more than 35%, demonstrating the technical advantages of this invention in complex scenarios.

[0037] The carrier phase locking module is used to determine the frequency offset pre-compensation value based on the preliminary frequency offset estimate f, apply the frequency offset pre-compensation value, and start the analog phase-locked loop control network PLL to enter the locking phase, outputting the phase error and locking the carrier phase;

[0038] It should be noted that the carrier phase-locked loop (PLL) module, which initiates the analog PLL control network into the locking phase, outputs the phase error, and locks the carrier phase, specifically includes the following steps: The analog PLL control network comprises a phase detector layer, a second-order loop filter layer, and a voltage-controlled oscillator (VCO) layer. The PLL outputs the phase error through the phase detector layer, which is then adjusted by the second-order loop filter layer. Simultaneously, a voltage-controlled voltage is applied to the VCO layer. When the phase error is lower than a preset phase error threshold, the carrier phase is locked. The phase error is determined using a Costas phase detector decision formula. During the phase error locking process, the equivalent noise bandwidth in the analog PLL control network is dynamically adjusted based on the mean square estimate of the phase error.

[0039] Understandably, traditional carrier phase-locked loop (PLL) technology often uses a fixed-bandwidth loop filter, which cannot adaptively cope with different frequency offsets and phase drifts. When encountering large frequency offsets (above 1kHz) or severe phase fluctuations due to multipath superposition, the phase-locking time is long, or even leads to loss of lock, which seriously affects subsequent digital carrier tracking and symbol synchronization. At the same time, the fixed bandwidth will lead to increased phase jitter under low signal-to-noise ratio, reducing receiver sensitivity.

[0040] It should be understood that, compared to existing technologies, this invention introduces an adaptive equivalent noise bandwidth adjustment mechanism based on the mean square estimate of the phase error during the phase error locking process. When a large mean square value of the phase error is detected (e.g., during the initialization phase), the equivalent bandwidth of the loop filter is automatically widened (e.g., to 500Hz) to accelerate the frequency offset acquisition speed. When the mean square value of the error converges to a smaller range (e.g., less than 0.05 rad²), the bandwidth is automatically reduced (e.g., to 20Hz) to reduce phase jitter and improve steady-state tracking accuracy. This adaptive bandwidth mechanism shortens the phase-locking time by approximately 40% and reduces the steady-state phase error by approximately 60%, making it particularly suitable for the rapid convergence and robust tracking requirements of narrowband systems such as NB-IoT in high dynamic frequency offset environments, significantly improving overall robustness.

[0041] The digital domain carrier tracking module is used to perform digital fine carrier tracking processing on the baseband signal based on the locked carrier phase using the digital domain Costas loop tracking method, extract the instantaneous phase deviation estimate, and perform numerically controlled oscillator compensation on the baseband signal based on the instantaneous phase deviation estimate to obtain a carrier phase stable signal;

[0042] It should be noted that the compensation process for the baseband signal using a digitally controlled oscillator also includes mean square monitoring of the phase error. When the mean square value obtained from the mean square monitoring exceeds a preset phase deviation threshold, an adaptive adjustment strategy is triggered, automatically restarting the analog phase-locked loop (PLL) control network in step S20 for fast re-acquisition after lock-out. Digital fine carrier tracking processing includes: constructing an error detection function for the baseband signal. , Where n is the sampling sequence number within the current symbol period; This is the estimated phase deviation value corresponding to the nth sampling sequence number at that instant; To receive the in-phase component of the baseband signal; To receive the quadrature components of the baseband signal; This is a sign function used to extract the positive or negative sign information of the input value; and it is used for the error detection function. Perform window averaging to output the instantaneous phase deviation estimate.

[0043] It should be noted that the vector amplitude and phase correction and equalization module is not only designed to compensate for single scenarios or static hardware imbalances, but also addresses the multi-dimensional signal distortion problems that occur in low-power, narrowband communication systems such as NB-IoT under complex dynamic channels. It employs a multi-level, dynamically adaptive vector amplitude and phase comprehensive compensation strategy. This module fully utilizes the analog vector modulator of the RF front-end to synchronously adjust the amplitude and phase of the input in-phase (I) and quadrature (Q) signals. By monitoring real-time amplitude and phase drift results in different paths and time windows, it dynamically generates targeted compensation commands, thereby correcting most static or slowly varying amplitude and phase shifts in the analog domain. This is particularly suitable for compensating for nonlinear mismatch problems caused by RF hardware aging, temperature drift, and RF switching. This module does not rely entirely on single analog compensation but is deeply coupled with the back-end digital complex equalization method. The digital complex equalization section performs channel estimation using pilot symbols, decision feedback, or a set of reference pilots to obtain the equivalent complex gain for each subcarrier or symbol. Based on the estimation results, it outputs dynamic correction coefficients for residual imbalance, enabling fine-tuning compensation for rapid burst phase rotation, small-amplitude rapid fading, and short-term random channel disturbances. This dual-domain collaborative mechanism of analog coarse compensation and digital fine-tuning effectively minimizes dynamic errors in the analog hardware, while reducing the computational burden of digital domain equalization, lowering overall power consumption and computational complexity. The analog vector amplitude and phase correction section employs a hardware-level fast closed-loop feedback architecture, communicating in real-time with the monitoring module in the FPGA or DSP. Once an amplitude deviation exceeding approximately 0.5 dB or a phase deviation exceeding approximately 3° is detected in the analog domain, the system immediately initiates a fast analog compensation command, ensuring that the signal amplitude and phase are close to ideal before entering the ADC. This design not only optimizes the dynamic range utilization of the analog signal but also significantly reduces the accumulation of ADC quantization errors, helping to maintain a high signal-to-noise ratio for the entire link, especially suitable for reception requirements under extremely weak signal conditions (e.g., -120 dBm or even lower). The digital complex equalization section employs adaptive update algorithms with different phase lengths and modes during the compensation process, such as Least Mean Square (LMS), Recursive Least Squares (RLS), or Decision-Guided Feedback (DFE), to further refine and stabilize the compensation effect. When the digital equalization detects abnormal abrupt changes (such as sudden phase jitter or rapid multipath switching), it simultaneously triggers a secondary correction request for the analog correction parameters, forming an end-to-end, multi-stage, multi-timescale adaptive compensation closed-loop mechanism to maximize the amplitude and phase consistency of the received signal and the overall robustness of the system. Furthermore, to meet the requirements of NB-IoT systems for ultra-low power consumption and ultra-high stability, both analog correction and digital equalization have power consumption awareness mechanisms. When high channel stability or a persistently low compensation amplitude is detected, they automatically enter a low-power hold-up state, retaining only the monitoring logic to further reduce unnecessary energy consumption.This on-demand operating mechanism, which combines hardware and algorithm optimizations, can significantly extend the battery life of terminal devices, making it particularly suitable for remote NB-IoT nodes designed for a lifespan of 10 years or more.

[0044] Understandably, traditional symbol synchronization schemes are typically based on fixed-interval early and late gate methods or use fixed oversampling differential algorithms for timing adjustments. In strong multipath environments, they are easily misled by the high instantaneous energy peaks of secondary paths, leading to symbol timing point offsets and accumulated decision errors. Furthermore, traditional schemes do not fully consider the amplitude and relative delay differences of different delay paths. Especially in complex reflection scenarios such as warehouses, basements, or indoor spaces, the main path signal is often masked by multiple secondary path signals of similar intensity. Traditional schemes can hardly accurately align to the main path energy peak, resulting in frequent demodulation errors and decision drift.

[0045] It should be understood that, compared to existing technologies, this invention, by introducing a multipath sensing dual-correlation mechanism, can not only actively sense secondary path interference but also perform targeted forward or backward fine-tuning of synchronization sampling points to achieve dynamic real-time timing correction. This mechanism can maintain accurate locking of the main path energy peak even in extreme scenarios with extremely low signal-to-noise ratios and multipath relative delays exceeding 0.3 symbol periods, effectively suppressing symbol timing drift and decision errors induced by secondary paths. Practice shows that the solution of this invention can control the symbol synchronization offset rate to less than 0.01 symbol periods, and the long-term symbol drift probability is essentially close to zero, greatly improving demodulation performance and link stability, making it particularly suitable for reliable reception requirements of NB-IoT in indoor long-range coverage, underground manhole covers, or complex industrial scenarios.

[0046] For example, in an NB-IoT experiment conducted in an underground parking lot environment, three distinct secondary path signals existed in the test environment. The power difference between the primary path signal and the secondary path signals was only about 3 dB, and the maximum relative delay was about 0.4 symbol periods. Using the traditional single early and late gate timing method, the symbol timing offset rate exceeded 0.1 symbol periods, resulting in an error decision rate exceeding 5% and a link failure probability as high as 9%. However, using the multipath sensing dual correlation synchronization method of this invention, under the same environment, the symbol timing offset rate was suppressed to within 0.007 symbol periods, the error decision rate was significantly reduced to about 1%, and the link continuous availability reached 99.7%. This completely avoided the misalignment problem induced by multipath secondary peaks, effectively verifying the superior performance of this solution.

[0047] The timing synchronization and multipath correction module is used to perform error detection and synchronization compensation for symbol timing based on the carrier phase stable signal using the multipath sensing dual correlation synchronization method, so as to obtain a timing-aligned synchronization symbol signal.

[0048] It should be noted that the multipath sensing dual-correlation synchronization method specifically includes: acquiring the advance sampled data E, the delayed sampled data L, and the timely sampled data P of the carrier phase-stabilized signal, and constructing a timing error function based on the advance sampled data E, the delayed sampled data L, and the timely sampled data P. , , The symbol function is used; the short-interval correlation results and wide-interval correlation results are calculated in parallel. When the two results are inconsistent, it is determined that there is multipath interference. The symbol timing phase compensation is dynamically adjusted by means of synchronous sampling points to make the sampling points align with the position of the maximum energy peak of the main path.

[0049] It should be noted that the multipath sensing dual-correlation synchronization method, in the process of performing symbol timing compensation, does not rely solely on a single timing error value. Instead, it achieves real-time sensing and discrimination of multipath signal characteristics by parallel calculation of short-interval and wide-interval correlation results. When a shift in the short-interval correlation result is detected while the wide-interval correlation result remains stable, the system determines it to be a scenario of decreased energy in the main path or transient enhancement in the secondary path. If both shift simultaneously, the system further analyzes the power ratio and delay characteristics between paths to dynamically determine the symbol timing phase compensation amount. This accurately adjusts the sampling point to the time position corresponding to the maximum energy peak of the main path, avoiding decision errors and synchronization drift caused by the secondary path.

[0050] Understandably, traditional symbol synchronization schemes often rely on fixed windows or a single early / late gate differential strategy, failing to proactively detect instantaneous changes in multipath channels. Especially when high-amplitude secondary paths exist, they are prone to misinterpreting the transient peaks of the secondary paths as the main path, leading to symbol timing offsets or even locking onto incorrect path energy peaks, severely impacting symbol demodulation accuracy. Furthermore, fixed strategies lack dynamic adaptability, are insensitive to different scenarios and time-varying channels, cannot automatically adjust compensation amounts, and cannot quickly self-recover from transient interference.

[0051] It should be understood that, compared to existing technologies, the multipath sensing dual-correlation synchronization method of this invention introduces a parallel multi-scale correlation discrimination mechanism, which can correct the synchronization sampling point position in real time to address the rapid changes in secondary path energy under complex reflection scenarios. By dynamically adjusting the symbol timing phase compensation, it can still ensure symbol timing alignment with the main path signal under extremely low signal-to-noise ratio conditions, completely suppressing the cumulative error of secondary path interference and improving the long-term stability of symbol decision. This invention's method can maintain a timing accuracy of over 99.5% and a near-zero symbol synchronization drift probability even under weak signal conditions with a multipath relative delay of 0.5 symbol periods and a signal power of only -120dBm, effectively improving reception robustness and overall system stability.

[0052] For example, in a set of NB-IoT downlink reception tests in an industrial warehousing environment, the scenario has two secondary paths with power differences of 3dB and 6dB relative to the primary path, respectively, and a maximum relative delay of approximately 0.45 symbol periods. Using a traditional fixed-window synchronization scheme, the symbol timing offset is approximately 0.09 symbol periods, resulting in a demodulation bit error rate of approximately 3.7 × 10⁻⁶. -3 The link recovery process is frequent and the probability of frame loss is high. However, by using the multipath sensing dual-correlation synchronization method of this invention, the symbol timing offset rate is controlled to within 0.006 symbol periods, and the demodulation bit error rate is reduced to 1.2 × 10⁻⁶. -3 The link availability was improved to 99.8%, and no frame loss occurred throughout the process, verifying the significant performance advantages and continuous demodulation reliability of the method of the present invention in complex multipath environments.

[0053] The vector amplitude and phase correction and equalization module is used to perform joint compensation of amplitude and phase vectors based on the synchronous symbol signal using analog vector amplitude and phase correction and digital complex equalization to obtain the final equalized output signal.

[0054] It should be noted that the vector amplitude and phase correction and equalization module adopts a combination of analog vector amplitude and phase correction and digital complex equalization to achieve comprehensive compensation for amplitude and phase distortion in the synchronization symbol signal. Specifically, the analog vector amplitude and phase correction first uses a programmable vector modulator integrated in the RF front end to perform real-time fine-grained adjustment of the amplitude and phase of the received I / Q components. This modulator achieves phase correction accurate to the sub-degree (less than 1°) level and amplitude compensation at the 0.1dB level based on the baseband control signal, thereby minimizing the imbalance and dynamic drift introduced by the analog domain. On this basis, the digital complex equalization method further performs complex channel compensation on the signal within the FPGA or digital baseband processor. Based on the overall amplitude and phase response characteristics of the channel estimated by the pilot symbol or decision feedback symbol, the equivalent complex equalization coefficient is calculated, and the amplitude and phase are adjusted symbol by symbol and subcarrier by subcarrier to correct residual multipath fading, amplitude compression, phase rotation, and frequency selective fading effects.

[0055] It should be noted that analog correction and digital equalization are not independent of each other, but rather adopt a collaborative closed-loop control strategy. When the real-time amplitude and phase distortion exceeds the dynamic threshold (e.g., amplitude deviation greater than 0.5dB or phase deviation greater than 3°), the digital baseband sends an update command to the analog front end, driving the vector modulator to perform a new round of analog domain pre-compensation in real time. This minimizes the adjustment amplitude of the back-end digital domain equalizer, thereby reducing the digital domain computational load and reducing the accumulation of quantization noise, thus improving the overall system energy efficiency and compensation accuracy.

[0056] Understandably, traditional receiving systems typically rely solely on pure digital equalizers for amplitude and phase compensation of the signal in the baseband. While this can correct channel distortion to some extent, when there are significant phase deviations in the analog front-end (such as RF link nonlinearity imbalance, mixer IQ mismatch, or gain differences caused by temperature drift), digital equalization often requires higher-order filtering and complex matrix operations to achieve complete compensation. This leads to increased FPGA or DSP utilization, significantly increased power consumption, and the introduction of additional processing delays. Furthermore, digital equalization is prone to slow convergence, overshoot, or oscillation issues when compensating for extremely large amplitude or phase shifts, severely impacting demodulation stability and real-time performance. This deficiency is particularly pronounced in NB-IoT systems, which have stringent requirements for low power consumption and ultra-low latency.

[0057] It should be understood that, compared to existing technologies, this invention, through deep collaboration between analog vector amplitude and phase correction and digital complex equalization, forms a hierarchical compensation architecture with rapid coarse compensation in the front-end hardware and fine-tuning in the back-end digital domain. Analog correction can quickly respond to non-ideal hardware offsets, eliminating most static or slowly varying amplitude and phase imbalances, significantly reducing the dynamic adjustment pressure on the back-end digital equalization; while digital equalization focuses on compensating for residual minor dynamic fading and short-term transient phase drift, achieving high-precision compensation. This design significantly shortens the amplitude and phase convergence time of the system, improves overall stability, and avoids frequent loss of lock and decision errors caused by large phase compensation. Verification shows that this hierarchical scheme can control the digital equalization compensation residual within ±1° and ±0.2dB in extreme scenarios with large phase offsets (such as phase deviation exceeding 15° and amplitude imbalance exceeding 2dB), while reducing the overall link bit error rate (BER) by at least 30% and improving energy efficiency by approximately 20%, fully meeting the stringent requirements of NB-IoT nodes for high stability and low power consumption.

[0058] For example, in a set of field tests on an NB-IoT receiver chain in a densely built-up urban environment, the channel exhibited significant hardware-introduced amplitude and phase imbalance, with an initial phase deviation of approximately 14° and an amplitude deviation of approximately 1.8dB. Using a traditional standalone digital equalization scheme, the compensation convergence time was approximately 50 milliseconds, the steady-state phase error fluctuated within ±3°, the amplitude error remained within ±0.5dB, and the final system bit error rate was approximately 3.5 × 10⁻⁶. -3 Furthermore, under extreme fading, a short-term loss of lock-in occurs, with a link interruption probability of approximately 2%. However, by employing the analog vector amplitude and phase correction and digital complex equalization coordinated scheme of this invention, the overall compensation convergence time is shortened to approximately 20 milliseconds, the steady-state phase error is controlled within ±0.8°, the amplitude error is reduced to ±0.1dB, and the system bit error rate is significantly reduced to 1.1×10⁻⁶. -3 The probability of link interruption is almost 0%, and the method maintains stable and reliable continuous data reception throughout the entire test, which fully demonstrates the significant advantages of the method in extreme scenarios.

[0059] Example 2: Furthermore, the present invention provides a method for receiving narrowband signals, employing a narrowband signal receiving system as described in the above embodiments, which can solve a technical problem related to narrowband signal reception. Compared with the prior art, the beneficial effects of the narrowband signal receiving method provided by the present invention are the same as those of the narrowband signal receiving system provided in the above embodiments, and other technical features in the narrowband signal receiving method are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0060] Example 3: This invention provides a narrowband signal receiving device, please refer to... Figure 2A narrowband signal receiving device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a narrowband signal receiving method as described in Embodiment 1 above. A narrowband signal receiving device in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. A narrowband signal receiving device is merely an example and should not impose any limitations on the functionality and scope of use of this embodiment. A narrowband signal receiving device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of a narrowband signal receiving device. Processing device 1001, read-only memory 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows a narrowband signal receiving device to communicate wirelessly or wiredly with other devices to exchange data. Although a narrowband signal receiving device with various systems is shown in the figure, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems may be implemented alternatively.

[0061] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0062] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A narrowband signal receiving system, characterized in that, The system includes: The coarse frequency offset capture module is used to acquire the first radio frequency narrowband signal and amplify the first radio frequency narrowband signal with low noise to obtain the second radio frequency narrowband signal. The second RF narrowband signal is down-converted using the local oscillator mixing method to obtain the down-converted signal and the baseband signal. The down-converted signal is sampled by an ADC and then a sliding autocorrelation detection is performed to determine the starting point of the synchronization sequence. The initial frequency offset estimate f is extracted based on the starting point of the synchronization sequence using the normalized phase correlation method; The carrier phase locking module is used to determine the frequency offset pre-compensation value based on the preliminary frequency offset estimate f, apply the frequency offset pre-compensation value, and start the analog phase-locked loop control network PLL to enter the locking phase, outputting the phase error and locking the carrier phase; The digital domain carrier tracking module is used to perform digital fine carrier tracking processing on the baseband signal based on the locked carrier phase using the digital domain Costas loop tracking method, extract the instantaneous phase deviation estimate, and perform numerically controlled oscillator compensation on the baseband signal based on the instantaneous phase deviation estimate to obtain a carrier phase stable signal; The timing synchronization and multipath correction module is used to perform error detection and synchronization compensation for symbol timing based on the carrier phase stable signal using the multipath sensing dual correlation synchronization method, so as to obtain a timing-aligned synchronization symbol signal. The vector amplitude and phase correction and equalization module is used to perform joint compensation of amplitude and phase vectors based on the synchronous symbol signal using analog vector amplitude and phase correction and digital complex equalization to obtain the final equalized output signal.

2. The narrowband signal receiving system as described in claim 1, characterized in that, In the carrier phase locking module, the steps of starting the analog phase-locked loop control network (PLL) to enter the locking phase, outputting the phase error, and locking the carrier phase specifically include: The analog PLL control network includes a phase detector layer, a second-order loop filter layer, and a voltage-controlled oscillator (VCO) layer. The analog PLL control network outputs the phase error through the phase detector layer, and the second-order loop filter layer regulates the phase error. At the same time, the output voltage-controlled voltage is applied to the VCO layer. When the phase error is lower than the preset phase error threshold, the carrier phase is locked.

3. The narrowband signal receiving system as described in claim 1, characterized in that, In the carrier phase-locked loop module, the phase error is determined using a Costas phase detector decision. During the phase error locking process, the equivalent noise bandwidth in the analog phase-locked loop control network (PLL) is dynamically adjusted based on the mean square estimate of the phase error.

4. The narrowband signal receiving system as described in claim 1, characterized in that, In the digital domain carrier tracking module, the compensation process for the baseband signal by numerically controlled oscillator also includes mean square monitoring of the phase error. When the mean square value obtained by the mean square monitoring exceeds the preset phase deviation threshold, the adaptive adjustment strategy is triggered, and the analog phase-locked loop control network PLL in step S20 is automatically restarted to perform fast re-acquisition processing after loss of lock.

5. The narrowband signal receiving system as described in claim 1, characterized in that, In the digital domain carrier tracking module, the digital fine carrier tracking processing includes: constructing an error detection function for the baseband signal. , Where n is the sampling sequence number within the current symbol period; This is the estimated phase deviation value corresponding to the nth sampling sequence number at that instant; To receive the in-phase component of the baseband signal; To receive the quadrature components of the baseband signal; This is a sign function used to extract the positive or negative sign information of the input value; and it is used for the error detection function. Perform window averaging to output the instantaneous phase deviation estimate.

6. The narrowband signal receiving system as described in claim 1, characterized in that, In the timing synchronization and multipath correction module, the multipath sensing dual-correlation synchronization method specifically includes: acquiring the advance sampled data E, the delayed sampled data L, and the timely sampled data P of the carrier phase stable signal, and constructing a timing error function based on the advance sampled data E, the delayed sampled data L, and the timely sampled data P. , , The symbol function is used; the short-interval correlation results and wide-interval correlation results are calculated in parallel. When the two results are inconsistent, it is determined that there is multipath interference. The symbol timing phase compensation is dynamically adjusted by means of synchronous sampling points so that the sampling points are aligned with the position of the maximum energy peak of the main path.

7. The narrowband signal receiving system as described in claim 1, characterized in that, In the vector amplitude and phase correction and equalization module, analog vector amplitude and phase correction specifically includes: using a vector modulator integrated in the analog RF front-end to perform fine-grained adjustment of the amplitude and phase of the input and output branches, achieving front-end analog pre-correction; digital complex equalization specifically includes: calculating channel gain estimates based on pilot symbols. And introduce channel gain estimates for subsequent data symbols. This enables backend digital flattening processing.

8. A method for receiving narrowband signals, applied to a narrowband signal receiving system according to any one of claims 1 to 7, characterized in that, The methods include: Step S10: Acquire the first RF narrowband signal and amplify it with low noise to obtain the second RF narrowband signal; then use the local oscillator mixing method to downconvert the second RF narrowband signal to obtain the downconverted signal and the baseband signal; after sampling the downconverted signal by ADC, perform sliding autocorrelation detection to determine the starting point of the synchronization sequence; based on the starting point of the synchronization sequence, use the normalized phase correlation method to extract the preliminary frequency offset estimate f; Step S20: Determine the frequency offset pre-compensation value based on the preliminary frequency offset estimate f, apply the frequency offset pre-compensation value, and start the analog phase-locked loop control network PLL to enter the locking stage, outputting the phase error and the locked carrier phase; Step S30: Based on the locked carrier phase, the digital domain Costas loop tracking method is used to perform digital fine carrier tracking processing on the baseband signal, extract the instantaneous phase deviation estimate, and perform numerically controlled oscillator compensation on the baseband signal according to the instantaneous phase deviation estimate to obtain a carrier phase stable signal; Step S40: Based on the carrier phase stable signal, the multipath sensing dual correlation synchronization method is used to perform error detection and synchronization compensation for symbol timing, so as to obtain a timing-aligned synchronization symbol signal; Step S50: Based on the synchronization symbol signal, the amplitude and phase vectors are jointly compensated using analog vector amplitude and phase correction and digital complex equalization to obtain the final equalized output signal.

9. A narrowband signal receiving device, characterized in that, The narrowband signal receiving device includes: a memory, a processor, and a narrowband signal receiving program stored in the memory and executable on the processor. When the narrowband signal receiving program is executed by the processor, it implements a narrowband signal receiving system according to any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a narrowband signal receiving program, which, when executed by a processor, implements a narrowband signal receiving system according to any one of claims 1 to 7.

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