Quasi-hemispherical CdZnTe detector reading circuit and working method thereof

Abstract

The invention relates to the technical field of nuclear radiation detection, in particular to a quasi-hemispherical CdZnTe detector reading circuit and a working method thereof. The reading circuit comprises a pre-amplification circuit, a clamping protection circuit, a pole-zero cancellation circuit, an operational amplification circuit, a differentiating circuit, an adjustable gain amplification circuit, a high-precision operational amplification circuit, a first-order S-K filter circuit and an impedance matching circuit which are connected in sequence. Wherein the pole zero cancellation circuit is used for offsetting an exponential decay pole introduced by the pre-amplification circuit; the differentiating circuit is used for compressing the signal pulse width; the adjustable gain amplification circuit is connected with the DAC voltage feedback circuit and is used for realizing gain adjustability; the reading circuit provided by the invention is connected with the CdZnTe detector, a charge signal output by the CdZnTe detector is processed by the reading circuit, and the energy resolution of the CdZnTe detector is improved to be less than 1% (at) 662 keV by extremely reducing noise, inhibiting accumulation, stabilizing a base line and keeping pulse front edge integrity.

Description

Technical Field

[0001] This invention relates to the field of nuclear radiation detection technology, and in particular to a quasi-hemispherical CdZnTe detector readout circuit and its operating method. Background Technology

[0002] CdZnTe detectors, due to their ability to achieve excellent energy resolution at room temperature, have shown great application potential in cutting-edge fields such as deep-earth trace element detection, novel radiopharmaceutical development, nuclear safety monitoring, and space exploration. In particular, the design of the quasi-hemispherical electrode structure partially overcomes the inherent defect of the large difference between the electron and hole mobility-lifetime products in CdZnTe crystals at the detector's physical level, laying the material foundation for achieving ultra-high energy resolution.

[0003] However, this advanced detector structure presents unprecedented performance challenges to its accompanying back-end readout circuitry. First, the CdZnTe crystal itself has a large bulk capacitance, leading to a significant increase in noise in the readout circuitry. Second, due to the vast difference in the mobilities of electrons and holes within the crystal, the detector output signal simultaneously contains electron signals with extremely fast rise times and hole signals with slow rise times. When these signals pass through the preamplifier, they form exponentially decaying voltage signals with different rise times, and the baseline of the voltage signal output by the preamplifier exhibits significant fluctuations. After the signal is processed by the back-end circuitry, some rise time information of the original signal is lost, causing subsequent processing circuits or algorithms to be unable to effectively identify and remove slow hole signals that degrade energy resolution.

[0004] Furthermore, in existing technology tests, after the signal passes through the differential pulse shaping circuit, amplitude overload, i.e., signal undershoot, often occurs, which further reduces the accuracy of energy spectrum measurement.

[0005] Due to the aforementioned technical bottlenecks, although the quasi-hemispherical CdZnTe detector has excellent potential in terms of physical structure, the shortcomings of its matching readout circuit in terms of noise, stability, and signal fidelity severely limit its final performance. Currently, using general-purpose readout circuits (such as...) Figure 1 The quasi-hemispherical CdZnTe detection system shown typically has an energy resolution of 2%~3% @662 keV, which is difficult to achieve <1%@662 keV, and cannot fully meet the urgent needs of cutting-edge science and precision medicine for ultra-high resolution energy spectrometers.

[0006] Therefore, there is an urgent need in the field for a low-noise, high-stability readout circuit specifically designed to match the characteristics of quasi-hemispherical CdZnTe detectors. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides a quasi-hemispherical CdZnTe detector readout circuit and its operating method to solve problems such as high signal noise, baseline fluctuation, signal undershoot, and loss of rise time information, thereby achieving a leap in the energy resolution of the quasi-hemispherical CdZnTe detector from 2%~3%@662 keV to <1%@662 keV.

[0008] To achieve the above objectives, the present invention provides the following technical solution: This invention proposes a readout circuit for a quasi-hemispherical CdZnTe detector. The readout circuit is connected to the CdZnTe detector and is used to process the charge signal output by the CdZnTe detector. The readout circuit comprises the following components connected in sequence: A preamplifier circuit is used to amplify the charge signal. Clamping protection circuit, used to limit signal amplitude; A pole-zero cancellation circuit is used to cancel the exponentially decaying poles introduced by the preamplifier circuit. Operational amplifier circuit; Differentiating circuits are used to compress signal pulse widths; An adjustable gain amplifier circuit, connected to the DAC voltage feedback circuit, is used to achieve adjustable gain; High-precision operational amplifier circuit; A first-order SK filter circuit is used to filter noise from a signal. Impedance matching circuits are used to impedance match signals before outputting them.

[0009] As a preferred technical solution, the preamplifier circuit adopts a multi-stage field-effect transistor parallel structure to reduce the noise introduced by the CdZnTe detector body capacitance, and the field-effect transistor is a junction field-effect transistor.

[0010] As a preferred technical solution, the preamplifier circuit includes a preamplifier operational amplifier A and multiple field-effect transistors (FETs). The inverting input terminal of the preamplifier operational amplifier A is connected to the drain of each FET, the non-inverting input terminal of the preamplifier operational amplifier A and the source of each FET are grounded, the output terminal of the preamplifier operational amplifier A is connected to the clamping circuit, and the gate of each FET is connected to one end of the second capacitor C2 and the feedback resistor R. f One end and feedback capacitor C f One end is connected to the feedback resistor R. f The other end, feedback capacitor C fThe other end of each capacitor is connected to the output of the preamplifier A. The other end of the second capacitor C2 is connected to the output of the CdZnTe detector and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the first resistor R1 and one end of the first capacitor C1. The other end of the first capacitor C1 is grounded, and the other end of the first resistor R1 is connected to a high voltage.

[0011] As a preferred technical solution, the clamping circuit includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2. The cathode of the first diode D1 is connected to a positive power supply, and the anode of the second diode D2 is connected to a negative power supply. The common point between the first diode D1 and the second diode D2 is connected to the output terminal of the preamplifier circuit and the input terminal of the pole-zero cancellation circuit.

[0012] As a preferred technical solution, the pole-zero phase cancellation circuit includes a third capacitor C3. One end of the third capacitor C3 is connected to the output terminal of the clamping circuit and one end of the third resistor R3. The other end of the third capacitor C3 is connected to the other end of the third resistor R3, one end of the fourth resistor R4, and the input terminal of the operational amplifier circuit. The other end of the fourth resistor R4 is grounded.

[0013] As a preferred technical solution, the adjustable gain amplifier circuit includes a second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the differentiating circuit. The gain adjustment terminal of the second operational amplifier U2 is connected to the output terminal of the DAC voltage feedback circuit. The inverting input terminal of the second operational amplifier U2 is connected to one end of the eighth resistor R8, the sixth capacitor C6, and one end of the ninth resistor R9. The other end of the eighth resistor R8 and the other end of the sixth capacitor C6 are grounded. The other end of the ninth resistor R9 is connected to the positive power supply. The output terminal of the second operational amplifier U2 is connected to the input terminal of the high-precision operational amplifier circuit.

[0014] As a preferred technical solution, the high-precision operational amplifier circuit includes a third operational amplifier U3. The non-inverting input terminal of the third operational amplifier U3 is connected to one end of the tenth resistor R10 and the output terminal of the adjustable gain amplifier circuit. The other end of the tenth resistor R10 is grounded. The inverting input terminal of the third operational amplifier U3 is connected to one end of the eighth capacitor C8, one end of the eleventh resistor R11, and one end of the twelfth resistor R12. The other end of the eleventh resistor R11 is connected to one end of the seventh capacitor C7. The other end of the seventh capacitor C7 is grounded. The output terminal of the third operational amplifier U3 is connected to the other end of the eighth capacitor C8, the other end of the twelfth resistor R12, and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the input terminal of the first-order SK filter circuit.

[0015] As a preferred technical solution, the first-order SK filter circuit includes a fourth operational amplifier U4. The non-inverting input terminal of the fourth operational amplifier U4 is connected to one end of the fourteenth resistor R14 and one end of the ninth capacitor C9, and the other end of the ninth capacitor C9 is grounded. The inverting input terminal of the fourth operational amplifier U4 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16, and the other end of the fifteenth resistor R15 is grounded. The output terminal of the fourth operational amplifier U4 is connected to one end of the seventeenth resistor R17 and the input terminal of the impedance matching circuit. The other end of the seventeenth resistor R17 is connected to the other end of the sixteenth resistor R16 and one end of the tenth capacitor C10. The other end of the tenth capacitor C10 is connected to the other end of the fourteenth resistor R14 and the output terminal of the high-precision operational amplifier circuit.

[0016] As a preferred technical solution, the impedance matching circuit includes an eleventh capacitor C11. One end of the eleventh capacitor C11 is connected to the output terminal of the first-order SK filter circuit, and the other end is connected to one end of the eighteenth resistor R18. The other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 and the output terminal, and the other end of the nineteenth resistor R19 is grounded.

[0017] The present invention also proposes a method for operating the readout circuit of the above-mentioned quasi-hemispherical CdZnTe detector, comprising: The quasi-hemispherical CdZnTe detector converts the received nuclear radiation signal into a charge signal and transmits the charge signal to the preamplifier circuit. The preamplifier circuit amplifies the charge signal to obtain the preamplified signal; The clamping protection circuit performs voltage limiting processing on the preamplified signal to obtain a clamping processing signal. The pole-zero cancellation circuit adjusts its own zero point to cancel the poles in the clamping processing signal, thus obtaining a de-scrambling signal. The operational amplifier circuit performs preliminary amplification processing on the de-sampling signal to obtain a primary amplified signal; The differentiating circuit performs pulse width compression on the primary step amplified signal to obtain the differentiated processed signal; The adjustable gain amplifier circuit adjusts the gain of the differential processed signal to obtain a gain adjustment signal. The high-precision operational amplifier circuit amplifies the gain adjustment signal to obtain a secondary amplified signal. The first-order SK filter circuit performs baseline stabilization and noise filtering on the secondary amplified signal to obtain a stable signal. The impedance matching circuit performs impedance matching on the stable signal and then outputs it.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This invention effectively solves the problems of high signal noise, baseline fluctuation, signal undershoot and loss of rise time information by working together with the preamplifier circuit, pole-zero cancellation circuit, differentiating circuit, adjustable gain amplifier circuit, first-order SK filter circuit and impedance matching circuit. It breaks through the readout circuit bottleneck that limits the performance of quasi-hemispherical CdZnTe detector, and significantly improves its energy resolution at 662 keV from 2%~3% to less than 1%, achieving the performance index of ultra-high resolution gamma spectrometer.

[0019] (2) The preamplifier circuit of the present invention adopts a multi-stage field-effect transistor parallel structure. By connecting multiple field-effect transistors in parallel, the equivalent value of the input capacitance is reduced, and the noise superposition caused by the large capacitance of the CdZnTe crystal is suppressed from the source of the circuit. This significantly reduces the noise level of the system and provides a low-noise original signal basis for subsequent signal processing, avoiding noise from masking the details of the effective signal.

[0020] (3) The present invention sets up a first-order SK filter circuit between the high-precision operational amplifier circuit and the impedance matching circuit. The first-order SK filter circuit, as a key post-stage noise suppression unit, effectively filters out the high-frequency noise of the system and greatly stabilizes the signal baseline, avoiding the influence of baseline drift and fluctuation on the signal amplitude extraction accuracy, and ensuring the accuracy of energy spectrum measurement. When the signal is transmitted to the back-end system, the impedance matching circuit completely retains the rise time information of the original signal, ensuring that the subsequent rise time discrimination method can accurately distinguish between fast rise time electron signals and slow rise time hole signals, successfully eliminating hole signal interference and further improving energy resolution.

[0021] (4) The present invention combines the pole-zero cancellation circuit with the differentiating circuit. The pole-zero cancellation circuit accurately cancels the exponential decay pole introduced by the preamplifier circuit through its adjustable zero point, fundamentally eliminating the signal undershoot phenomenon. The differentiating circuit compresses the signal pulse width from the millisecond level to the microsecond level, greatly reducing the system dead time and increasing the signal throughput, which is suitable for high count rate detection scenarios.

[0022] (5) The present invention combines the adjustable gain amplifier circuit with the DAC voltage feedback circuit to realize the flexible and precise digital adjustment of the system gain, thereby enabling the same set of readout circuits to adapt to gamma ray measurements of different energy ranges and detectors of different sensitivities, greatly improving the applicability and scene coverage of the system. Attached Figure Description

[0023] Figure 1 This is a block diagram of a general-purpose readout circuit. Figure 2 This is a block diagram of the readout circuit of the present invention; Figure 3 This is a schematic diagram of the readout circuit of the present invention; Figure 4 This is a schematic diagram of the preamplifier circuit of the present invention; Figure 5 This is a test schematic diagram of the readout circuit of the present invention; Figure 6 The waveform of the charge signal output by the quasi-hemispherical CdZnTe detector after processing by the readout circuit of this invention is shown. Figure 7 The diagram shows the energy spectrum output of the readout circuit of this invention (A) and the energy spectrum obtained after rise time discrimination (B). Figure labels: 1. Preamplifier circuit; 2. Clamping protection circuit; 3. Pole-zero cancellation circuit; 4. Operational amplifier circuit; 5. Differentiating circuit; 6. Adjustable gain amplifier circuit; 7. High-precision operational amplifier circuit; 8. First-order SK filter circuit; 9. Impedance matching circuit; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; R7, Seventh resistor; R8, Eighth resistor; R9, Ninth resistor; R10, Tenth resistor; R11, Eleventh resistor; R12, Twelfth resistor; R13, Thirteenth resistor; R14, Fourteenth resistor; R15, Fifteenth resistor; R16, Sixteenth resistor; R17, Seventeenth resistor; R18, Eighteenth resistor; R19, Nineteenth resistor; R f Feedback resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor; C9, ninth capacitor; C10, tenth capacitor; C11, eleventh capacitor; C f 1. Feedback capacitor; D1, first diode; D2, second diode; Q1, first field-effect transistor; Q2, second field-effect transistor; Q3, third field-effect transistor; A, preamplifier; U1, first operational amplifier; U2, second operational amplifier; U3, third operational amplifier; U4, fourth operational amplifier; F, DAC voltage feedback circuit. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the protection scope of the present invention. Example

[0025] refer to Figures 2 to 4This embodiment proposes a readout circuit for a quasi-hemispherical CdZnTe detector. This readout circuit is connected to the output terminal of the CdZnTe detector and is used to process the charge signal output by the CdZnTe detector. The preferred dimensions of the CdZnTe detector are 10×10×5mm. 3 The readout circuit includes, in sequence, a preamplifier circuit, a clamping protection circuit, a pole-zero cancellation circuit, an operational amplifier circuit, a differentiating circuit, an adjustable gain amplifier circuit, a high-precision operational amplifier circuit, a first-order SK filter circuit, and an impedance matching circuit. The preamplifier circuit amplifies the received signal; the clamping protection circuit limits the signal amplitude; the pole-zero cancellation circuit cancels the exponentially decaying poles introduced by the preamplifier circuit; the differentiating circuit compresses the signal pulse width; the adjustable gain amplifier circuit is connected to the DAC voltage feedback circuit to achieve adjustable gain; the first-order SK filter circuit filters noise from the signal; and the impedance matching circuit outputs the signal after impedance matching.

[0026] refer to Figure 3 The preamplifier circuit employs a multi-stage parallel field-effect transistor (FET) structure to reduce noise introduced by the CdZnTe detector body capacitance. The FETs are preferably junction field-effect transistors (JFETs). Specifically, the preamplifier circuit includes a preamplifier operational amplifier A and multiple FETs. In this embodiment, there are three FETs: Q1, Q2, and Q3. The inverting input of the preamplifier operational amplifier A is connected to the drain of each FET, while the non-inverting input of the preamplifier operational amplifier A and the source of each FET are grounded. The output of operational amplifier A is connected to the clamping circuit. The gate of each field-effect transistor is connected to one end of the second capacitor C2, one end of the feedback resistor Rf, and one end of the feedback capacitor Cf. The other ends of the feedback resistor Rf and the feedback capacitor Cf are both connected to the output of the preamplifier operational amplifier A. The other end of the second capacitor C2 is connected to the output of the CdZnTe detector and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the first resistor R1 and one end of the first capacitor C1. The other end of the first capacitor C1 is grounded, and the other end of the first resistor R1 is connected to a high voltage. The preamplifier circuit is the first stage of charge signal processing. This embodiment, with its multi-stage field-effect transistor parallel structure, can significantly reduce the equivalent value of the input capacitance, making it suitable for processing weak charge signals generated by quasi-hemispherical CdZnTe detectors (whose bulk capacitance is typically large).

[0027] refer to Figure 2The clamping circuit includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2. The cathode of the first diode D1 is connected to the positive power supply, and the anode of the second diode D2 is connected to the negative power supply. The common point between the first diode D1 and the second diode D2 is connected to the output terminal of the preamplifier A in the preamplifier circuit and the input terminal of the pole-zero cancellation circuit. When the signal amplitude exceeds the preset safe voltage threshold, the circuit will conduct to discharge the overvoltage signal, thereby protecting the subsequent precision analog circuits (such as operational amplifier circuits) from damage or saturation, and ensuring that the entire system operates in the linear region.

[0028] The pole-zero cancellation circuit includes a third capacitor C3. One end of the third capacitor C3 is connected to the common point between the first diode D1 and the second diode D2, and one end of the third resistor R3. The other end of the third capacitor C3 is connected to the other end of the third resistor R3, one end of the fourth resistor R4, and the input terminal of the operational amplifier circuit. The other end of the fourth resistor R4 is grounded. In this embodiment, the pole-zero cancellation circuit achieves a perfect match between the zero-point frequency and the pole-point frequency by finely adjusting the adjustable resistors in the circuit. This makes the output signal a near-ideal step-attenuated signal, fundamentally eliminating signal undershoot.

[0029] The operational amplifier circuit includes a first operational amplifier U1, and a differentiating circuit includes a fifth capacitor C5 and a seventh resistor R7. The non-inverting input of the first operational amplifier U1 is connected to the third capacitor C3 as the input of the operational amplifier circuit. The inverting input of the first operational amplifier U1 is connected to one end of the fourth capacitor C4, one end of the fifth resistor R5, and one end of the sixth resistor R6. The other end of the fifth resistor R5 is grounded. The output of the first operational amplifier U1 is connected to the other end of the fourth capacitor C4, the other end of the sixth resistor R6, and one end of the fifth capacitor C5. The other end of the fifth capacitor C5 is connected to one end of the seventh resistor R7 and the input of the adjustable gain amplifier circuit. The other end of the seventh resistor R7 is grounded. In this embodiment, the differentiating circuit can convert a slowly exponentially decaying signal into a narrow bipolar pulse. By selecting appropriate capacitor and resistor parameters, the pulse width of the original signal can be compressed from the millisecond level to the microsecond level. This greatly reduces the system dead time, enabling the system to process high-throughput signals.

[0030] The adjustable gain amplifier circuit includes a second operational amplifier U2. The non-inverting input of the second operational amplifier U2 is connected to the fifth capacitor C5. The gain adjustment terminal of the second operational amplifier U2 is connected to the output terminal of the DAC voltage feedback circuit. The inverting input of the second operational amplifier U2 is connected to one end of the eighth resistor R8, the sixth capacitor C6, and one end of the ninth resistor R9. The other ends of the eighth resistor R8 and the sixth capacitor C6 are grounded. The other end of the ninth resistor R9 is connected to the positive power supply. The output terminal of the second operational amplifier U2 is connected to the input terminal of the high-precision operational amplifier circuit. In this embodiment, the adjustable gain amplifier circuit is connected to the DAC voltage feedback circuit. By changing the output voltage of the DAC, the gain can be flexibly set, thereby meeting the dynamic range requirements of different measurement scenarios and enhancing the applicability of the system.

[0031] The high-precision operational amplifier circuit includes a third operational amplifier U3. The non-inverting input of the third operational amplifier U3 is connected to one end of the tenth resistor R10 and the output of the adjustable gain amplifier circuit. The other end of the tenth resistor R10 is grounded. The inverting input of the third operational amplifier U3 is connected to one end of the eighth capacitor C8, one end of the eleventh resistor R11, and one end of the twelfth resistor R12. The other end of the eleventh resistor R11 is connected to one end of the seventh capacitor C7. The other end of the seventh capacitor C7 is grounded. The output of the third operational amplifier U3 is connected to the other end of the eighth capacitor C8, the other end of the twelfth resistor R12, and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the input of the first-order SK filter circuit.

[0032] The first-order SK filter circuit includes a fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is connected to one end of the fourteenth resistor R14 and one end of the ninth capacitor C9, with the other end of the ninth capacitor C9 grounded. The inverting input of the fourth operational amplifier U4 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16, with the other end of the fifteenth resistor R15 grounded. The output of the fourth operational amplifier U4 is connected to one end of the seventeenth resistor R17 and the input of the impedance matching circuit. The other end of the seventeenth resistor R17 is connected to the other end of the sixteenth resistor R16 and one end of the tenth capacitor C10. The other end of the tenth capacitor C10 is connected to the other end of the fourteenth resistor R14 and the output of the high-precision operational amplifier circuit. In this embodiment, the first-order SK filter circuit can filter out useless high-frequency noise (such as shot noise and thermal noise) in the signal while retaining the main frequency components of the signal. Furthermore, another key function of this circuit is to greatly stabilize the signal baseline, avoiding the impact of baseline drift and fluctuations on the accuracy of signal amplitude extraction.

[0033] The impedance matching circuit includes an eleventh capacitor C11. One end of the eleventh capacitor C11 is connected to the output terminal of the first-order SK filter circuit, and the other end is connected to one end of the eighteenth resistor R18. The other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 and the output terminal. The other end of the nineteenth resistor R19 is grounded. In this embodiment, the impedance matching circuit can minimize signal reflection and distortion, ensuring that the processed signal, especially the rise time information which is crucial for discrimination, can be transmitted completely and accurately to the back-end rise time discrimination system.

[0034] The operation method of the readout circuit in the above embodiments is as follows: The quasi-hemispherical CdZnTe detector converts the received nuclear radiation signal into a charge signal and transmits the charge signal to the preamplifier circuit. The preamplifier circuit amplifies the charge signal to obtain the preamplified signal; The clamping protection circuit performs voltage limiting processing on the preamplified signal to obtain a clamping processing signal, which avoids saturation of the downstream circuit and maintains the linear operating range. The pole-zero cancellation circuit adjusts its own zero point to cancel the poles in the clamping signal, thereby eliminating signal undershoot and accumulation and obtaining a de-overshoot signal. The operational amplifier circuit performs preliminary amplification on the de-sampling signal to obtain the primary amplified signal; The differentiating circuit performs pulse width compression on the primary step amplification signal (from the millisecond level to the microsecond level) to obtain the differential processed signal, thereby reducing the system dead time. The adjustable gain amplifier circuit adjusts the gain of the differential processing signal to obtain a gain adjustment signal, so as to adapt to the dynamic range requirements of different measurement scenarios. A high-precision operational amplifier circuit amplifies the gain-adjusted signal to obtain a secondary amplified signal. The first-order SK filter circuit performs baseline stabilization and high-frequency noise filtering on the secondary amplified signal to obtain a stable signal, ensuring accurate extraction of the subsequent signal amplitude. The impedance matching circuit performs impedance matching on the stable signal and then outputs it to the back-end rise time discrimination system, ensuring the integrity of signal transmission; the back-end rise time discrimination system performs rise time discrimination by setting rise time threshold and amplitude threshold range.

[0035] To better illustrate the beneficial effects of the present invention, see references. Figure 5 The inventors combined the readout circuit proposed in the above embodiments with a specification of 10×10×5mm. 3 A quasi-hemispherical CdZnTe detector was connected and tested, with a rise time threshold of 161 ns and an amplitude threshold range of 10%–90%. (Reference) Figure 6As can be seen, after processing by the readout circuit proposed in this invention, the exponentially decaying signal output is standard, with good signal quality, low noise, and a very stable signal baseline. This provides a good foundation for subsequent rise time discrimination methods. (Refer to...) Figure 7 (A is a schematic diagram of the original energy spectrum output by the readout circuit of the present invention, and B is a schematic diagram of the energy spectrum obtained after the original energy spectrum is determined by rise time discrimination.) It can be seen that after the rise time discrimination system at the back end of the readout circuit of the present invention performs rise time discrimination and removes hole signals, the energy resolution of the quasi-hemispherical CdZnTe detector reaches <1% @662 keV.

[0036] In summary, this invention, through the synergistic design of a preamplifier circuit, clamping protection circuit, pole-zero cancellation circuit, operational amplifier circuit, differentiating circuit, adjustable gain amplifier circuit, high-precision operational amplifier circuit, first-order SK filter circuit, and impedance matching circuit, serves and optimizes the implementation conditions of the "rise time discrimination method." By maximally reducing noise, suppressing accumulation, stabilizing the baseline, and maintaining the integrity of the pulse leading edge, it significantly improves the energy resolution of the CdZnTe detector from the original 2%~3%@662 keV to <1%@662 keV, solving the key problem of high-resolution energy spectrum detection.

[0037] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

[0038] It should be understood that the present invention is not limited to the content already described above, and modifications and changes can be made without departing from its scope. The scope of the present invention is limited only by the appended claims.

Claims

1. A readout circuit for a quasi-hemispherical CdZnTe detector, characterized in that, The readout circuit is connected to the CdZnTe detector and is used to process the charge signal output by the CdZnTe detector. The readout circuit includes the following components connected in sequence: A preamplifier circuit (1) is used to amplify the charge signal; Clamping protection circuit (2) is used to limit signal amplitude; The pole-zero cancellation circuit (3) is used to cancel the exponentially decaying pole introduced by the preamplifier circuit (1); Operational amplifier circuit (4); Differentiating circuit (5) is used to compress signal pulse width; The adjustable gain amplifier circuit (6) is connected to the DAC voltage feedback circuit F to achieve adjustable gain; High-precision operational amplifier circuit (7); A first-order SK filter circuit (8) is used to filter noise from the signal; Impedance matching circuit (9) is used to output the signal after impedance matching.

2. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The preamplifier circuit (1) adopts a multi-stage field-effect transistor parallel structure to reduce the noise introduced by the CdZnTe detector body capacitance. The field-effect transistor is a junction field-effect transistor.

3. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 2, characterized in that, The preamplifier circuit (1) includes a preamplifier operational amplifier A and multiple field-effect transistors (FETs). The inverting input terminal of the preamplifier operational amplifier A is connected to the drain of each FET, and the non-inverting input terminal of the preamplifier operational amplifier A and the source of each FET are grounded. The output terminal of the preamplifier operational amplifier A is connected to the clamping circuit. The gate of each FET is connected to one end of the second capacitor C2 and the feedback resistor R. f One end and feedback capacitor C f One end is connected to the feedback resistor R. f The other end, feedback capacitor C f The other end of each capacitor is connected to the output of the preamplifier A. The other end of the second capacitor C2 is connected to the output of the CdZnTe detector and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the first resistor R1 and one end of the first capacitor C1. The other end of the first capacitor C1 is grounded, and the other end of the first resistor R1 is connected to a high voltage.

4. The readout circuit for the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The clamping circuit includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2. The cathode of the first diode D1 is connected to a positive power supply, and the anode of the second diode D2 is connected to a negative power supply. The common point between the first diode D1 and the second diode D2 is connected to the output terminal of the preamplifier circuit (1) and the input terminal of the pole-zero cancellation circuit (3).

5. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The pole-zero cancellation circuit (3) includes a third capacitor C3. One end of the third capacitor C3 is connected to the output terminal of the clamping circuit and one end of the third resistor R3. The other end of the third capacitor C3 is connected to the other end of the third resistor R3, one end of the fourth resistor R4 and the input terminal of the operational amplifier circuit (4). The other end of the fourth resistor R4 is grounded.

6. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The adjustable gain amplifier circuit (6) includes a second operational amplifier U2. The non-inverting input of the second operational amplifier U2 is connected to the output of the differentiating circuit (5). The gain adjustment terminal of the second operational amplifier U2 is connected to the output of the DAC voltage feedback circuit. The inverting input of the second operational amplifier U2 is connected to one end of the eighth resistor R8, the sixth capacitor C6, and one end of the ninth resistor R9. The other end of the eighth resistor R8 and the other end of the sixth capacitor C6 are grounded. The other end of the ninth resistor R9 is connected to the positive power supply. The output of the second operational amplifier U2 is connected to the input of the high-precision operational amplifier circuit (7).

7. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The high-precision operational amplifier circuit (7) includes a third operational amplifier U3. The non-inverting input terminal of the third operational amplifier U3 is connected to one end of the tenth resistor R10 and the output terminal of the adjustable gain amplifier circuit (6). The other end of the tenth resistor R10 is grounded. The inverting input terminal of the third operational amplifier U3 is connected to one end of the eighth capacitor C8, one end of the eleventh resistor R11 and one end of the twelfth resistor R12. The other end of the eleventh resistor R11 is connected to one end of the seventh capacitor C7. The other end of the seventh capacitor C7 is grounded. The output terminal of the third operational amplifier U3 is connected to the other end of the eighth capacitor C8, the other end of the twelfth resistor R12 and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the input terminal of the first-order SK filter circuit (8).

8. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The first-order SK filter circuit (8) includes a fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is connected to one end of the fourteenth resistor R14 and one end of the ninth capacitor C9. The other end of the ninth capacitor C9 is grounded. The inverting input of the fourth operational amplifier U4 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16. The other end of the fifteenth resistor R15 is grounded. The output of the fourth operational amplifier U4 is connected to one end of the seventeenth resistor R17 and the input of the impedance matching circuit (9). The other end of the seventeenth resistor R17 is connected to the other end of the sixteenth resistor R16 and one end of the tenth capacitor C10. The other end of the tenth capacitor C10 is connected to the other end of the fourteenth resistor R14 and the output of the high-precision operational amplifier circuit (7).

9. The readout circuit of the quasi-hemispherical CdZnTe detector according to claim 1, characterized in that, The impedance matching circuit (9) includes an eleventh capacitor C11. One end of the eleventh capacitor C11 is connected to the output terminal of the first-order SK filter circuit (8), and the other end is connected to one end of the eighteenth resistor R18. The other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 and the output terminal. The other end of the nineteenth resistor R19 is grounded.

10. A method for operating the readout circuit of the quasi-hemispherical CdZnTe detector according to any one of claims 1 to 9, characterized in that, include: The quasi-hemispherical CdZnTe detector converts the received nuclear radiation signal into a charge signal and transmits the charge signal to the preamplifier circuit (1). The preamplifier circuit (1) amplifies the charge signal to obtain the preamplified signal; The clamping protection circuit (2) performs voltage limiting processing on the preamplified signal to obtain the clamping processing signal; The pole-zero cancellation circuit (3) adjusts its own zero point to cancel the poles in the clamping processing signal to obtain the de-scratching signal; The operational amplifier circuit (4) performs preliminary amplification processing on the de-sampling signal to obtain the primary amplified signal; The differentiating circuit (5) performs pulse width compression on the primary step amplification signal to obtain the differential processing signal; The adjustable gain amplifier circuit adjusts the gain of the differential processed signal to obtain a gain adjustment signal. The high-precision operational amplifier circuit (7) amplifies the gain adjustment signal to obtain the secondary amplified signal; The first-order SK filter circuit (8) performs baseline stabilization and noise filtering on the secondary amplified signal to obtain a stable signal; The impedance matching circuit (9) performs impedance matching on the stable signal and then outputs it.

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