Digital clock phase measurement method and system based on direct sampling technique

Abstract

The application provides a digital clock phase measurement method and system based on a direct sampling technology, and a specific embodiment of the method comprises the following steps: triggering a first counter based on the edge of a first to-be-measured clock signal, using a preset sampling clock signal to sample the numerical signal of the first counter as a first timestamp signal, and the first timestamp signal is used to represent the phase of the first to-be-measured clock signal; triggering a second counter based on the edge of a second to-be-measured clock signal, using the sampling clock signal to sample the numerical signal of the second counter as a second timestamp signal; calculating the difference value of the numerical signal of each sampling point based on the first timestamp signal and the second timestamp signal, obtaining the phase difference value of the first to-be-measured clock signal and the second to-be-measured clock signal at each sampling point, and the sign of the phase difference value represents the phase leading relationship; and performing statistical analysis on the calculated phase difference value, and determining the phase difference of the first to-be-measured clock signal and the second to-be-measured clock signal according to the statistical analysis result.

Description

Technical Field

[0001] This invention relates to the field of time-frequency synchronization network technology, and in particular to a digital clock phase measurement method and system based on direct sampling technology. Background Technology

[0002] With the rapid development of applications and services such as 5G, metaverse, and cloud services, traffic in data optical networks, including optical access networks (user to data center) and data center optical switching networks (between servers, racks, and clusters), is increasing exponentially. This places higher demands on bandwidth and throughput on current optical switching networks. For the widely used optical network communication mode based on time-frequency synchronization and time slot distribution using TDM (Time-Division Multiplexing), a new challenge arises: the time slot granularity must be continuously refined to carry higher aggregated traffic within a fixed clock cycle.

[0003] To achieve high-precision time slot allocation, high-precision time synchronization among widely distributed nodes is required. In a high-precision time synchronization system, the transmitters and receivers of each node port are in different clock domains. The transmitter clock of the master node and the receiver clock of the slave node have a certain phase difference. When the transmitter sends data for subsequent time synchronization at a specific moment (such as the rising edge) of its clock signal, the receiver needs to sample the data at the corresponding moment of its clock signal.

[0004] If there is a phase difference between the two clock signals, the sampling time at the receiver may not match the transmission time at the transmitter, resulting in inaccurate sampled data. Figure 1 As shown, Figure 1 A schematic diagram illustrating an example of how phase error can lead to sampling data error is shown. Figure 1 In the example shown, assume clk1 is the transmitting clock signal, data1 is the corresponding data signal used for time synchronization, and sample_clk is the sampling clock at the receiving end after frequency and phase synchronization. In this case, the data sampled by the receiving end is consistent with the data transmitted by the transmitting end. However, when there is a phase difference between the transmitting and receiving clocks, such as... Figure 1As shown by the dashed line, assuming clk_phase_shift is the transmitting clock signal, and there is a phase difference between the receiving clock samp_clk and the transmitting clock, the data data2 sampled by the receiving clock will have an error compared to the data transmitted by the transmitting end. When the sampled data used for subsequent time synchronization is inaccurate, the time synchronization process based on this data will lead to a large error in the final time synchronization result. Therefore, the clock phase difference between the transmitting and receiving clock domains at each node port is one of the main factors causing synchronization errors. Measuring and correcting this factor is crucial to further improving the synchronization accuracy of the time synchronization system. Therefore, how to perform digital clock phase measurement is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a digital clock phase measurement method and system based on direct sampling technology to eliminate or improve one or more defects existing in the prior art.

[0006] According to a first aspect, a digital clock phase measurement method based on direct sampling technology is provided, characterized in that the method includes: triggering a first counter based on the edge of a first clock signal under test, and sampling the numerical signal of the first counter using a preset sampling clock signal as a first timestamp signal, wherein the first timestamp signal is used to represent the phase of the first clock signal under test; triggering a second counter based on the edge of a second clock signal under test, and sampling the numerical signal of the second counter using the sampling clock signal as a second timestamp signal, wherein the second timestamp signal is used to represent the phase of the second clock signal under test; calculating the difference between the numerical signals of each sampling point based on the first timestamp signal and the second timestamp signal to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point, wherein the sign of the phase difference indicates the phase lead relationship; performing statistical analysis on the calculated phase difference, and determining the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results.

[0007] According to a second aspect, a digital clock phase measurement system based on direct sampling technology is provided, characterized in that the system comprises: a first timestamp generation unit, including a first counter, for triggering the first counter based on an edge of a first clock signal under test; a first sampler, including multiple cascaded D flip-flops, for sampling the numerical signal of the first counter using a preset sampling clock signal as a first timestamp signal, wherein the first timestamp signal is used to represent the phase of the first clock signal under test; a second timestamp generation unit, including a second counter, for triggering the second counter based on an edge of a second clock signal under test; and a second sampler, including multiple cascaded D flip-flops. A D flip-flop is used to sample the numerical signal of the second counter using the sampling clock signal as a second timestamp signal, wherein the second timestamp signal is used to represent the phase of the second clock signal under test; a difference calculation unit is used to calculate the difference between the first timestamp signal and the second timestamp signal at each sampling point to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point, wherein the sign of the phase difference indicates the phase lead relationship; an accumulator and a post-processing unit are used to perform statistical analysis on the calculated phase difference and determine the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results.

[0008] This specification provides a digital clock phase measurement method and system based on direct sampling technology. A first counter is triggered based on the edge of a first clock signal under test, and the numerical signal of the first counter is sampled using a preset sampling clock signal as a first timestamp signal, which represents the phase of the first clock signal under test. Simultaneously, a second counter is triggered based on the edge of a second clock signal under test, and the numerical signal of the second counter is sampled using the same sampling clock signal as a second timestamp signal, which also represents the phase of the second clock signal under test. Then, the difference between the numerical signals at each sampling point is calculated based on the first and second timestamp signals to obtain the phase difference between the first and second clock signals under test at each sampling point. The sign of this phase difference indicates the phase lead relationship. Finally, statistical analysis is performed on the calculated phase difference values ​​at each sampling point, and the phase difference between the first and second clock signals under test is determined based on the statistical analysis results. Therefore, by directly sampling, a timestamp signal representing the phase of the clock signal under test can be obtained. The phase difference and phase lead relationship between the two clock signals under test can be determined by the difference between their timestamp signals. Furthermore, statistical analysis of the phase difference at multiple sampling points can make the phase difference between the two clock signals under test more accurate.

[0009] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, and will also become apparent in part to those skilled in the art upon studying the description, or may be learned by practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the description and drawings.

[0010] Those skilled in the art will understand that the objectives and advantages achievable with the present invention are not limited to those specifically described above, and that the above and other objectives achievable with the present invention will become clearer from the following detailed description. Attached Figure Description

[0011] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0012] Figure 1 A schematic diagram illustrating an example of how phase error can lead to sampling data error is shown.

[0013] Figure 2 A schematic diagram illustrating an example of phase difference measurement based on the duty cycle of an inter-clock XOR signal is shown.

[0014] Figure 3 A flowchart of a digital clock phase measurement method based on direct sampling technology according to one embodiment is shown;

[0015] Figure 4 A schematic diagram illustrating an example of the numerical mapping rule for the subtraction operation of timestamp signals corresponding to two clock signals under test;

[0016] Figure 5 This diagram illustrates an example of a timing diagram of key signals during the execution of the digital clock phase measurement method based on direct sampling technology according to this embodiment.

[0017] Figure 6 A schematic block diagram of a digital clock phase measurement system based on direct sampling technology according to one embodiment is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0019] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0020] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0021] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0022] It is understood that the ordinal numbers such as "first" and "second" mentioned in this specification are only used to distinguish multiple objects of the same or different categories (such as components, steps, parameters, etc.), and do not indicate the priority, importance or order relationship between objects, nor do they constitute a limitation on the technical features.

[0023] As mentioned earlier, how to perform digital clock phase measurement is a problem that urgently needs to be solved.

[0024] In traditional time synchronization networks, various digital clock phase measurement techniques can be used to measure the clock phase difference between the transmitting and receiving clock domains of each node port.

[0025] As an example, phase measurement techniques based on Time-to-Digital Converters (TDCs) can be used. In digital systems, TDCs are a commonly used technique to convert the time interval between the edges of two signals into a digital measurement. Internally, a high-precision oscillator-based reference clock source generates a reference clock signal. A sub-picosecond TDC core (typically using a vernier delay chain structure) measures the time interval between the rising edges of the input clock and the reference clock signal and outputs this time interval as a digital code. An internal calibration subsystem then calibrates the measurement result, performs temperature compensation, and corrects for nonlinearity, accurately measuring the phase difference between the clock signals. However, current mainstream TDC designs typically use delay line structures. A delay line is usually a chain of dozens to hundreds of "minimum delay units," such as LUT (Look-Up Table) buffers, linked together. While this achieves high time resolution, the delay between the nodes in the delay line structure is often uneven due to factors such as process technology, temperature, and unequal wiring delays. Therefore, the measurement accuracy of this type of TDC is often poor. In addition, another shortcoming of TDC is that the method uses a single direct conversion rather than a statistical approach to measure the signal interval. For periodic clock signals, TDC cannot use repeated sampling to improve the measurement accuracy through statistical methods, which also prevents it from achieving better measurement results.

[0026] As another example, phase measurement technology based on a Digital Dual Mixer Time Difference (DDMTD) can be used. The core idea is to convert minute time or phase differences into low-frequency signals using a dual mixer structure. Internally, the DDMTD uses a PLL (Phase Locked Loop) to generate a sampling clock with a frequency related to the clock under test (UTC). This sampling clock is then used to sample the UTC clocks clkA and clkB respectively. After sampling, the frequency of the resulting square wave is the difference between the UTC signal and the sampling clock frequency. In this process, the signal period is amplified by a factor of N+1, and the phase difference is also amplified by this factor, thus allowing phase difference measurement at a lower clock frequency. After shaping the sampled signal using de-glitch logic, a counter is used to measure the time difference phase between the rising edges of the two shaped signals. The resulting delay, after correction, yields the phase difference between the original UTC clocks. While DDMTD can achieve high measurement accuracy, it requires complex external hardware and loop control algorithms. For example, when generating the sampling clock, it typically employs an architecture combining an external VCO (Voltage-Controlled Oscillator) and a soft PLL. This increases hardware complexity and design cost, and makes it difficult to adapt the technology to existing infrastructure. Furthermore, the low-frequency phase difference signal output by DDMTD after mixing exhibits a sawtooth waveform in the time domain, requiring smoothing using a de-aliasing algorithm. This step also introduces additional errors, thus affecting measurement accuracy.

[0027] As another example, phase difference can also be measured based on the duty cycle of the XOR signal between clocks. Processing two clock signals of the same frequency using an XOR logic gate will output a square wave signal. The duty cycle of this square wave signal has a direct linear relationship with the phase difference between the two clock signals. For example, ... Figure 2 As shown, Figure 2 A schematic diagram illustrating an example of phase difference measurement based on the duty cycle of an inter-clock XOR signal is shown. Figure 2 In the example shown, there are two clock signals to be measured, clk1 and clk2. The duty cycle of both clock signals is 50%, and the clock period is T. clk In this example, assume the time difference between clock signal clk1 and clock signal clk2 is... After clock signals clk1 and clk2 are XORed, the resulting signal is clk1^clk2 (shown in the third row of the diagram). This XORed signal is still a square wave, but its period becomes T. clk / 2. As can be seen from the figure, in a T clkWithin the cycle, the XOR signal contains two high-level cycles. As shown in the figure, these two high levels originate from the time delay between the rising edges and the time delay between the falling edges of the two clock signals under test, respectively. At this time, the measurement of the phase difference between clock signals clk1 and clk2 is transformed into the measurement of the duty cycle of the clk1^clk2 signals.

[0028] When two signals are in phase (e.g., both are high or both are low), the XOR result is 0. When the two signals have different phases (e.g., one signal is high and the other is low), the XOR result is 1. However, regardless of whether clk1 leads clk2 or clk2 leads clk1, the duty cycle of the XOR signal is the same, resulting in phase ambiguity.

[0029] Therefore, embodiments of this specification provide a digital clock phase measurement method based on direct sampling technology. This method represents the phase of the clock signal under test using timestamp signals and replaces the XOR operation of the clock signals under test with a subtraction operation between the timestamp signals. This allows the phase difference and phase lead relationship between two clock signals under test (clk1, clk2) to be obtained based on the subtraction result (including the sign and specific value of the result). Subsequent statistical analysis (e.g., accumulation, averaging, etc.) of the subtraction result within the phase measurement period yields the precise phase difference between the two clock signals under test.

[0030] See also Figure 3 , Figure 3 A flowchart of a digital clock phase measurement method based on direct sampling technology according to one embodiment is shown. It will be understood that this method can be performed by a digital clock phase measurement system based on direct sampling technology. Figure 3 As shown, the digital clock phase measurement method based on direct sampling technology may include the following steps 301-304, specifically:

[0031] Step 301: Trigger the first counter based on the edge of the first clock signal to be tested, and use a preset sampling clock signal to sample the numerical signal of the first counter as the first timestamp signal.

[0032] In this embodiment, the clock signals used for phase measurement include a first clock signal to be measured and a second clock signal to be measured. The first and second clock signals to be measured can refer to the clock signals corresponding to the transmitting and receiving ends of the node ports, respectively. For example, the first and second clock signals to be measured can be two high-frequency (e.g., frequencies above 100MHz) digital clock signals. Here, a node can refer to any independent network device in a distributed system that needs to work collaboratively with other devices. In this example, a first counter can be triggered based on the edge of the first clock signal to be measured, and the numerical signal of the first counter can be sampled using a preset sampling clock signal as a first timestamp signal. Here, the sampling clock signal can be a periodically changing electrical signal (e.g., a square wave), and its rising or falling edge can serve as a trigger point, indicating that the signal is sampled at this moment. As an example, a phase-locked loop can be used to generate a sampling clock signal for sampling the clock signal to be measured. Since the change in the first timestamp signal occurs at the edge of the first clock signal to be measured, and the edge itself contains phase information, the first timestamp signal can be used to represent the phase of the first clock signal to be measured.

[0033] In some examples, the sampling clock signal used during sampling can be independent of the two clock signals under test. Specifically, the sampling clock signal and the first clock signal under test do not have a fixed frequency or phase correlation, and their timing variations (such as phase jitter and frequency drift) are independent of each other. Similarly, the sampling clock signal and the second clock signal under test do not have a fixed frequency or phase correlation, and their timing variations (such as phase jitter and frequency drift) are independent of each other. By using a sampling clock signal independent of the clock signals under test, it is possible to avoid using complex external hardware and loop control algorithms to generate a precise sampling clock with a fixed frequency relationship to the clock signals under test, thereby reducing design costs and hardware complexity, and providing high adaptability for deployment in current infrastructure.

[0034] Step 302: Trigger the second counter based on the edge of the second clock signal to be tested, and use the sampling clock signal to sample the value signal of the second counter as the second timestamp signal.

[0035] In this embodiment, a second counter can be triggered based on the edge of the second clock signal under test, and the numerical signal of the second counter can be sampled using the same sampling clock signal as in step 301 as the second timestamp signal. Since the change of the second timestamp signal occurs at the edge of the second clock signal under test, and the edge itself contains phase information, the second timestamp signal can be used to represent the phase of the second clock signal under test. In practice, steps 301 and 302 can be executed simultaneously.

[0036] In some examples, the edges used to trigger the counter can include both rising and falling edges. Thus, the counter can be triggered by either a rising or falling edge.

[0037] In some examples, before performing steps 301 and 302, the above-described digital clock phase measurement method based on direct sampling technology may also include the following step: receiving control information.

[0038] In this example, external control information can be received. This control information may include measurement control signals and measurement parameters. For instance, measurement control signals may include start measurement, end measurement, etc. For example, corresponding buttons for start and end measurement can be set on the control interface, allowing technicians to input measurement control signals to the measurement system by clicking these buttons. Measurement parameters may include the number of sampling periods, which refers to the total number of samples taken within a specific time range. Typically, the number of sampling periods is determined by the total measurement duration, sampling frequency, etc. By inputting control information into the measurement system, technicians can flexibly control the completion of phase measurements.

[0039] Step 303: Calculate the difference between the numerical signals of each sampling point based on the first timestamp signal and the second timestamp signal to obtain the phase difference between the first clock signal to be tested and the second clock signal to be tested at each sampling point.

[0040] In this embodiment, when sampling the numerical signals of the first counter and the second counter using a sampling clock signal, there can be multiple sampling points. Each sampling point can perform one data sampling, and each data sampling can sample the numerical signal of one first counter and the numerical signal of one second counter. The numerical signals sampled from multiple sampling points can form a timestamp signal. Thus, based on the first timestamp signal and the second timestamp signal, the difference between the numerical signals sampled at each sampling point can be calculated to obtain the phase difference between the first and second clock signals under test at each sampling point. The sign of this phase difference can represent the phase lead relationship.

[0041] In this example, the phase of the clock signal is represented by a timestamp signal, and the subtraction operation between the timestamp signals is used instead of the XOR operation of the clock signal under test. In this way, the phase difference and phase lead relationship between the two clock signals under test (clk1, clk2) can be obtained based on the difference obtained by subtraction (including positive and negative signs and specific values).

[0042] In some examples, step 303 above may include: subtracting the numerical signals of each sampling point of the second timestamp signal from the numerical signals of each sampling point of the first timestamp signal, calculating the difference between the numerical signals of each sampling point, and obtaining the phase difference between the first and second clock signals under test at each sampling point. Wherein, when the sign of the phase difference corresponding to a sampling point is positive, it indicates that the phase of the first clock signal under test leads the second clock signal under test at that sampling point. When the sign of the phase difference corresponding to a sampling point is negative, it indicates that the phase of the second clock signal under test leads the first clock signal under test at that sampling point.

[0043] In this example, each sampling point can perform one data sampling, and each data sampling can sample the numerical signals of a first counter and a second counter. The numerical signals sampled from multiple sampling points can form a timestamp signal. Therefore, the difference between the numerical signals at each sampling point can be calculated by subtracting the numerical signals at each sampling point of the second timestamp signal from the numerical signals at each sampling point of the first timestamp signal. Specifically, the subtraction operation is performed using the numerical signals sampled at the same sampling points in the first and second timestamp signals. When the sign of the phase difference value corresponding to a certain sampling point is positive, it indicates that the phase of the first clock signal under test leads the phase of the second clock signal under test at that sampling point. When the sign of the phase difference value corresponding to a certain sampling point is negative, it indicates that the phase of the second clock signal under test leads the phase of the first clock signal under test at that sampling point.

[0044] like Figure 4 As shown, Figure 4 A schematic diagram illustrating an example of the numerical mapping rule for the subtraction operation of timestamp signals corresponding to two clock signals under test.

[0045] The value range of the timestamp signal is 0 to 1. Where W represents the bit width of the timestamp signal, and the difference between the timestamp signals can be represented by a signed number, with a value range of: to .exist Figure 4 In the example shown, assuming W = 2, the timestamp signal ranges from 0 to 3. Furthermore, assuming the timestamp signal corresponding to the clock signal clk1 under test is Фclk1, and the timestamp signal corresponding to the clock signal clk2 under test is Фclk2, the numerical mapping rule for the subtraction operation between Фclk1 and Фclk2 (in this example, the subtraction operation Фclk1-Фclk2) can be as follows: Figure 4 As shown. By Figure 4It can be seen that when Фclk1 and Фclk2 are equal, the difference in timestamp signals is 0. When Фclk1 is greater than Фclk2, the difference in timestamp signals is greater than 0 (i.e., the sign is positive), indicating that clk1 leads clk2 in phase. When Фclk2 is greater than Фclk1, the difference in timestamp signals is less than 0 (i.e., the sign is negative), indicating that clk2 leads clk1 in phase.

[0046] Step 304: Perform statistical analysis on the calculated phase difference value, and determine the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results.

[0047] In this embodiment, the phase difference values ​​of each sampling point calculated in step 303 can be statistically analyzed, for example, by calculating the mean, median, mode, etc. Then, the phase difference between the first and second clock signals under test can be determined based on the statistical analysis results; for example, the statistical analysis results can be used as the phase difference. In practice, the unit of phase can include degrees and radians. Taking radians as an example, multiplying the phase difference by 2π yields the radian phase difference. By statistically analyzing the phase difference values ​​of each sampling point and determining the phase difference between the two clock signals under test based on the statistical analysis results, random jitter and noise can be effectively suppressed, making the obtained phase difference more accurate.

[0048] In some examples, step 304 above may include steps 1) and 2), specifically:

[0049] Step 1), calculate the mean of the obtained phase difference values.

[0050] In this example, for the phase difference values ​​of each sampling point calculated in step 303, the average value of the phase difference values ​​of each sampling point can be calculated.

[0051] Step 2), determine the phase difference between the first and second clock signals under test based on the mean.

[0052] In this example, the phase difference between the first and second clock signals under test can be determined based on the mean. For example, the mean can be directly used as the phase difference between the first and second clock signals under test. Alternatively, the mean can be multiplied by a preset weight to obtain the phase difference between the first and second clock signals under test. This example demonstrates how the moving average algorithm can be used to suppress random jitter and quantization noise, resulting in a more accurate calculated phase difference.

[0053] Please continue reading Figure 5 , Figure 5 This diagram illustrates an example of a timing diagram of key signals during the execution of the digital clock phase measurement method based on direct sampling technology according to this embodiment. Figure 5 In the example shown, assume the first and second clock signals under test are clk1 and clk2, respectively, where clk1 and clk2 have the same frequency but a certain phase difference. In this example, assume the first and second counters are 2-bit wide counters, generating a count range of 0-3. The rising edge of the first clock signal clk1 triggers the first counter, producing the numerical signal tstamp1 in the diagram. The rising edge of the second clock signal clk2 triggers the second counter, producing the numerical signal tstamp2 in the diagram. Then, the sampling clock signal samp_clk directly samples tstamp1 and tstamp2, respectively, obtaining the first timestamp signal tstamp1_s and the second timestamp signal tstamp2_s. In the clock domain of the sampling clock signal samp_clk, the phase difference between the first timestamp signal tstamp1_s and the second timestamp signal tstamp2_s is calculated, resulting in tstamp_diff. The values ​​in tstamp_diff are then accumulated. After a long sampling period, the average value of the accumulated result tstamp_sum can be used to characterize the phase difference between the first clock signal clk1 and the second clock signal clk2 under test.

[0054] According to another embodiment, a digital clock phase measurement system based on direct sampling technology is provided. This system can be used to achieve, for example... Figure 3 The method shown.

[0055] Figure 6 A schematic block diagram of a digital clock phase measurement system based on direct sampling technology according to one embodiment is shown. Figure 6As shown, the digital clock phase measurement system based on direct sampling technology includes: a first timestamp generation unit, a first sampler, a second timestamp generation unit, a second sampler, a difference calculation unit, an accumulator, and a post-processing unit. Specifically, the first timestamp generation unit includes a first counter, which is used to trigger the first counter based on the edge of the first clock signal under test. A first sampler includes a multi-stage cascaded D flip-flop for sampling the numerical signal of a first counter using a preset sampling clock signal as a first timestamp signal, wherein the first timestamp signal represents the phase of a first clock signal under test; a second timestamp generation unit includes a second counter for triggering the second counter based on the edge of a second clock signal under test; a second sampler includes a multi-stage cascaded D flip-flop for sampling the numerical signal of the second counter using a sampling clock signal as a second timestamp signal, wherein the second timestamp signal represents the phase of the second clock signal under test; a difference calculation unit is used to calculate the difference between the first timestamp signal and the second timestamp signal at each sampling point to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point, wherein the sign of the phase difference indicates the phase lead relationship; an accumulator and a post-processing unit are used to perform statistical analysis on the calculated phase difference values ​​and determine the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results.

[0056] like Figure 6 As shown, in the actual phase measurement process, the clock signals A and B, representing the phase difference to be measured, can first be processed by their respective timestamp generation units. Each timestamp generation unit can include a counter with a width of W bits and a counting range of 0 to 2. W -1. After the system starts phase measurement, the counters corresponding to the two clock signals under test will start counting. Each time the rising edge (or falling edge) of the clock signal under test clk_ref is triggered, the counter will perform an addition process, and the phase of the clock signal will be represented by the counter's numerical signal data_phase.

[0057] The sampler can include multiple cascaded D flip-flops to directly sample the counter's numerical signal using a sampling clock signal to obtain a timestamp signal. Since the numerical signal output from the timestamp generation unit belongs to the clock domain of the input clock signal under test, and is asynchronous with the clock domain of the sampling clock signal, using multiple cascaded D flip-flops for sampling avoids metastability issues in the circuit. Furthermore, the sampler can perform Gray code encoding and decoding on multi-bit sampled signals to prevent data errors caused by signal offsets.

[0058] The difference calculation unit performs a subtraction operation on the values ​​of the timestamp signals corresponding to the two clock signals under test to obtain the phase difference.

[0059] After subtracting the timestamps corresponding to the two clock signals under test, the accumulator can sum the signals output by the difference calculation unit. The accumulator is cleared to zero at the beginning of each measurement cycle, and at the end of the measurement cycle, the accumulated value of the accumulator is the sum of the phase differences within each measurement cycle.

[0060] An accumulator can consist of an adder and a register forming a feedback loop. It accumulates the phase difference value each clock cycle, obtaining the sum of the phase differences at the end of each measurement cycle. The accumulator accumulates the sum of discrete phase differences between the measured clock signals over a relatively long statistical period. Although this number is linearly related to the measured phase difference, the high bit depth due to potentially long sampling periods makes it inconvenient for processing programs. Therefore, a post-processing unit can perform statistical analysis (e.g., calculate the mean) on the accumulated results based on the number of sampling periods, thereby further improving measurement accuracy. For example, the post-processing unit can average the accumulated values ​​obtained from the accumulator based on the externally configured sampling period number N.

[0061] In some examples, the sampling clock signal does not have a fixed frequency and phase correlation with the first and second clock signals under test.

[0062] In some examples, the post-processing unit is further used to calculate the mean of the obtained phase difference values; and to determine the phase difference between the first and second clock signals under test based on the mean value.

[0063] See also Figure 6 , Figure 6 The digital clock phase measurement system based on direct sampling technology shown may also include a control unit for receiving control information, which includes measurement control signals and measurement parameters. The control unit can receive externally configured control information.

[0064] Those skilled in the art will understand that the exemplary components, systems, and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Whether implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. When implemented in hardware, it can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the desired tasks. The programs or code segments can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave.

[0065] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0066] In this invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations of the embodiments of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A digital clock phase measurement method based on direct sampling technology, characterized in that, The method includes: The first counter is triggered based on the edge of the first clock signal under test, and the value signal of the first counter is sampled using a preset sampling clock signal as the first timestamp signal, wherein the first timestamp signal is used to represent the phase of the first clock signal under test. The second counter is triggered based on the edge of the second clock signal under test, and the numerical signal of the second counter is sampled using the sampling clock signal as the second timestamp signal, wherein the second timestamp signal is used to represent the phase of the second clock signal under test; The difference between the numerical signals at each sampling point is calculated based on the first timestamp signal and the second timestamp signal to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point, wherein the sign of the phase difference indicates the phase lead relationship; The calculated phase difference is statistically analyzed, and the phase difference between the first clock signal under test and the second clock signal under test is determined based on the statistical analysis results.

2. The method according to claim 1, characterized in that, The sampling clock signal does not have a fixed frequency or phase correlation with the first clock signal under test and the second clock signal under test.

3. The method according to claim 1, characterized in that, The step of performing statistical analysis on the calculated phase difference value and determining the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results includes: The mean of the calculated phase difference values; The phase difference between the first clock signal under test and the second clock signal under test is determined based on the mean value.

4. The method according to claim 1, characterized in that, The edge is either a rising edge or a falling edge.

5. The method according to claim 1, characterized in that, The step of calculating the difference between the numerical signals at each sampling point based on the first timestamp signal and the second timestamp signal to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point includes: The difference between the numerical signals of the first timestamp signal and the numerical signals of the second timestamp signal at each sampling point is calculated to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point. When the phase difference corresponding to a sampling point is positive, it indicates that the phase of the first clock signal under test leads the phase of the second clock signal under test at that sampling point. When the phase difference corresponding to a sampling point is negative, it indicates that the phase of the second clock signal under test leads the phase of the first clock signal under test at that sampling point.

6. The method according to claim 1, characterized in that, Before triggering the first counter and the second counter, the method further includes: Receive control information, wherein the control information includes measurement control signals and measurement parameters.

7. A digital clock phase measurement system based on direct sampling technology, characterized in that, The system includes: The first timestamp generation unit includes a first counter, which is used to trigger the first counter based on the edge of the first clock signal under test; The first sampler includes a multi-stage cascaded D flip-flop, used to sample the numerical signal of the first counter using a preset sampling clock signal as a first timestamp signal, wherein the first timestamp signal is used to represent the phase of the first clock signal under test; The second timestamp generation unit includes a second counter, which is used to trigger the second counter based on the edge of the second clock signal to be tested; The second sampler includes a multi-stage cascaded D flip-flop for sampling the numerical signal of the second counter using the sampling clock signal as a second timestamp signal, wherein the second timestamp signal is used to represent the phase of the second clock signal under test; The difference calculation unit is used to calculate the difference between the first timestamp signal and the second timestamp signal at each sampling point, so as to obtain the phase difference between the first clock signal under test and the second clock signal under test at each sampling point, wherein the sign of the phase difference indicates the phase lead relationship; An accumulator and a post-processing unit are used to perform statistical analysis on the calculated phase difference value and determine the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results.

8. The system according to claim 7, characterized in that, The sampling clock signal does not have a fixed frequency or phase correlation with the first clock signal under test and the second clock signal under test.

9. The system according to claim 7, characterized in that, The step of performing statistical analysis on the calculated phase difference value and determining the phase difference between the first clock signal under test and the second clock signal under test based on the statistical analysis results includes: The mean of the calculated phase difference values; The phase difference between the first clock signal under test and the second clock signal under test is determined based on the mean value.

10. The system according to claim 7, characterized in that, The system also includes: A control unit is used to receive control information, wherein the control information includes measurement control signals and measurement parameters.

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