Fault detection method and system for analog circuit

Abstract

The invention provides a fault detection method and system for an analog circuit, and the method comprises the steps: obtaining a one-dimensional time sequence voltage signal outputted by a to-be-detected analog circuit in a plurality of preset fault modes, and converting the one-dimensional time sequence voltage signal into a two-dimensional detection image through employing a Grubm angle difference field; obtaining a preset fault detection model based on a double-attention residual shrinkage network, the preset fault detection model comprising a double-attention residual shrinkage block, the double-attention residual contraction block comprises a channel attention module used for adaptively calibrating the weight of a feature channel, a space attention module used for enhancing the response of a key space region in a feature map, and a soft thresholding module used for suppressing noise and retaining effective features; and inputting the two-dimensional detection image into the preset fault detection model to obtain a fault classification result of the analog circuit to be detected. According to the technical scheme, the working efficiency of analog circuit fault detection and the accuracy of a detection result can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog circuit fault detection, and particularly to an analog circuit fault detection method and system. BACKGROUND

[0002] Analog circuits are electronic circuits that process continuously varying analog signals, which are widely used in communication, control, medical electronics and other systems, and the reliability thereof is crucial to the operation of the entire device. At present, the defect detection of analog circuits includes hard fault detection and soft fault detection, wherein the commonly used method for hard fault detection is to collect the image of the analog circuit, and to use an artificial intelligence algorithm to identify defects in the image to identify defects such as breakpoints in the analog circuit.

[0003] Soft faults of analog circuits include component parameter drift, etc., and the commonly used detection method is to obtain a test signal output by the analog circuit, and to compare the test signal with a preset standard signal to determine the soft fault of the analog circuit according to the consistency of the test signal and the standard signal. This fault detection method not only has low work efficiency, but also cannot guarantee the accuracy of the detection result. SUMMARY

[0004] The present application provides an analog circuit fault detection method and system for improving the work efficiency and accuracy of analog circuit fault detection.

[0005] Specifically, in a first aspect, the present application provides an analog circuit fault detection method, comprising: obtaining a one-dimensional time sequence voltage signal output by a to-be-tested analog circuit under a plurality of preset fault modes, and converting the one-dimensional time sequence voltage signal into a two-dimensional detection image using a Gram angle difference field; obtaining a preset fault detection model based on a double-attention residual shrinkage network, which comprises an input layer, a convolution layer, a double-attention residual shrinkage block, a batch normalization layer, an activation function layer, a global average pooling layer, a full connection layer and an output layer, wherein the double-attention residual shrinkage block comprises a channel attention module for adaptive calibration of feature channel weights, a spatial attention module for enhancing the response of key spatial regions in a feature map, and a soft thresholding module for suppressing noise and retaining effective features; inputting the two-dimensional detection image into the preset fault detection model to obtain a fault classification result of the to-be-tested analog circuit.

[0006] Further, the step of obtaining a one-dimensional time sequence voltage signal output by a to-be-tested analog circuit under a plurality of preset fault modes comprises: using a set circuit simulation software to perform simulation testing on the to-be-tested analog circuit under each of the preset fault modes to obtain the one-dimensional time sequence voltage signal.

[0007] Further, the step of obtaining the preset fault detection model based on the dual attention residual shrinkage network comprises: obtaining a preset training data set, and constructing an initial fault detection model based on the dual attention residual shrinkage network; using the preset training data set to train the initial fault detection model by taking Focal Loss as a loss function, to obtain the preset fault detection model.

[0008] In a second aspect, the present application further provides a fault detection system of an analog circuit, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the fault detection method of the analog circuit according to any one of the above aspects when executing the program.

[0009] The technical scheme of the present application converts the one-dimensional time sequence voltage signals output by the analog circuit under test under multiple preset fault modes into a two-dimensional detection image by using the Gram angle difference field, so that the two-dimensional detection image pays more attention to the nonlinear characteristics of each one-dimensional time sequence voltage signal, and the preset fault detection model based on the dual attention residual shrinkage network is used to obtain the fault classification result of the analog circuit under test according to the two-dimensional detection image, which can reduce the noise interference in the signal and improve the accuracy and reliability of the fault detection of the analog circuit under test.

[0010] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of some embodiments thereof, when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0011] Some specific embodiments of the present application will be described in detail below with reference to the accompanying drawings, which are shown by way of example and not limitation. The same reference numbers in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Fig. 1 is a schematic flowchart of a fault detection method of an analog circuit according to an embodiment of the present application; Fig. 2 is a schematic diagram of a fault detection system of an analog circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] Reference will now be made to Figs. 1-2This invention describes a fault detection method and system for an analog circuit according to an embodiment of the present invention. In this description, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of that feature, that is, include one or more of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. When a feature "includes or contains" one or more of the features it encompasses, unless otherwise specifically described, this indicates that other features are not excluded and may be further included.

[0013] In the description of this embodiment, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0014] Please see Fig. 1 , Fig. 1 The diagram shown is a schematic flowchart of a fault detection method for an analog circuit in one embodiment of the present invention. This method can obtain the fault classification result of the analog circuit under test by using the one-dimensional timing voltage signal output by the analog circuit under test in a preset fault mode.

[0015] Specifically, the fault detection method in this embodiment includes the following steps: Step S101: Obtain the one-dimensional timing voltage signal output by the analog circuit under test under various preset fault modes; Step S102: Using the Gram angle difference field, the one-dimensional time-series voltage signal output by the analog circuit under test is converted into a two-dimensional detection image; Step S103: Obtain a preset fault detection model based on a dual-attention residual shrinkage network, and use the preset fault detection model to obtain the fault classification result of the simulated circuit under test based on the two-dimensional detection image of the simulated circuit under test.

[0016] In step S101 above, the analog circuit under test can be any type of circuit, such as a filter circuit, an amplifier circuit, a power management circuit, etc. In this embodiment, a four-op-amp two-stage high-pass filter circuit is used as the analog circuit under test, and its fault detection method is described in detail.

[0017] In this embodiment, multiple preset fault modes can be pre-set, including a fault-free mode, as well as multiple resistance parameter drift fault modes and capacitance parameter drift fault modes. Then, the analog circuit under test is tested under each preset fault mode, and the voltage signal output by the analog circuit under test under each preset fault mode is periodically collected within a set time period, thereby obtaining the one-dimensional time-series voltage signal output by the analog circuit under test under each preset fault mode.

[0018] In step S102 above, the one-dimensional timing voltage signal output by the analog circuit under test in each preset fault mode can be normalized first.

[0019] Taking a one-dimensional time-series voltage signal obtained under one of the preset fault modes as an example, let the one-dimensional time-series voltage signal be X, and let the i-th voltage signal in the one-dimensional time-series voltage signal X be... The largest voltage signal is The smallest voltage signal is Furthermore, after normalization, the i-th voltage signal in the one-dimensional time-series voltage signal... ,but

[0020] After normalization, the one-dimensional time-series voltage signal X is transformed into a normalized one-dimensional time-series voltage signal. Then, the normalized one-dimensional time-series voltage signal Mapped to polar coordinates, let this one-dimensional time-series voltage signal The i-th voltage signal The x-coordinate in polar coordinates is The vertical axis is ,but

[0021]

[0022] in, One-dimensional time-series voltage signal The i-th voltage signal The timestamp, where N is a constant factor of the polar coordinate range. Unlike Cartesian coordinates, polar coordinates preserve absolute time relationships.

[0023] After converting the one-dimensional time-series voltage signal under each preset fault to polar coordinates, the Gram angle difference field algorithm is used to generate a 128×128 pixel two-dimensional detection image based on the one-dimensional time-series voltage signal under each preset fault. For example, this one-dimensional time-series voltage signal Methods for converting to two-dimensional detection images include: First, based on the one-dimensional time-series voltage signal Construct a GADF matrix, where the element in the i-th row and j-th column is... ,but

[0024] The GADF matrix is ​​a symmetric matrix whose elements reflect one-dimensional time-series voltage signals. The relationship between angular differences at different points in time.

[0025] Then, the GADF matrix is ​​converted into a corresponding two-dimensional detection image. The pixel value at each position in the two-dimensional detection image corresponds to the size of the corresponding element in the GADF matrix. For example, the pixel value of the i-th row and j-th column pixel in the two-dimensional detection image can be set to... .

[0026] In this embodiment, the above method is used to obtain two-dimensional detection images of the analog circuit under test in each preset fault mode. Gram angle difference field focuses more on the nonlinear characteristics of the signal, offering significant advantages for fault diagnosis of analog circuits. Furthermore, the conversion parameters and image size can be adjusted according to the actual circuit.

[0027] In step S103 above, the preset fault detection model is a deep convolutional neural network. Its core innovation lies in the introduction of a dual-attention residual shrink block. This structure can work together to adaptively emphasize key features and suppress noise, making it particularly suitable for processing grayscale images converted from voltage signals that may contain background noise. After inputting the two-dimensional detection images of the analog circuit under test in each preset fault mode into the preset fault detection model, the convolutional layer, batch normalization layer, ReLU activation function layer, and pooling layer in the preset fault model can perform initial feature extraction on each two-dimensional detection image. Then, the dual-attention residual shrink block is used to denoise the extracted initial features, and a classifier is used to classify the analog circuit under test according to the initial features to obtain the fault type of the analog circuit under test.

[0028] Specifically, in the preset fault detection model of this embodiment, the convolutional layer can perform convolution operations on the input two-dimensional detection image to initially extract the initial features of the two-dimensional detection image, obtaining an initial feature map of the two-dimensional detection image. Then, the batch normalization layer performs batch normalization processing on the initial feature map to accelerate the training process of the preset fault detection model and improve its stability. Next, the ReLU activation function layer performs nonlinear activation on the initial feature map to introduce nonlinear features into the initial feature map, and the pooling layer further compresses the feature map size to reduce the computational load of data analysis on the initial feature map. Finally, multiple stacked dual-attention residual shrinking blocks are used to perform deep feature learning and adaptive denoising processing on the initial feature map, and a classifier is used to classify the analog circuit under test based on the initial feature map to obtain the fault classification result of the analog circuit under test.

[0029] The dual-attention residual shrinking block module in this embodiment includes a channel attention module, a spatial attention module, and a soft thresholding module, enabling adaptive optimization of the initial feature map. In the channel attention module, a global average pooling operation is first performed on the input initial feature map to generate a channel-level statistical descriptor for each channel of the initial feature map. Then, a two-layer fully connected network learns the non-linear dependencies between channels of the initial feature map based on these channel-level statistical descriptors. Finally, a sigmoid activation function is used to generate a weight vector for each channel based on these non-linear dependencies, and each channel weight vector is used to weight the corresponding feature channels of the initial feature map to achieve adaptive recalibration of the initial feature map.

[0030] In the spatial attention module, a spatial transformer structure based on large kernel convolution (e.g., using a 7×7 kernel) is adopted to perform spatial domain analysis on the initial feature map after channel weighting of the channel attention module. This is to capture the local feature correlation in the initial feature map through the wide receptive field of the convolution kernel. Then, the sigmoid function is used to activate the initial feature map based on this correlation to generate the spatial attention map of the initial feature map, thereby achieving accurate localization of the key spatial regions of the initial feature map.

[0031] In the soft thresholding module, the channel statistics of the feature magnitude in the spatial attention map of the initial feature map are first obtained through absolute value transformation and global average pooling. Then, an adaptive soft thresholding parameter is generated for each channel through a parameterized thresholding learning network, which may contain two fully connected layers and a sigmoid activation function. Finally, the feature magnitude of the initial feature map is adaptively shrunk through a continuously differentiable soft thresholding function, thereby effectively achieving a balance between noise suppression and feature enhancement of the initial feature map.

[0032] In this embodiment, the channel attention module, spatial attention module, and soft thresholding module of the dual-attention residual shrinking block can achieve end-to-end optimization through the residual connection architecture, ensuring that the network maintains gradient flow stability while achieving synergistic optimization of feature selection and noise suppression.

[0033] After denoising the initial feature map of the two-dimensional detection image using a dual-attention residual shrink block, the initial feature map is input into a classifier so that the classifier can classify the faults of the analog circuit under test based on the initial feature map to obtain the fault type of the analog circuit under test.

[0034] In this embodiment, the classifier can be the Adam classifier. The model architecture of the Adam classifier can be a convolutional neural network. The learning rate of the Adam classifier is set to 0.001. The classifier is trained using a preset classification training dataset so that the classifier can classify faults in the simulated circuit under test based on the feature map.

[0035] As can be seen from the above, this embodiment uses Gram angle difference field to convert the one-dimensional time-series voltage signal output by the analog circuit under test in various preset fault modes into a two-dimensional detection image. This two-dimensional detection image focuses more on the nonlinear characteristics of each one-dimensional time-series voltage signal. Furthermore, by using a preset fault detection model based on a dual-attention residual shrinkage network, the fault classification results of the analog circuit under test can be obtained from the two-dimensional detection image. This can reduce noise interference in the signal and improve the accuracy and reliability of fault detection of the analog circuit under test.

[0036] In some embodiments of the present invention, the method for obtaining the one-dimensional timing voltage signal output by the analog circuit under test in multiple preset fault modes in step S101 includes: The simulation circuit under test was simulated and tested under each preset fault mode using circuit simulation software to obtain the one-dimensional timing voltage signal output by the simulation circuit under test under various preset fault modes.

[0037] In this embodiment, PSpice software can be used as the simulation software for setting up the circuit. The simulation circuit of the simulation circuit under test is constructed in the simulation software according to the circuit structure of the simulation circuit under test. The parameters of the corresponding components in the simulation circuit are set according to the parameters of the components in the simulation circuit under test. Then, the simulation test of the simulation circuit under test is performed under each preset fault mode to obtain the one-dimensional timing voltage signal output by the simulation circuit under test under multiple preset fault modes.

[0038] This embodiment obtains the one-dimensional timing voltage signal output by the analog circuit under test under various preset fault modes through simulation. This not only ensures the accuracy of the voltage signal, but also improves the convenience of obtaining the voltage signal.

[0039] In some embodiments of the present invention, the method for obtaining a preset fault detection model based on a dual-attention residual shrinkage network includes: Obtain the pre-defined training dataset and construct an initial fault detection model based on a dual-attention residual shrinkage network; Focal Loss is used as the loss function, and the initial fault detection model is trained using a pre-defined training dataset to obtain a pre-defined fault detection model based on a dual-attention residual shrinkage network.

[0040] In this embodiment, the mathematical expression for Focal Loss is:

[0041] in, The loss value of the initial fault detection model. This represents the confidence level of the initial fault detection model in predicting the correct category. For category weights, For focusing parameters.

[0042] In this embodiment, Focal Loss is used as the loss function to train the initial fault detection model to obtain a preset fault detection model based on a dual-attention residual shrinkage network. This can alleviate the problem of model type imbalance and improve the model's ability to identify difficult-to-classify samples.

[0043] The flowcharts provided in this embodiment are not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in every case. Furthermore, the methods described above may include additional operations. Within the scope of the technical concept provided by the methods in this embodiment, additional variations can be made to the methods described above.

[0044] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0045] This embodiment also provides a fault detection system 30 for analog circuits. The fault detection system 30 for analog circuits may include a memory 31, a processor 32, and a computer program 11 stored in the memory 31 and running on the processor 32. The processor 32 may execute the computer program 11 to implement the steps of the fault detection method for analog circuits in any of the above embodiments.

[0046] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information from computer-readable program instructions.

[0047] The analog circuit fault detection system 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, the analog circuit fault detection system 30 can be a cloud computing node. The analog circuit fault detection system 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. The analog circuit fault detection system 30 can be implemented in a distributed cloud computing environment where tasks are performed on remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0048] The fault detection system 30 for analog circuits may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0049] The analog circuit fault detection system 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data input and output using external devices that can be connected to the computer equipment. The network adapter / interface provides communication between the computer equipment and a network, typically represented as a communication network.

[0050] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method of fault detection for an analog circuit, characterized by, The method comprises the following steps: acquiring one-dimensional time sequence voltage signals output by the analog circuit under test under multiple preset fault modes, and converting the one-dimensional time sequence voltage signals into two-dimensional detection images by using a Gram angle difference field; acquiring a preset fault detection model based on a double-attention residual shrinkage network, which comprises an input layer, a convolution layer, a double-attention residual shrinkage block, a batch normalization layer, an activation function layer, a global average pooling layer, a full connection layer and an output layer, wherein the double-attention residual shrinkage block comprises a channel attention module for adaptive calibration of feature channel weights, a spatial attention module for enhancing the response of key spatial regions in a feature map, and a soft thresholding module for suppressing noise and retaining effective features; inputting the two-dimensional detection images into the preset fault detection model to obtain a fault classification result of the analog circuit under test.

2. The method according to claim 1, wherein the step of acquiring one-dimensional time sequence voltage signals output by the analog circuit under test under multiple preset fault modes comprises: using a set circuit simulation software to perform simulation tests on the analog circuit under test under each of the preset fault modes to obtain the one-dimensional time sequence voltage signals.

3. The method according to claim 1, wherein the step of acquiring a preset fault detection model based on a double-attention residual shrinkage network comprises: acquiring a preset training data set and constructing an initial fault detection model based on the double-attention residual shrinkage network; using the preset training data set to train the initial fault detection model by taking Focal Loss as a loss function to obtain the preset fault detection model. A device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method for detecting faults of an analog circuit according to any one of claims 1-3 when executing the program. ​ 4. A fault detection system for analog circuits, characterized by ​

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