Broadband low-power-consumption receiving and transmitting shared phase shifter

Abstract

The invention discloses a broadband low-power-consumption receiving and transmitting shared phase shifter which comprises a differential signal common port, a frequency sampling and control circuit, a dual-mode orthogonal generation circuit and a passive vector modulation synthesis circuit. The differential signal common port comprises a common input / output port interface of RF + and RF-differential radio frequency signals; the frequency sampling and control circuit is composed of a frequency sampling circuit, a frequency detection circuit and a logic control unit. The dual-mode orthogonal generation circuit is composed of a frequency selection change-over switch, a multi-phase filter, a coupling transformer, a matching network 1 and a matching network 2. The passive vector modulation synthesis circuit is composed of two passive vector modulation arrays and two combining / power dividing circuits.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuit design technology, and specifically relates to a broadband low-power transceiver phase shifter. Background Technology

[0002] Phase shifters, as the core functional unit of RF transceiver front-ends, are widely used in wireless systems such as navigation, wireless communication, and low-frequency radar. Their performance directly determines the system's signal transmission quality, operating bandwidth, and battery life. With the increasing demand for low power consumption, high integration, and wide-band adaptability in wireless communication technologies and navigation and radar systems, silicon-based CMOS technology, with its advantages of controllable cost and strong compatibility, has gradually become the mainstream choice for RF phase shifter design, meeting the integration needs of various application scenarios.

[0003] However, existing phase shifters still face numerous technical bottlenecks in practical applications, making it difficult to meet the combined demands of wide bandwidth, low power consumption, and interference resistance. Firstly, their operating frequency is limited. Existing phase shifters often employ a single-structure design for their quadrature generators, preventing them from simultaneously ensuring phase consistency across a wide frequency range and hindering their adaptability to multi-band switching applications. Furthermore, the matching network between the quadrature generator and the vector modulator is typically a fixed structure, unable to dynamically adjust with the signal frequency, thus limiting the phase shifter's operating bandwidth. Secondly, redundant phase shifter designs in the transceiver channels result in high power consumption. In conventional RF transceiver front-ends, separate active phase shifters are required for the transmit and receive channels, occupying additional chip area. Moreover, the static power consumption of active phase shifters is typically 30-50mW, accounting for 25-30% of the total power consumption of the transceiver front-end. In battery-powered applications such as portable navigation devices and drone radar, this significantly shortens device runtime. Third, the 180-nm CMOS process has the problem of large parasitic capacitance. At high frequencies, parasitic parameters will introduce additional phase errors, further deteriorating the phase shifting accuracy.

[0004] The deficiencies of the existing technologies mentioned above result in shortcomings in wide-band adaptability, low-power control, and integration level of phase shifters, which restricts the performance improvement of systems such as navigation, wireless communication, and low-frequency radar. There is an urgent need for a phase shifter design scheme with wide-band adaptability, low power consumption, and high integration. Summary of the Invention

[0005] Existing RF transceiver front-end phase-shifting amplification technology has design flaws such as a lack of wideband adaptability and a lack of coordination between the phase shifter and the low-power amplifier module when adapting to various applications in the low- and mid-frequency bands.

[0006] This invention aims to address the shortcomings of existing technologies and provides the following solutions:

[0007] A broadband low-power phase shifter for both transmitting and receiving includes: a differential signal common port, a frequency sampling and control circuit, a dual-mode quadrature generation circuit, and a passive vector modulation synthesis circuit;

[0008] The differential signal common port includes a common input / output port interface for RF+ and RF- differential radio frequency signals;

[0009] The frequency sampling and control circuit consists of a frequency sampling circuit, a frequency detection circuit, and a logic control unit;

[0010] The dual-mode quadrature generation circuit consists of a frequency selective switching switch, a multiphase filter, a coupling transformer, matching network 1, and matching network 2.

[0011] The passive vector modulation synthesis circuit consists of two passive vector modulation arrays and two combiner / power divider circuits.

[0012] Preferably, in the frequency sampling and control circuit:

[0013] The frequency sampling circuit adopts a parallel coupling method of transmission lines to couple out a small-amplitude radio frequency sampling signal from the main radio frequency path;

[0014] The frequency detection circuit consists of a buffer amplifier and an RC low-pass filter. The buffer amplifier receives a weak radio frequency sampling signal, amplifies the amplitude, and then outputs it to the RC low-pass filter. The cutoff frequency of the RC filter is 6GHz. Radio frequency signals below 6GHz can pass through with low loss, while signals above 6GHz have greater attenuation.

[0015] The logic control unit consists of a voltage comparator and a first inverter, and the radio frequency signal is processed by the RC low-pass filter. The voltage is input to the voltage comparator and compared with the set fixed reference voltage. Compare the results and output logic levels based on the comparison results. Then the logic level The input is fed into the first inverter to obtain the inverted level. .

[0016] Preferably, in the dual-mode quadrature generation circuit:

[0017] The frequency selection switch is composed of 8 MOS transistors and 4 second inverters. The differential RF signal at the differential signal common port is divided into two paths and connected to the input of the frequency selection switch. The two output paths are respectively connected to the coupling transformer and the multiphase filter.

[0018] The coupling transformer is composed of stacked metal inductor coils of different layers. The differential radio frequency signal is input from the RF+ and RF- ports and will be divided into I-path (I+, I-) and Q-path (Q+, Q-) signals with the same amplitude and a 90° phase difference.

[0019] The multiphase filter consists of a network of parallel resistors R0 and capacitors C0. The differential radio frequency signal is input from the RF+ and RF- ports and will be divided into I-path (I+, I-) and Q-path (Q+, Q-) signals with the same amplitude and a 90° phase difference.

[0020] The matching network 1 consists of a primary inductor coil L1 and a secondary inductor coil L2, and is used for impedance matching between the coupling transformer and the passive vector modulation array.

[0021] The matching network 2 consists of resistors R1 and R2, as well as parallel capacitors C1 and C2, and is used for impedance matching between the polyphase filter and the passive vector modulation array.

[0022] Preferably, in the passive vector modulation synthesis circuit:

[0023] The two passive vector modulation arrays are divided into I-path and Q-path. Each passive vector modulation array consists of 6 modulator units connected in parallel. The differential pair MOS transistors in each modulator unit have different sizes. The passive vector modulator arrays of the I-path and Q-path have the same structure.

[0024] The two passive vector modulation arrays are respectively connected to a transceiver switching switch via two combiner / power divider circuits, and the transceiver switching switch is also connected to a transmitting antenna and a receiving antenna.

[0025] Preferably, the modulator unit comprises the differential pair MOS transistors and the compensation capacitor array C. b_1 Compensation capacitor array C b_2 V C1 Switch, V C2 Switches and MOSFETs M b composition;

[0026] The differential radio frequency signal is transmitted between the source and drain of the differential pair MOSFET. The gate of the differential pair MOSFET is connected to a digital control level. When the digital control level is high, the differential pair MOSFET is turned on, and the differential radio frequency signal can be transmitted. When the digital control level is low, the differential pair MOSFET is turned off, and the differential radio frequency signal cannot pass through this unit.

[0027] The differential RF path of the modulator unit is connected in parallel with the compensation capacitor array C. b_1 and the compensation capacitor array C b_2 Through the VC1 Switch and the V C2 The switching is controlled by adjusting the voltage level of the switch, and switching is performed according to the operating frequency to compensate for the parasitic capacitance of the differential pair MOSFET.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] This invention proposes a low-power phase-shifting circuit for shared transmit and receive channels based on 180nm CMOS technology. A dual-mode quadrature generator connected to an adjustable matching network is designed to achieve stable coverage and high-precision phase adjustment across a wide frequency band of 1-10GHz. Simultaneously, the transceiver channel architecture is simplified, reducing overall power consumption. Furthermore, compensation is provided for the large parasitic capacitance of MOS transistors in the 180nm CMOS process. Attached Figure Description

[0030] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the phase shifter structure according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the frequency sampling and control circuit structure according to an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the frequency selection switching switch structure according to an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the coupling transformer structure according to an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the polyphase filter structure according to an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the matching network 1 structure according to an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the matching network 2 structure according to an embodiment of the present invention;

[0038] Figure 8 This is a schematic diagram of the passive vector modulation array structure according to an embodiment of the present invention;

[0039] Figure 9 This is a schematic diagram illustrating the basic principle of vector synthesis phase shifting in an embodiment of the present invention;

[0040] Figure 10 The following is a schematic diagram of the simulation results of the phase shifter in an embodiment of the present invention, wherein (a) is a schematic diagram of different phase shift degrees in the range of 1-10 GHz, and (b) is a schematic diagram of the difference between the simulated phase shift degree and the ideal phase shift degree. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Example

[0044] In this embodiment, as Figure 1 As shown, a broadband low-power phase shifter for both transmitting and receiving includes: a differential signal common port, a frequency sampling and control circuit, a dual-mode quadrature generation circuit, and a passive vector modulation synthesis circuit.

[0045] The differential signal common port includes a common input / output port interface for the RF+ and RF- differential radio frequency signals. In this embodiment, the differential signal common port uses an RF differential transmission line with a characteristic impedance of 50Ω.

[0046] The frequency sampling and control circuit consists of a frequency sampling circuit, a frequency detection circuit, and a logic control unit, such as... Figure 2 As shown. In the frequency sampling and control circuit:

[0047] The frequency sampling circuit uses a parallel coupling method with a 50Ω transmission line to couple a small-amplitude RF sampling signal from the main RF path. The coupling amount is very small (generally less than -20dB), so it has virtually no impact on the signal of the main RF path. One end of the sampling coupling line is grounded through a 50-ohm resistor, and the other end is output to the buffer amplifier.

[0048] The frequency detection circuit consists of a buffer amplifier and an RC low-pass filter. The buffer amplifier uses a MOSFET single-ended common-source amplifier structure, and the RC low-pass filter has a 100Ω resistor and a 200F capacitor. After the buffer amplifier receives a weak RF sampling signal, it amplifies the amplitude and then outputs it to the RC low-pass filter. The cutoff frequency of the RC filter is 6GHz. RF signals below 6GHz can pass through with low loss, while signals above 6GHz experience significant attenuation.

[0049] The logic control unit consists of a voltage comparator and a first inverter, and the radio frequency signal is processed by an RC low-pass filter. The input is fed into the voltage comparator and compared with the set fixed reference voltage. Comparison ( The specific settings need to be determined in advance based on the amplitude of the RF signal. RF signals with frequencies below 6GHz experience very little attenuation through the RC filter, and their amplitude will be greater than the reference voltage. However, radio frequency signals with frequencies higher than 6 GHz experience significant attenuation through the RC filter, resulting in amplitudes lower than the reference voltage. At this time, the voltage comparator outputs a logic level based on the comparison result. Greater than the reference voltage Time output =High level, less than the reference voltage Time output =Low level. Output logic level based on the comparison result. Then logic level The input is given to the first inverter to obtain the inverted level. Logic level and its inverting level This will serve as the control level to be used when switching the frequency selection switch in the future.

[0050] The specific workflow of this module includes: sampling the frequency signal via coupling on the main RF circuit, amplifying the signal through a buffer amplifier, and then transmitting it to an RC low-pass filter. Signals with frequencies below 6GHz pass through the filter and are output to a voltage comparator. Greater than (Fixed reference voltage), the comparator output high logic control level (e.g., Signals with frequencies above 6 GHz (≥1.0V) are attenuated by a filter and output to a voltage comparator. Less than (Fixed reference voltage), the comparator outputs a low logic control level (e.g., ≤0.2V). Logic control level. Used and its inverted level Used for switching frequency selection switches in the main circuit.

[0051] The dual-mode quadrature generator circuit consists of a frequency selective switch, a multiphase filter, a coupling transformer, matching network 1, and matching network 2. In the dual-mode quadrature generator circuit:

[0052] The frequency selection switch consists of eight MOSFETs and four second inverters, such as... Figure 3As shown, the common port differential positive terminal COM+ splits into two transmission lines. One line connects to the drain of MOSFET M1, with the source of M1 connected to the positive terminal of the output coupling transformer. The other line connects to the drain of MOSFET M5, with the source of M5 connected to the positive terminal of the output multiphase filter. Similarly, the common port differential negative terminal COM- also splits into two transmission lines. One line connects to the drain of MOSFET M2, with the source of M2 connected to the negative terminal of the output coupling transformer. The other line connects to the drain of MOSFET M6, with the source of M6 connected to the negative terminal of the output multiphase filter. The drain of MOSFET M3 is connected to the positive terminal of the output coupling transformer, and its source is grounded. The drain of MOSFET M4 is connected to the negative terminal of the output coupling transformer, and its source is grounded. The drain of MOSFET M7 is connected to the positive terminal of the output multiphase filter, and its source is grounded. The drain of MOSFET M4 is connected to the negative terminal of the output multiphase filter, and its source is grounded. The logic control level... The second inverter N1 is connected to its input terminal, and its output terminal is connected to the gates of M1 and M2, as well as the input terminal of the second inverter N2. The output terminal of the second inverter N2 is connected to the gates of M3 and M4; the logic controls the inverted level. The second inverter N3 is connected to the input terminal of the second inverter N3. The output terminal of the second inverter N3 is connected to the gates of M5 and M6, and the input terminal of the second inverter N4 is connected to the gates of M7 and M8.

[0053] The differential RF signal at the differential signal common port is divided into two paths, which are connected to the input of the frequency selection switch. The two output paths are connected to the coupling transformer and the multiphase filter, respectively. The design of each switch is the same. M1~M8 are MOS transistors with a gate width of 60μm. The on / off state of the MOS transistors is controlled by the gate level.

[0054] Specifically, logic control levels Used and its inverted level These are used to control the MOSFET switches of the upper and lower RF paths respectively; when When it is high (RF signal frequency < 6GHz), its inverted level When the voltage is low, transistors M1, M2, M7, and M8 are cut off, while transistors M3, M4, M5, and M6 are turned on. The path connecting the coupling transformer is broken, while the path of the multiphase filter is turned on. When... When it is low (RF signal frequency > 6GHz), its inverted level When the signal is high, transistors M1, M2, M7, and M8 are turned on, while transistors M3, M4, M5, and M6 are turned off. The path connecting the coupling transformer is open, while the path of the multiphase filter is closed; thus, the switch selection function is achieved.

[0055] Coupling transformers, such as Figure 4As shown, it is composed of stacked metal inductors of different layers, with a wire width of 10μm and an overall coil size of 200μm×220μm. Differential radio frequency signals are input from the RF+ and RF- ports and are output as I-path (I+, I-) and Q-path (Q+, Q-) signals with the same amplitude but a 90° phase difference.

[0056] polyphase filters such as Figure 5 As shown, the multiphase filter consists of a network of parallel resistors R0 and capacitors C0. The resistor R0 = 150Ω and the capacitor C0 = 200f. The differential positive signal RF+ port is split into two paths via a microstrip line (50Ω characteristic impedance): one path is connected in series with resistor R0. 01 After passing through node a, R is connected in series. 02 One path is connected to the positive signal non-inverting output terminal I+; the other path is connected in series with resistor R. 03 After passing through node b, R is connected in series. 04 The positive signal quadrature output terminal Q+ is connected to the positive signal quadrature output terminal; the differential negative signal RF- port is split into two paths through a microstrip line (50Ω characteristic impedance); one path is connected in series with a resistor R. 05 After passing through node c, R is connected in series. 06 One path is connected to the negative signal non-inverting output terminal I−; the other path is connected in series with resistor R. 07 After passing through node d, R is connected in series. 08 Connect to the negative signal quadrature output terminal Q−; capacitor C 01 Connected between RF+ port and node b; capacitor C 02 Connected between node a and output terminal Q+; capacitor C 03 Connected between the RF+ port and node c; capacitor C 04 Connected between node b and output terminal I−; capacitor C 05 Connected between the RF-port and node d; capacitor C 06 Connected between node c and output terminal Q−; capacitor C 07 Connected between the RF-port and node a; capacitor C 08 It is connected between node d and output terminal I+. The differential RF signal is input from the RF+ and RF- ports and will be split into I-path (I+, I-) and Q-path (Q+, Q-) signals with the same amplitude and a 90° phase difference.

[0057] Matching network 1, such as Figure 6 As shown, the frequency matching is 6-10GHz, and an inductor matching method is used. It consists of a primary inductor L1 and a secondary inductor L2. The inductance of L1 is 1nH and the inductance of L2 is 0.3nH. It is used for impedance matching between the coupling transformer and the passive vector modulation array. Using inductors is more effective and the size is not too large.

[0058] Matching Network 2, such as Figure 7As shown, the frequency matching is 1-6GHz, using a resistor-capacitor matching network, consisting of resistors R1 and R2, and parallel capacitors C1 and C2 (where the resistance of resistor R1 is equal to that of resistor R2, both 220Ω, and the capacitance of parallel capacitors C1 and C2 is equal to that of parallel capacitors C2, both 500F). This network is used for impedance matching between a polyphase filter and a passive vector modulation array. Since low-frequency inductors are large, using a resistor-capacitor matching network provides better area and performance.

[0059] The passive vector modulation combining circuit consists of two passive vector modulation arrays and two combiner / power divider circuits. In the passive vector modulation combining circuit:

[0060] Two passive vector modulation arrays are divided into I-path and Q-path. Each passive vector modulation array consists of 6 modulator units connected in parallel. The differential pair MOS transistors in each modulator unit have different sizes (from unit 1 to unit 6, the MOS transistors have different sizes). a_1 ~M a_6 The gate widths / lengths are 2μm / 300nm, 4μm / 300nm, 8μm / 300nm, 16μm / 300nm, 32μm / 300nm, and 64μm / 300nm, respectively. The passive vector modulator arrays for the I and Q paths have the same structure.

[0061] Modulator unit such as Figure 8 As shown, the differential pair MOS transistors (M a_i (i from 1 to 6), compensation capacitor array C b_1 Compensation capacitor array C b_2 V C1 Switch, V C2 Switches and MOSFETs M b composition;

[0062] The differential RF signal is transmitted between the source and drain of the differential pair MOSFETs. The gate of the differential pair MOSFETs is connected to a digital control level. When the digital control level is high, the differential pair MOSFETs are turned on, and the differential RF signal can be transmitted. When the digital control level is low, the differential pair MOSFETs are turned off, and the differential RF signal cannot pass through this unit. The differential RF path of the modulator unit is connected in parallel with a compensation capacitor array C. b_1 and compensation capacitor array C b_2 (Compensation capacitor array C) b_1 The capacitance is 100F, and the compensation capacitor array C b_2 The capacitance is 200f), through V C1 Switch and V C2 The switching is controlled by the voltage level of the switch, and switching is performed according to the operating frequency (V). C1 Switch and V C2The switch can have four combinations of equivalent parallel capacitors to compensate for the parasitic capacitance of the differential pair MOSFET.

[0063] The differential pair MOSFETs of these 6 modulator units a_i The gate width-to-length ratio (W / L) of the MOSFETs differs, and the relationship between the current IDS through the source-drain junction and the MOSFET width-to-length ratio is shown in the formula: Where VDS represents the drain-source voltage of the MOSFET, μ n C represents the carrier mobility of a MOSFET. ox V represents the gate oxide capacitance density of a MOS transistor. GS V represents the gate-source voltage of a MOSFET. th This represents the threshold voltage of the MOSFET; therefore, the source-drain current of the MOSFET is proportional to the width-to-length ratio of the MOSFET. The total current of the modulator array is the sum of the source-drain currents (IDS) of the differential MOSFETs in each modulator unit. Different total currents can be obtained by varying the digital control level (CTR_i) of each unit; there are 2... 6 =64 types, therefore, for the I-path and Q-path modulator arrays, there are 64 different combinations of total current. According to the appendix Figure 9 The working principle of the vector synthesis phase shifter (adjusting the signal amplitudes I0 and Q0 of the mutually orthogonal I and Q paths; the synthesized signal amplitude R and phase θ can be calculated using the formulas in the attached diagram; the signal amplitudes I0 and Q0 of the I and Q paths are respectively the total currents of the passive modulator arrays of the I and Q paths). The signal amplitudes of the I and Q paths determine the amplitude R and phase θ of the synthesized RF signal. Therefore, different combinations of the total output currents I0 and Q0 of the I and Q path modulator arrays can obtain different phase shifts θ. Thus, we can control the control CTR_i of the I and Q paths to select the desired phase shift.

[0064] Two passive vector modulation arrays are connected to a transmit / receive switching switch via two combiner / power divider circuits. The transmit / receive switching switch is also connected to the transmit antenna and the receive antenna.

[0065] The phase shifter of this invention was simulated, and the results are attached. Figure 10 As shown; Figure 10 (a) shows the different phase shift degrees simulated in the 1-10GHz range. The phase shift range was selected from the minimum phase shift step of 5.626° to the maximum step of 354.375°, covering the range of 0~360°. The minimum phase shift step of 5.626° meets the performance requirements of a 6-bit phase shifter. Figure 10 Figure (b) shows the root mean square (RMS) error curve (1-10GHz) calculated based on the difference between the simulated phase shift degree and the ideal phase shift degree. The formula for calculating the root mean square error is:

[0066]

[0067] Among them, X i The value represents the difference between the simulated phase shift degree and the ideal phase shift degree, and N represents the total number of phase shift states. The error curve shows that the error is less than 1.8° within a wide bandwidth of 1-10 GHz, indicating excellent phase shift accuracy.

[0068] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A wideband low-power consumption transceiver-shared phase shifter, characterized by, The application relates to a differential signal common port, a frequency sampling and control circuit, a dual-mode quadrature generating circuit and a passive vector modulation synthesis circuit. The differential signal common port comprises a common input / output port interface of RF+ and RF- differential radio frequency signals. The frequency sampling and control circuit comprises a frequency sampling circuit, a frequency detection circuit and a logic control unit. The dual-mode quadrature generating circuit comprises a frequency selection switch, a polyphase filter, a coupling transformer, a matching network 1 and a matching network 2. The passive vector modulation synthesis circuit comprises two passive vector modulation arrays and two combining / dividing circuits. In the frequency sampling and control circuit:

2. The wideband low-power transceiver shared phase shifter of claim 1, wherein, The frequency sampling circuit adopts a parallel coupling mode of a transmission line to couple a small-amplitude radio frequency sampling signal from a radio frequency main path; The frequency detection circuit comprises a buffer amplifier and an RC low-pass filter; the buffer amplifier inputs the weak radio frequency sampling signal, performs amplitude amplification and then outputs the signal to the RC low-pass filter; the cut-off frequency of the RC filter is 6GHz; radio frequency signals lower than 6GHz can pass through with low loss, and signals higher than 6GHz are greatly attenuated; In the dual-mode quadrature generating circuit: The logic control unit is composed of a voltage comparator and a first inverter, the radio frequency signal processed by the RC low-pass filter is input into the voltage comparator and compared with a set fixed reference voltage , and a logic level is output according to the comparison result , then the logic level is input into the first inverter to obtain an inverted level .

3. The wideband low-power phase shifter for transceiver sharing according to claim 2, wherein, The frequency selection switch comprises eight MOS tubes and four second inverters; the differential radio frequency signals of the differential signal common port are divided into two paths and connected to the input end of the frequency selection switch; the two paths of the output end are connected to the coupling transformer and the polyphase filter respectively; The coupling transformer is composed of metal inductance coils in different layers which are stacked up and down; the differential radio frequency signals input from the RF+ and RF- ports are divided into I path (I+, I-) and Q path (Q+, Q-) signals with the same amplitude and a 90-degree phase difference; The polyphase filter is composed of a network of parallel resistors R0 and capacitors C0; the differential radio frequency signals input from the RF+ and RF- ports are divided into I path (I+, I-) and Q path (Q+, Q-) signals with the same amplitude and a 90-degree phase difference; The matching network 1 is composed of a primary inductance coil L1 and a secondary inductance coil L2 and is used for impedance matching between the coupling transformer and the passive vector modulation array; The matching network 2 is composed of resistors R1 and R2 and parallel capacitors C1 and C2 and is used for impedance matching between the polyphase filter and the passive vector modulation array. In the passive vector modulation synthesis circuit:

4. The wideband low-power phase shifter for transceiver sharing according to claim 3, wherein, The two passive vector modulation arrays are divided into I path and Q path; each passive vector modulation array is composed of six parallel modulator units; the differential MOS tubes in each modulator unit are different in size; the structures of the passive vector modulation arrays in the I path and the Q path are consistent; The two passive vector modulation arrays are connected to a transceiving switch through two combining / dividing circuits; the transceiving switch is also connected to a transmitting antenna and a receiving antenna. ​ 5. The wideband low-power phase shifter for transceiver sharing according to claim 4, wherein, The modulator unit is composed of the differential pair MOS transistor, the compensation capacitor array C b_1 , the compensation capacitor array C b_2 , the V C1 switch, the V C2 switch and the MOS transistor M b ​ The differential radio frequency signal is transmitted between the source-drain of the differential pair MOS transistor, the gate of the differential pair MOS transistor is connected with a digital control level, when the digital control level is high, the differential pair MOS transistor is turned on, the differential radio frequency signal can be transmitted, when the digital control level is low, the differential pair MOS transistor is turned off, the differential radio frequency signal cannot be transmitted through the unit; The differential radio frequency path of the modulator unit is connected in parallel with the compensation capacitor array C b_1 and the compensation capacitor array C b_2 , through the V C1 switch and the V C2 switch, the voltage high and low of the switch control, according to the working frequency respectively switch, compensate the parasitic capacitance of the differential pair MOS tube.

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