Abnormal data real-time filtering method and system based on edge calculation in dynamic environment system

Abstract

The invention discloses an abnormal data real-time filtering method and system based on edge computing in a dynamic environment system, the method is executed by an edge computing gateway, sliding window weighted average preprocessing is equivalently realized by adopting integer shift operation, and the single computing overhead is controlled within 50 clock cycles; dynamically and adaptively adjusting dynamic reference model parameters based on the ratio of the network load to the sensor sampling frequency; performing multi-stage anomaly filtering of a hard threshold value, a mutation rate and a statistical interval on the data through a three-stage pipeline judgment structure executed by atomization; an FPGA hardware queue manager independent of a main processor bypasses a TCP stack to push abnormal data at the highest priority, and redundant data is stored in a zero-copy annular buffer area managed by DMA. According to the invention, the problems of intranet congestion, server I / O bottleneck and alarm delay under the centralized architecture of the traditional dynamic loop system are solved, and the fault, fault, fault, fault, fault and fault are realized on resource-limited platforms such as Cortex-M4 and the like; the average alarm delay is 8 milliseconds; and the data compression rate is more than 90%.

Description

Technical Field

[0001] This invention relates to the field of edge computing technology for the Internet of Things, and in particular to a method and system for real-time filtering of abnormal data based on edge computing in an environmental system. Background Technology

[0002] The existing centralized data processing model has the following significant drawbacks when deployed on a large scale within an intranet (such as a large campus or a network of multiple data centers):

[0003] Inefficient use of internal network bandwidth resources can easily trigger broadcast storms: In large data centers, thousands of sensors upload "normal and unchanging" data (such as long-term constant voltage, temperature, and humidity values). This redundant data consumes a significant amount of bandwidth from internal network switches. During network fluctuations or mass device restarts, this massive amount of concurrent data can easily cause network congestion or broadcast storms, blocking the issuance of normal reverse control commands (such as remote power on / off).

[0004] Central server I / O bottleneck and storage waste: All raw data, regardless of its value, must be written to the central database, resulting in persistently high database write concurrency (IOPS). Disk space is quickly filled with massive amounts of redundant historical data, which not only greatly increases the cost of purchasing storage hardware but also severely slows down the efficiency of historical data querying and report generation.

[0005] Alarm response suffers from queuing delays: Since all anomaly judgment logic relies on the central server, when massive amounts of data arrive concurrently, the server processing queue becomes long, causing alarm commands for emergency faults such as fires, power outages, and water leaks to be unable to be calculated and issued within milliseconds, posing a security risk.

[0006] Single point of failure leads to monitoring blind spots: Once the internal network backbone link is interrupted or the central server crashes, the front-end FSU will be unable to make local judgments, causing the entire monitoring system to be paralyzed, unable to trigger audible and visual alarms on site, and unable to record data during the failure period. Summary of the Invention

[0007] The purpose of this invention is to provide a real-time filtering method and system for abnormal data based on edge computing in a dynamic environmental system, thereby solving the aforementioned problems existing in the prior art.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A real-time filtering method for abnormal data based on edge computing in a dynamic environmental system includes the following steps:

[0010] S100. The edge computing gateway periodically collects raw data sequences from the underlying sensors and performs sliding window weighted average preprocessing on the raw data to obtain the preprocessed value at the current time. The edge computing gateway uses fixed-point arithmetic to implement sliding window weighted average preprocessing, converting the floating-point smoothing coefficient α into an integer shift operation, so that a single preprocessing calculation consumes less than 50 CPU cycles. Specifically, the integer shift operation is mapped as follows: when α=0.2, it is mapped to a right shift of 3 bits; when α=0.3, it is mapped to a right shift of 2 bits followed by a right shift of 4 bits. The mapping relationship is automatically configured according to the preset smoothing coefficient when the edge computing gateway starts by using a lookup table.

[0011] S200. Store historical data for the most recent N time periods in the local memory of the edge computing gateway, calculate dynamic feature values ​​in real time, and build a dynamic benchmark model. The determination of the N time periods adopts an adaptive adjustment mechanism: the edge computing gateway dynamically adjusts the value of N according to the ratio of the current network load L to the sensor sampling frequency F. When L / F>10, N is reduced to 5 minutes, and when L / F<1, N is extended to 15 minutes. The adaptive adjustment mechanism is triggered by the load monitoring interrupt service routine of the edge computing gateway at the end of each heartbeat cycle.

[0012] S300, based on a dynamic benchmark model, executes a multi-level anomaly filtering strategy on the current preprocessed value, classifying the data into first-level anomalies, second-level anomalies, or redundant data. The multi-level anomaly filtering strategy adopts a three-level pipelined decision structure: the first level is a hard threshold comparator, the second level is a mutation rate accumulator, and the third level is a statistical interval discriminator. The three-level pipelined decision structure is executed atomically within the hardware timer interrupt of the edge computing gateway, ensuring that the decision process cannot be preempted by other tasks.

[0013] S400: Perform differentiated data transmission based on classification results: If it is a Level 1 or Level 2 anomaly, the edge computing gateway immediately pushes the data to the central server with the highest priority through the priority queue controller. The highest priority push bypasses the TCP stack regular queue and sends directly. The priority queue controller is an independent FPGA logic unit, which integrates 8 levels of hardware queues. Each level of queue is configured with an independent DMA descriptor ring. The highest priority data is directly written to the Level 0 DMA descriptor ring and triggers the network card hardware transmission interrupt. If it is redundant data, it is temporarily stored in the local cache. The local cache adopts a zero-copy ring buffer structure. The buffer head pointer is directly managed by the edge computing gateway's DMA controller to avoid CPU participation in memory copying.

[0014] The S500 edge computing gateway monitors the connection status with the central server in real time through a heartbeat monitoring link. When an intranet connection interruption is detected, it automatically switches to autonomous mode, directly drives the GPIO interface to control peripheral audible and visual alarm devices according to local policies, and writes key abnormal data into local non-volatile memory. After the network is restored, the backlogged alarm data is uploaded first. The heartbeat monitoring link adopts a bidirectional UDP heartbeat mechanism with a heartbeat period of 500 milliseconds. Three consecutive timeouts are considered as intranet connection interruptions. The bidirectional UDP heartbeat packet payload carries the current backlog of data B of the edge computing gateway and the processing queue length Q of the central server. The central server dynamically adjusts the heartbeat period according to the Q value. When Q>1000, the heartbeat period is actively extended to 1000 milliseconds to reduce network pressure.

[0015] Preferably, in fixed-point arithmetic, when α = 0.2~0.3, the specific mapping relationship configured by the lookup table method is as follows:

[0016] α = 0.2 → Shift right by 3 bits;

[0017] α = 0.25 → Shift right by 2 bits;

[0018] α = 0.3 → Right shift by 2 bits, then subtract the value after right shift by 4 bits;

[0019] The lookup table method is stored in the startup configuration Flash of the edge computing gateway, occupying 16 bytes of space, and is loaded into the CPU's instruction cache by the BootLoader during system power-on initialization.

[0020] Preferably, in the adaptive adjustment mechanism, the network load L is calculated by the edge computing gateway by monitoring the queue length of data packets to be sent per unit time. The sensor sampling frequency F is a system preset value. The ratio of network load L / sensor sampling frequency F is stored in 16-bit fixed-point format. The load monitoring interrupt service routine is executed once every 500 milliseconds. The N value is updated according to the ratio of network load L / sensor sampling frequency F, and the sliding window size is adjusted synchronously. The adjustment of the sliding window size is achieved by modifying the modulus of the circular buffer pointer, without the need to reallocate memory.

[0021] Preferably, the three-stage pipelined decision structure in the Cortex-M4 core achieves atomic execution in the following way:

[0022] The three functions—hard threshold comparator, mutation rate accumulator, and statistical interval discriminator—are encapsulated into an inline assembly code block, and global interrupts are disabled before execution using the __disable_irq() instruction.

[0023] After the decision is completed, interrupts are restored by __enable_irq() to ensure that the entire decision process is executed continuously on the CPU pipeline, cannot be preempted, and the time window for atomic execution is less than 12 microseconds.

[0024] Preferably, in the FPGA logic unit, the DMA descriptor ring of the 8-level hardware queue is configured as follows:

[0025] Level 0: Dedicated to abnormal data, 128 descriptors, each descriptor points to a 2KB data buffer;

[0026] Levels 1-6: Normal business data, 64 descriptors per level;

[0027] Level 7: Redundant data, 32 descriptors, uploaded in batches only when the network is idle;

[0028] The descriptor ring is allocated in the FPGA's internal Block RAM and interacts with the CPU via the AXI4-Lite bus.

[0029] Preferably, the head pointer of the zero-copy circular buffer is automatically updated by the DMA controller, specifically implemented as follows:

[0030] The DMA engine of the edge computing gateway's network card is configured in receive-direction circular buffer mode. When redundant data is received, the DMA engine writes the data to the current write pointer position. The write pointer is automatically incremented by 1 and wraps around. The CPU obtains the data position by reading the write pointer register without executing any memory copy instructions.

[0031] Preferably, the current data backlog B and the central server processing queue length Q carried in the bidirectional UDP heartbeat packet payload are encoded in TLV format, where:

[0032] Type=0x01, Length=4 bytes, Value=B;

[0033] Type=0x02, Length=4 bytes, Value=Q;

[0034] The heartbeat packet is sent in user space by the FPGA logic unit of the edge computing gateway via RDMA (Remote Data Interchange), bypassing the kernel network protocol stack.

[0035] An environmental monitoring data processing system based on the same concept includes:

[0036] The edge computing gateway, deployed at the monitoring site, integrates a real-time operating system, non-volatile Flash memory, and a priority queue controller. The real-time operating system is configured with an interrupt response time of less than 10 microseconds and a task scheduling cycle accurate to 1 millisecond. The priority queue controller is an independent FPGA logic unit configured to perform data push bypassing the TCP stack in step S400. The edge computing gateway's CPU core is a Cortex-M4 with a main frequency of 168MHz. When performing sliding window weighted average preprocessing, it maps the floating-point smoothing coefficient α to integer shift operations, so that a single preprocessing calculation consumes 42 clock cycles, which is equivalent to an execution time of 250 nanoseconds.

[0037] The central server is configured to receive and process priority-tagged data packets from the edge computing gateway. These packets contain exception data that is sent directly by bypassing the TCP stack. The central server's data receiving thread uses memory-mapped I / O technology to directly map the network card's receive buffer to the user-space memory space, bypassing the kernel protocol stack parsing and making the average data write latency less than 50 microseconds.

[0038] The heartbeat monitoring link is used for bidirectional heartbeat detection. The heartbeat monitoring link is implemented in user space through raw sockets. The sending and receiving of heartbeat packets bypasses the kernel TCP / IP protocol stack and is directly processed by the FPGA logic unit of the edge computing gateway, ensuring that the heartbeat detection latency is less than 5 milliseconds.

[0039] Preferably, the memory-mapped I / O technology is specifically implemented as follows:

[0040] The central server maps the receive buffer (BAR) space of the PCIe network card to the user-mode address space of the monitoring process through the mmap() system call. The monitoring process detects buffer updates in a polling rather than interrupt manner. When the FPGA logic unit writes a data packet, the monitoring process reads the data through the CAS atomic instruction, reducing the data write latency from the traditional 200 microseconds to 45 microseconds.

[0041] Preferably, the FPGA logic unit of the heartbeat monitoring link integrates a heartbeat state machine. The state machine contains four states: IDLE, SEND, WAIT, and TIMEOUT. The state transition is driven by a 500-millisecond hardware timer. After three consecutive timeouts, the state machine outputs a network disconnection signal. The network disconnection signal directly triggers the GPIO to drive the relay controller without CPU intervention, ensuring that the time from network disconnection to the triggering of the audible and visual alarm is less than 15 milliseconds.

[0042] The beneficial effects of this invention are:

[0043] (1) Significantly reduce central server I / O load and storage costs: Through edge filtering, the amount of data entering the central database is reduced by more than 90%, which greatly alleviates the database write pressure (IOPS), extends the life of the server hard disk, and saves a lot of storage hardware expansion costs.

[0044] (2) Eliminate the risk of intranet congestion: effectively avoid intranet broadcast storms caused by massive sensors reporting data at the same time, and ensure the stability of critical control commands in the network transmission.

[0045] (3) Improve system scalability: Due to the significant reduction in server resources occupied by a single FSU, the number of edge nodes that a single central server can manage can increase exponentially, reducing the server investment required for large-scale networking.

[0046] (4) Improve the real-time performance and reliability of alarms: Anomaly detection is moved to the edge, eliminating the delay caused by network transmission and server queuing; at the same time, the network outage self-governance function ensures the monitoring security in extreme situations. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the real-time filtering method for abnormal data based on edge computing in the dynamic environmental system provided by an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0049] Reference Figure 1 The method for real-time filtering of abnormal data based on edge computing in a dynamic environmental system includes the following steps: S100, the edge computing gateway periodically collects raw data sequences from the underlying sensors and performs sliding window weighted average preprocessing on the raw data to obtain the preprocessed value at the current time. The edge computing gateway uses fixed-point arithmetic to implement sliding window weighted average preprocessing, converting the floating-point smoothing coefficient α into an integer shift operation, so that a single preprocessing calculation consumes less than 50 CPU cycles. Specifically, the integer shift operation is as follows: when α=0.2, it is mapped to a right shift of 3 bits (equivalent to 1 / 8); when α=0.3, it is mapped to a right shift of 2 bits followed by a right shift of 4 bits (equivalent to 1 / 4-1 / 16=3 / 16). The mapping relationship is automatically configured according to the preset smoothing coefficient when the edge computing gateway starts by using a lookup table.

[0050] This step specifically involves: Step S100, which involves the edge computing gateway periodically acquiring and preprocessing the raw data sequences from the underlying sensors using a sliding window weighted average. This step is accomplished through the coordinated execution of a series of physical hardware actions and computer program instructions. The specific implementation process is as follows:

[0051] First, at the physical level, the underlying sensors deployed at the monitoring site continuously convert the monitored physical quantities (such as temperature, humidity, voltage values, etc.) into analog or digital signals at a preset fixed frequency. These signals are then transmitted in electrical form to the sensor interface circuit of the edge computing gateway via fieldbus (such as RS485, CAN bus) or wireless communication modules (such as ZigBee, LoRa). The signal conditioning unit in this interface circuit filters, performs level conversion, and analog-to-digital conversion (if necessary) on the input signal, ultimately sending a stable digital electrical signal to the main processor data bus of the edge computing gateway.

[0052] The main processor of the edge computing gateway (in this embodiment, a Cortex-M4 core microcontroller) runs a real-time operating system. Its periodic task scheduler generates a hardware timer interrupt request in each sampling cycle (e.g., once per second). When the interrupt request is responded to by the processor, the processor executes an interrupt vector jump, pointing the program counter pointer to the starting address of the sensor data acquisition service routine, thereby starting the current data acquisition cycle. The processor sends a read command to the sensor interface circuit via the data bus. After the command is decoded by the address bus, it activates the chip select signal of the sensor interface. The interface circuit then sends the converted digital signal data back to the processor's data register via the data bus, completing the digital acquisition process of the physical signal.

[0053] The acquired raw data dt is transferred by the processor from the data register to a sliding window buffer maintained in internal RAM. This buffer uses a circular queue structure, occupying a contiguous memory address space in physical memory, and is jointly managed by a start address pointer, an end address pointer, and a current write pointer. After the newly acquired data dt is written to the physical memory unit pointed to by the current pointer, the write pointer automatically increments. When the pointer exceeds the end address, it wraps back to the start address, achieving circular overwrite storage, thereby maintaining a historical data sequence of fixed length N in physical memory.

[0054] Meanwhile, during the edge computing gateway's startup phase, a mapping configuration table for the smoothing coefficient α is pre-programmed into a specific address region (in this embodiment, a 16-byte space starting at 0x0800C000) of its built-in non-volatile Flash memory. This mapping table is physically represented as a series of binary bitstreams stored in the floating-gate transistors of the Flash memory cells. When the system powers on and completes the BootLoader boot process, the processor executes an initialization program, reading the physical memory cells of this Flash region via the QSPI bus in four-wire high-speed mode, and loading the mapping relationship of the α coefficient into the processor's instruction cache for subsequent table lookup operations.

[0055] When the sliding window weighted average preprocessor is invoked, the processor first reads the lookup instruction from the instruction cache, using the currently configured α value as an index, and accesses the corresponding mapping entry in the cache through the address mapping mechanism. This entry is physically represented by a combination of bits in a register, indicating the corresponding integer shift operation mode. Specifically, when α = 0.2, the bit combination of the mapping entry instructs the processor to perform a "right shift by 3 bits" operation. This operation is physically manifested as the processor's internal arithmetic logic unit (ALU) shifting the binary value in the data register 3 bits to the right along the bit lines, padding the high-order bits with zeros, and shifting the low-order bits to the carry bit in the flag register, thus achieving the equivalent effect of division by 8 at the circuit level. When α = 0.3, the mapping entry instructs the processor to perform a compound shift operation: first, a right shift by 2 bits (equivalent to 1 / 4), then a right shift by 4 bits independently (equivalent to 1 / 16), and finally, the ALU's subtraction unit subtracts the two shift results in the physical adder to obtain a weighting coefficient equivalent to 3 / 16. The entire lookup and shift operation is executed continuously in the processor instruction pipeline, and is completed through the coordinated work of the hardware decoding unit, register set and ALU, without relying on any floating-point arithmetic unit.

[0056] After the shift operation is completed, the processor performs a multiplication and accumulation operation in the ALU with the shifted result and the original data dt at the current moment. This operation is physically represented by the AND, OR, and NOT logic combinations of gate circuits, triggered by timing control signals at specific clock edges, and finally outputs the weighted intermediate result. This result is then added to the weighted accumulated value of the historical data in the sliding window in the physical adder to complete the weighted average calculation of the sliding window. During the calculation, the processor precisely controls the timing of each operation step through program instructions to ensure that all operations are completed within 50 clock cycles. Each clock cycle corresponds to one physical oscillation cycle of the processor's internal oscillator (5.95 nanoseconds in this embodiment). Completion within 50 cycles means that the entire preprocessing process ends in approximately 250 nanoseconds of physical time. The calculation result Vt is written to the designated physical memory unit as the final preprocessed value at the current moment for subsequent steps to call.

[0057] The entire S100 process physically transforms the sensor physical signals into digital signals, the digital signals into memory data, the memory data into processor registers, the registers into ALU operations, and the operation results back into memory. Each transformation is accomplished through the propagation of electrical signals in the hardware circuit, the execution of processor instructions, and the read and write operations of memory units, ensuring efficient and deterministic data preprocessing on resource-constrained edge computing platforms.

[0058] S200. Store historical data for the most recent N time periods in the local memory of the edge computing gateway, calculate dynamic feature values ​​in real time, and build a dynamic benchmark model. The determination of the N time periods adopts an adaptive adjustment mechanism: the edge computing gateway dynamically adjusts the value of N according to the ratio of the current network load L to the sensor sampling frequency F. When L / F>10, N is reduced to 5 minutes, and when L / F<1, N is extended to 15 minutes. The adaptive adjustment mechanism is triggered by the load monitoring interrupt service routine of the edge computing gateway at the end of each heartbeat cycle.

[0059] Specifically, step S200 involves building and dynamically maintaining a baseline model in the local memory of the edge computing gateway. This process is accomplished in coordination with the level changes of the physical storage medium and the periodic execution of processor instructions, as detailed below:

[0060] First, on the circuit board of the edge computing gateway, a specific address range of the physical memory chip (SRAM or SDRAM in this embodiment) is divided into a dedicated storage area. This area is divided by the processor executing memory management unit configuration instructions during the power-on initialization phase. By writing the start address and length parameters to the memory controller register, a contiguous physical address space is defined at the hardware level as a circular buffer. The start address pointer of this buffer is loaded into the processor's base address register, and the end address pointer is loaded into the length limit register, forming a ring-shaped physical storage structure. Whenever the sensor sampling cycle arrives, the processor executes a data transfer instruction, writing the preprocessed value Vt output in step S100 to the physical memory cell pointed to by the current write pointer via the data bus in the form of a parallel electrical signal. The write pointer register then performs an increment operation, which is physically manifested as the level toggling of the flip-flops inside the register. When the pointer value exceeds the end address stored in the limit register, the comparator circuit generates a wraparound signal, resetting the write pointer to the start address of the base address register. This achieves cyclic overwriting storage of data on the physical storage medium, ensuring that the memory chip always retains historical data samples from the most recent N time periods.

[0061] Meanwhile, the acquisition of network load L is manifested as physical queue length monitoring. When the network interface controller (NIC) of the edge computing gateway sends data, it stores the descriptor information of the data packets to be sent into its internal transmit descriptor circular buffer, which consists of a physically independent register array or a shared memory block. The processor reads the NIC's transmit queue status register by executing a peripheral access instruction. This register is physically connected to the counting circuit of the descriptor buffer and reflects the number of data packets to be sent in the queue in real time. The read count value is transmitted to the processor's general-purpose register in binary form via the data bus. This value is the physical quantization representation of the current network load L. The sensor sampling frequency F is a system preset parameter, which is fixed in the configuration area of ​​the Flash memory in constant form. When the processor executes the read instruction, it selects the physical storage cell in the Flash memory that stores the value of F through the address bus. After charge sensing and amplification by the Flash interface circuit, the charge state stored in the floating gate transistor is converted into a binary frequency value and transmitted to another general-purpose register of the processor.

[0062] At the physical moment the heartbeat cycle ends, the timer circuit of the edge computing gateway generates a periodic interrupt pulse signal. This signal is routed to the processor core via the interrupt controller, triggering the execution of the load monitoring interrupt service routine. After responding to the interrupt request, the processor suspends the instruction pipeline of the current user-mode task, forces the program counter to jump to the entry address corresponding to the interrupt service routine in the interrupt vector table, and begins executing the adaptive adjustment mechanism. The processor calls the division instruction, shifts the contents of the register storing the L value left by 8 bits (implementing fixed-point conversion), and then performs a division operation with the contents of the register storing the F value. This division operation is physically completed by the processor's internal division unit, involving the coordinated work of shift registers, adders, and control logic circuits. After several clock cycles, a fixed-point representation of the L / F ratio is obtained, and the result is stored in the result register.

[0063] Subsequently, the processor executes a comparison instruction, comparing the L / F ratio in the result register with a preset threshold constant (the fixed-point representation corresponding to 10 and 1) in parallel within the ALU. The comparison operation is implemented using a subtractor. If the subtraction result generates a borrow signal, the flag bit in the status register is set, indicating the comparison result. Based on the flag bit status, the processor executes a conditional jump instruction: if L / F > 10, the processor rewrites the memory cell corresponding to the N value variable with the number of samples corresponding to 5 minutes of data (physically manifested as writing a new binary value to that memory address); if L / F < 1, the processor expands the N value to the number of samples corresponding to 15 minutes; if L / F is between the two, the N value remains unchanged. After the N value adjustment instruction is executed, the processor immediately modifies the DMA controller's transfer count register (NDTR). This register is physically connected to the DMA engine's address generation unit. The new N value will change the address range of the DMA during the next transfer, thereby dynamically adjusting the circular buffer window size at the hardware level. The entire adjustment process is physically manifested as register level rewriting and DMA configuration signal level transitions.

[0064] After the value of N is determined, the processor executes the dynamic feature value calculation program. Historical data samples are read from the physical storage units of the circular buffer in address order. The read operation of each sample is physically manifested as the address bus sending an address signal. The decoding circuit of the memory chip selects the corresponding storage unit, and the data is returned to the processor register through the data bus as a parallel level signal. The processor sends the read data to the ALU to perform accumulation operation. During the accumulation process, the carry chain of the adder generates carry propagation. After multiple cycles, the sum is obtained, and then the mean μ is obtained through the division unit. The calculation of the standard deviation σ involves operations such as the difference between each sample and μ, squaring, accumulation, and square root. The square root operation is completed in the ALU through multiple iterations using a lookup table method or Newton's iteration method. Each iteration contains multiple multiplication and addition operations, and finally approximates the value of σ at the physical circuit level. The trend slope is achieved by least squares fitting. The processor executes multiplication and accumulation instructions to calculate Σ(t_i·V_ti) and Σt_i, and performs division operations in the floating-point unit or integer unit to obtain the slope value. The above calculation results are all stored in binary form in a specific variable area of ​​physical memory, forming the parameter set of the dynamic benchmark model, which can be called by subsequent S300 steps.

[0065] The entire S200 process physically realizes the complete process from sensor data storage, network status monitoring, adaptive parameter calculation to model feature value generation. Each sub-step is completed through physical operations such as processor instruction execution, register level switching, memory unit reading and writing, and peripheral register access, ensuring efficient and adaptive dynamic benchmark model construction under the condition of limited edge computing gateway resources.

[0066] S300, based on a dynamic benchmark model, executes a multi-level anomaly filtering strategy on the current preprocessed value, classifying the data into first-level anomalies, second-level anomalies, or redundant data. The multi-level anomaly filtering strategy adopts a three-level pipelined decision structure: the first level is a hard threshold comparator, the second level is a mutation rate accumulator, and the third level is a statistical interval discriminator. The three-level pipelined decision structure is executed atomically within the hardware timer interrupt of the edge computing gateway, ensuring that the decision process cannot be preempted by other tasks.

[0067] Specifically, step S300 involves multi-level anomaly classification and decision-making of preprocessed values ​​based on a dynamic benchmark model. Its core lies in the atomic execution of the decision-making process within a hardware timer interrupt through a three-level pipelined decision-making structure, ensuring the non-preemptibility and determinism of the decision-making process.

[0068] When the hardware timer reaches its preset sampling period (e.g., 1 second), the timer counter overflows and generates an interrupt request signal. This signal is sent to the processor core after priority arbitration by the interrupt controller. The processor core responds to the interrupt, suspends the currently executing user-mode task instruction stream, automatically saves the current program counter, status register, and other context information to the stack storage area through hardware mechanisms, and then jumps the instruction pointer to the entry address of the hardware timer interrupt service routine, thereby starting the execution of step S300.

[0069] At the interrupt service routine entry point, the processor first executes an interrupt disable instruction (__disable_irq()). This instruction operates at the hardware level on the processor's internal interrupt enable register, clearing the global interrupt enable bit. This ensures that even if other peripheral interrupt requests occur during subsequent execution, the processor will not respond, thus creating an atomic execution environment. In this environment, the currently deciding task exclusively occupies the processor's instruction pipeline, and no higher-priority task can be inserted for execution, providing isolation guarantees for the three-level pipelined decision process.

[0070] The first-stage hard threshold comparator, acting as the first stage of the pipeline, reads the current preprocessed value Vt and the preset hard threshold constant HARD_THRESHOLD from memory into a general-purpose register. The hard threshold constant is stored in the read-only region of Flash memory and loaded into the constant segment of memory during system startup. The processor executes a comparison instruction, performing a subtraction operation on the values ​​in the two registers in the arithmetic logic unit, and setting a flag in the status register based on the sign bit of the result. If Vt is greater than the hard threshold, the flag indicates true, and the processor immediately executes a conditional jump instruction, pointing the program counter to the result output segment, setting the exception level to level=1, and skipping the subsequent two stages of decision-making, directly entering the result processing flow before the interrupt return. This stage of decision-making is completed at the hardware level through a single-cycle comparison instruction, with extremely short execution time.

[0071] If the first level does not trigger an exception, the program flow enters the second level, the mutation rate accumulator. The processor reads the preprocessed value Vt-1 from memory, which was stored at a specific variable address in memory after step S100. The processor executes a subtraction instruction to calculate the difference Δ between the current value and the value from the previous time step, and stores the result in a temporary register. Subsequently, an absolute value instruction is executed to determine the sign of the difference and take a positive value. The obtained Δ value is compared with the preset mutation threshold δ in the comparator. The mutation threshold δ is calculated in real time by the dynamic benchmark model module based on the volatility of historical data and stored in the threshold variable area in memory. If Δ is greater than δ, the exception level is set to level=2, and a jump instruction is executed to skip the subsequent third-level decision and directly output the result. This level of decision involves two register read operations, one subtraction, one absolute value calculation, and one comparison, which are executed continuously in the processor pipeline, taking approximately 3-5 instruction cycles.

[0072] If no exception is triggered at level two, the program flow enters the third-level statistical interval discriminator. The processor obtains the mean μ and standard deviation σ of the current sliding window from the dynamic benchmark model module. Both are double-precision floating-point numbers or fixed-point numbers stored in memory after the calculation in step S200. The processor executes a subtraction instruction to calculate the difference between Vt and μ, and stores the result in a register. Then, an absolute value instruction is executed to obtain the absolute value of the deviation. The processor calculates 3 times the value of σ (through two additions or one multiplication-addition instruction) and compares it with the absolute value of the deviation. If the absolute value of the deviation is less than 3σ, the data is determined to be within the normal fluctuation range, and the exception level is set to level=0 (redundant data); if the deviation is greater than or equal to 3σ, it is determined to be an exception, and level=1 is set. This level of decision-making completes the arithmetic operation and comparison operation at the instruction level, and the result is selected by the conditional branch instruction to select the corresponding level value.

[0073] After the three-stage pipeline decision is completed, the processor executes the result output segment instructions, branching according to the value of the level register. If the level value is 1 or 2, the processor packages the preprocessed value Vt and the level value into a structure and passes it to the hardware queue manager module of step S400 through the function call interface; if the level value is 0, the processor writes Vt to the current write pointer position of the DMA zero-copy circular buffer and triggers the buffer pointer increment operation. After the result is output, the processor executes the interrupt enable instruction (__enable_irq()), resets the global interrupt enable bit, restores the processor's ability to respond to external interrupts, and deactivates the atomic execution environment. Subsequently, the processor executes the interrupt return instruction, restores the previously saved context information from the stack, and the program counter jumps back to the interrupted user-mode task to continue execution. The entire S300 step is completed in the interrupt service routine.

[0074] From a process transformation perspective, the S300 achieves a complete process transformation from interrupt triggering to atomic environment establishment, from three-level pipelined sequential decision-making to result classification and output, and from atomic environment deactivation to interrupt return. At the computer program level, this step is implemented through a carefully curated mix of assembly instructions and C language inline assembly, ensuring that each level of decision-making is completed within a minimal number of instructions, avoiding function call overhead. By using a pair of interrupt-disabling and interrupt-enabling methods, the program constructs a critical section at the software level, combined with the periodic triggering of hardware timer interrupts, achieving determinism and real-time performance in the decision-making task. The total execution time of the entire decision-making process, after compiler optimization and instruction cycle calculation, can be controlled within 12 microseconds, meeting the high timeliness requirements of edge computing gateways for anomaly detection.

[0075] S400: Perform differentiated data transmission based on classification results: If it is a Level 1 or Level 2 anomaly, the edge computing gateway immediately pushes the data to the central server with the highest priority through the priority queue controller. The highest priority push bypasses the TCP stack regular queue and sends directly. The priority queue controller is an independent FPGA logic unit, which integrates 8 levels of hardware queues. Each level of queue is configured with an independent DMA descriptor ring. The highest priority data is directly written to the Level 0 DMA descriptor ring and triggers the network card hardware transmission interrupt. If it is redundant data, it is temporarily stored in the local cache. The local cache adopts a zero-copy ring buffer structure. The buffer head pointer is directly managed by the edge computing gateway's DMA controller to avoid CPU participation in memory copying.

[0076] Specifically, step S400 is based on the anomaly level classification results output by step S300 and executes a differentiated data transmission strategy. This process is completed through the coordinated cooperation of FPGA hardware logic, DMA controller and processor instructions, to achieve rapid push of abnormal data and efficient caching of redundant data.

[0077] After the atomic decision in step S300 is completed, the processor's internal status register stores the exception level value corresponding to the current data. Based on this level value, the processor executes a conditional judgment instruction. If the level value is 1 or 2, the program flow enters the exception data transmission path; if the level value is 0, the program flow enters the redundant data cache path, thereby implementing branch selection of the transmission path at the software level.

[0078] In the abnormal data transmission path, the processor first encapsulates the preprocessed value Vt and the abnormal level value level into a data structure. This encapsulation process is completed at the instruction level through shift and bitwise OR operations, combining the bit fields of Vt and level into a fixed-length binary code stream, which is stored in contiguous memory locations. Subsequently, the processor calls a hardware push function, which accesses the register space of the FPGA logic unit through a memory-mapped I / O mechanism. At the circuit level, the FPGA logic unit uses an address decoder to identify the specific address signal issued by the processor. When the address matches, the internal data receiving channel is activated.

[0079] The processor transmits the packaged data stream to the priority queue controller integrated within the FPGA via the bus. This controller, at the hardware level, consists of multiple independent state machines and register sets, integrating a total of 8 hardware queues, each corresponding to a DMA descriptor ring. The descriptor ring is represented on the storage medium as a ring structure of a contiguous address space, with each descriptor containing fields such as data buffer address, data length, and status flags. The 0th-level DMA descriptor ring is specifically used for abnormal data. During system initialization, the processor writes the base address, length, and attribute parameters of this descriptor ring to the FPGA registers via configuration instructions. These configuration parameters are stored in binary level form in the FPGA's static configuration memory.

[0080] After receiving data, the priority queue controller automatically selects the level 0 queue based on the exception level using its internal arbitration logic. The controller writes the data stream to the data buffer pointed to by the currently available DMA descriptor for that queue. This buffer is located in the system's main memory, and its address is specified by the address field in the descriptor. After writing, the controller automatically updates the descriptor's status flag, switching the status from "idle" to "pending transmission." This update is implemented at the circuit level through a flip-flop level transition. The controller then immediately triggers a hardware transmit interrupt from the network interface card (NIC). This interrupt signal is represented at the circuit level as a level transition on a dedicated interrupt request line, transmitted from the interrupt controller to the NIC chip's transmit engine.

[0081] After the network card's transmission engine responds to an interrupt, it bypasses the layer-by-layer encapsulation and queuing processing of the TCP / IP protocol stack. It directly extracts the data buffer address and length information from the DMA descriptor ring, initiates internal DMA transfer, and transmits the data from main memory to the network card's internal transmission buffer via the bus. Physical layer signal transmission is then immediately initiated. This entire process bypasses the operating system kernel's TCP protocol processing module, omitting software processing steps such as socket buffer copying, sliding window management, and acknowledgment, enabling extremely rapid push of abnormal data.

[0082] In the redundant data cache path, the processor transfers the preprocessed value Vt with a level of 0 to the DMA zero-copy circular buffer management module. During initialization, this module has been configured by the processor to operate in circular mode for the DMA controller, and the buffer base address, length, and transfer direction have been set. The DMA controller, at the hardware level, consists of an address generator, a data transfer engine, and a status register. Internally, it maintains a header pointer register, which is directly connected to the buffer address bus at the circuit level.

[0083] When Vt data needs to be stored in the buffer, the processor does not directly perform a memory write operation. Instead, it triggers a DMA transfer by writing to the source address register and transfer count register of the DMA controller. The DMA engine automatically moves the data from the processor registers to the memory address pointed to by the head pointer in the circular buffer. After the transfer is complete, the DMA hardware circuit automatically increments the value of the head pointer register. When the pointer reaches the end of the buffer, an address overflow is detected by the comparator circuit, and a wraparound signal is automatically generated to reset the head pointer to the start address of the buffer, thus achieving circular overwriting of the circular buffer. The entire process is completed independently by the DMA controller. The processor does not need to execute any data copy instructions, but only needs to configure registers, thereby avoiding CPU involvement in memory copy operations and saving processor instruction cycles.

[0084] After step S400 is completed, if the data is of an abnormal type, it has been sent directly to the network card via the FPGA hardware queue and DMA, entering physical network transmission; if the data is of a redundant type, it has been stored in the DMA-managed circular buffer, waiting for batch upload. The processor continues to execute the subsequent S500 step of heartbeat monitoring or returns to the main loop to wait for the next sampling cycle, completing the overall process of differentiated data transmission.

[0085] The S500 edge computing gateway monitors the connection status with the central server in real time through a heartbeat monitoring link. When an intranet connection interruption is detected, it automatically switches to autonomous mode, directly drives the GPIO interface to control peripheral audible and visual alarm devices according to local policies, and writes key abnormal data into local non-volatile memory. After the network is restored, the backlogged alarm data is uploaded first. The heartbeat monitoring link adopts a bidirectional UDP heartbeat mechanism with a heartbeat period of 500 milliseconds. Three consecutive timeouts are considered as intranet connection interruptions. The bidirectional UDP heartbeat packet payload carries the current backlog of data B of the edge computing gateway and the processing queue length Q of the central server. The central server dynamically adjusts the heartbeat period according to the Q value. When Q>1000, the heartbeat period is actively extended to 1000 milliseconds to reduce network pressure.

[0086] Specifically, the S500 step enables real-time monitoring of the connection status between the edge computing gateway and the central server, autonomous switching during network outages, and data continuation after recovery. The entire process is completed collaboratively through UDP heartbeat packet interaction, hardware timer counting, interrupt service routine response, and memory read / write operations.

[0087] During system startup, the edge computing gateway's processor executes a network protocol stack initialization program, creating a UDP socket at the transport layer and binding it to a preset port number. This socket corresponds to a protocol control block structure in the kernel, containing fields such as the local IP address, port number, and peer server address and port. The processor configures the socket to allow broadcast or multicast packet transmission via the socket API call, and sets its send and receive buffer sizes. Simultaneously, the processor configures a hardware timer (in this embodiment, the STM32's TIM7 timer) with its auto-reload register set to a count value corresponding to 500 milliseconds, and enables the timer update interrupt. The timer counter decrements cycle by cycle under the clock source's drive. When the count value reaches zero, the hardware automatically generates an update event, triggering an interrupt request signal, which is transmitted to the processor kernel via the interrupt controller.

[0088] During normal operation, whenever a hardware timer interrupt is triggered, the processor executes the interrupt service routine. This routine first reads the backlog B in the current socket send queue. The backlog B is represented at the software level as the number of data packets to be sent in the socket send buffer, a value recorded by a counter variable maintained by the kernel protocol stack. The processor obtains the memory address of this variable by calling a kernel API function and executes a load instruction to read the value of B into a register. Subsequently, the processor reads the length Q of the central server's processing queue from memory. This Q value is carried by the central server in each heartbeat response packet, and the edge gateway parses and stores it in a specific memory variable after receiving the response packet. The processor encapsulates the B and Q values ​​into the application layer payload of the UDP heartbeat packet according to the TLV (Type-Length-Value) format. The specific encapsulation process is completed through a memory copy instruction, writing the B and Q values ​​sequentially to the corresponding byte positions in the UDP payload buffer. After encapsulation, the processor calls the UDP send function, which delivers the heartbeat packet to the network card driver. The driver writes the packet descriptor into the 7th level queue (heartbeat dedicated queue) of the FPGA hardware queue manager and triggers the network card send engine to start DMA transfer, sending the heartbeat packet to the central server via the network cable.

[0089] The central server's UDP receive service process listens for heartbeat packets on a designated port. When the network interface card (NIC) receives a data packet, the hardware DMA engine moves the data from the NIC buffer to the kernel receive queue and generates a receive interrupt. The server processor responds to the interrupt, executes the protocol stack handler, parses the TLV data in the UDP payload, and extracts the B and Q values. The server compares the Q value with its preset queue length threshold of 1000; this comparison is performed in the processor's ALU. If the Q value is greater than 1000, the server sets the heartbeat period adjustment variable to 1000 milliseconds and sends this adjustment instruction back to the edge gateway via a reverse heartbeat response packet; if the Q value is less than or equal to 1000, the period remains at 500 milliseconds. The sending process of the reverse heartbeat response packet is similar to that of the edge gateway sending heartbeat packets; it is encapsulated by the server's protocol stack and sent through the network interface.

[0090] After sending a heartbeat packet, the edge gateway starts a receive timeout timer. The processor maintains a timeout counter variable in memory, initially set to 0. The gateway's receive thread is blocked on the UDP socket receive call, waiting for the server's heartbeat response packet. If no response is received within a 500-millisecond time window, the receive call returns a timeout error, the processor executes the error handler, and increments the timeout counter variable by 1. This incrementing operation is represented at the instruction level as an atomic read-modify-write operation, ensuring counting accuracy in a multi-tasking environment. The counter value is then compared with a preset threshold of 3. If the counter value is less than 3, the program flow returns to the timer interrupt service routine entry point, waiting for the next heartbeat cycle; if the counter value reaches 3, the processor determines that the internal network connection has been interrupted, sets a global network disconnection flag variable to true, and triggers the autonomous mode switching process.

[0091] The autonomous mode switching is driven by the state change of the network disconnection flag variable. After the atomic decision procedure of step S300 is completed, the network disconnection flag is checked. If the flag is true, the normal data upload process is skipped, and the autonomous control function is executed instead. This function first accesses the configuration register of the FPGA logic unit and writes a control word to the FPGA's GPIO control register through memory-mapped I / O. Each bit of the control word corresponds to a GPIO pin. The write operation is decoded and latched at the circuit level, causing the GPIO control logic unit inside the FPGA to generate a corresponding level signal. This signal is amplified by a level conversion chip and drives the external relay coil. The relay contacts close, connecting the power circuit of the audible and visual alarm, and the alarm emits an audible and visual alarm signal. The driving process does not require continuous processor intervention, and the FPGA logic unit maintains the output level until the network is restored. For the emergency exhaust fan, the FPGA generates a pulse width modulation signal through the PWM module. This signal is generated by the FPGA's internal counter and comparator circuit, and the duty cycle is determined by the value written to the PWM control register by the processor, thereby adjusting the fan speed.

[0092] During network outages, critical abnormal data must still be preserved. The processor transfers abnormal data with a level value of 1 or 2 from the memory buffer to the Flash write queue, which is managed by the DMA controller. The processor configures the DMA source address to the data's address in memory, the destination address to the write page address in the Flash memory, and the transfer length to the data packet size, then initiates the DMA transfer. The DMA engine automatically moves the data from memory to the data register of the Flash interface controller in the background. The Flash controller executes erase and programming commands sequentially according to the timing requirements of the Flash chip, storing the data in the floating gate structure of the Flash memory cell in the form of charge, ensuring data retention even when power is lost. The write address uses a circular queue management system controlled by a Flash address pointer variable. The pointer increments after each data write, and after the entire Flash area is filled, it wraps back to the starting address, overwriting the oldest data.

[0093] When the network is restored, the edge gateway's receiving thread successfully receives the server's heartbeat response packet. The processor resets the timeout counter and sets the network outage flag variable to false. Afterward, the processor prioritizes processing the backlogged alarm data in Flash. Starting from the head address of the Flash read queue, it moves the data from Flash to the memory transmit buffer via DMA. Then, it calls the FPGA hardware queue manager's transmit interface to write the data packet to the level 0 DMA descriptor ring and triggers transmission. After each data packet is transmitted, the Flash read pointer increments until all backlogged data is uploaded, restoring normal data flow. When the server receives resumed data, it identifies it as historical data based on the timestamp in the data packet and inserts it into the corresponding position in the database to ensure data integrity.

[0094] In summary, the S500 achieves a complete functional closed loop of connection monitoring, network outage autonomy, and recovery and resumption of transmission through multi-level hardware and software collaboration, including heartbeat packet timed sending and receiving, timeout counting, status flag switching, FPGA register configuration, DMA transmission, and Flash storage.

[0095] Preferably, in fixed-point arithmetic, when α = 0.2~0.3, the specific mapping relationship configured by the lookup table method is as follows:

[0096] α=0.2 → shift right by 3 bits (1 / 8=0.125);

[0097] α = 0.25 → shift right by 2 bits (1 / 4 = 0.25);

[0098] α=0.3 → Shift right by 2 bits and then subtract the value after shifting right by 4 bits (1 / 4-1 / 16=3 / 16=0.1875);

[0099] The lookup table method is stored in the startup configuration Flash of the edge computing gateway, occupying 16 bytes of space, and is loaded into the CPU's instruction cache by the BootLoader during system power-on initialization.

[0100] Specifically, in the fixed-point arithmetic implementation, the mapping relationship between the smoothing coefficient α and the integer shift operation is implemented using a lookup table method. This mapping relationship is reflected at the system level as the 16-byte storage space layout in the Flash memory during startup configuration. Specifically, when α is 0.2, the mapping relationship is configured as a right shift of 3 bits, which is equivalent to multiplying by 1 / 8 (0.125) in two's complement representation. In implementation, the binary code of the original data dt is shifted 3 bits to the right, with high-order bits automatically padded with zeros, completing the fixed-point division by 8. When α is 0.25, the mapping relationship is configured as a right shift of 2 bits, equivalent to multiplying by 1 / 4 (0.25). In implementation, dt is shifted 2 bits to the right, with high-order bits padded with zeros, completing the division by 4. When α is 0.3, the mapping relationship is configured as a composite shift operation. First, dt is shifted right by 2 bits to obtain the first intermediate value, and then dt is shifted right by 4 bits to obtain the second intermediate value. Then, the first intermediate value is subtracted from the second intermediate value through the ALU subtraction unit. This composite operation is equivalent to 1 / 4 minus 1 / 16, and the result is 3 / 16, which is 0.1875, thus approximating a floating-point weight of 0.3 in the integer arithmetic domain.

[0101] The three mapping relationships described above are stored in a compact format in the startup configuration Flash of the edge computing gateway, starting at address 0x0800C000 and occupying 16 consecutive bytes of space. In the storage layout, the first 4 bytes are used to store the mapping parameter for α=0.2, encoded as a single-byte opcode 0x03 (representing a right shift of 3 bits); bytes 5 to 8 are used to store the mapping parameter for α=0.25, encoded as a single-byte opcode 0x02 (representing a right shift of 2 bits); bytes 9 to 16 are used to store the composite mapping parameter for α=0.3, encoded as two-byte sequences 0x02 and 0x04 (representing right shift of 2 bits and right shift of 4 bits respectively), and the subtraction operation identifier is stored in the following 2 bytes. The remaining space is reserved for future expansion to other α value mappings.

[0102] During system power-up, the BootLoader program performs a Flash read operation during the boot phase, continuously reading 16 bytes of data from address 0x0800C000 via the QSPI bus in four-wire mode. This read operation is represented at the circuit level by the chip select signal being pulled low, the clock signal being triggered, and the data line voltage levels changing. The 16 bytes of mapped data are then written by the BootLoader into a specific line of the CPU's internal instruction cache using a memory copy instruction. The instruction cache, at the hardware level, consists of multiple sets of tag memory arrays and data storage arrays, each containing a valid bit, a tag bit, and a data block. The BootLoader writes the mapped data into the data block area of ​​the cache, sets the corresponding tag bit to valid, and sets the valid bit, completing the loading process from Flash non-volatile storage to the cache. After loading, the subsequent sliding window preprocessing module directly reads the mapped parameters from the instruction cache, obtains the opcode by indexing the cache line corresponding to the α value, and performs the corresponding shift operation, thus avoiding the latency caused by each Flash access and completing the preprocessing calculation within 42 clock cycles.

[0103] Preferably, in the adaptive adjustment mechanism, the network load L is calculated by the edge computing gateway by monitoring the queue length of data packets to be sent per unit time. The sensor sampling frequency F is a system preset value. The ratio of network load L / sensor sampling frequency F is stored in 16-bit fixed-point format. The load monitoring interrupt service routine is executed once every 500 milliseconds. The N value is updated according to the ratio of network load L / sensor sampling frequency F, and the sliding window size is adjusted synchronously. The adjustment of the sliding window size is achieved by modifying the modulus of the circular buffer pointer, without the need to reallocate memory.

[0104] Preferably, the three-stage pipelined decision structure in the Cortex-M4 core achieves atomic execution in the following way:

[0105] The three functions—hard threshold comparator, mutation rate accumulator, and statistical interval discriminator—are encapsulated into an inline assembly code block, and global interrupts are disabled before execution using the __disable_irq() instruction.

[0106] After the decision is completed, interrupts are restored by __enable_irq() to ensure that the entire decision process is executed continuously on the CPU pipeline, cannot be preempted, and the time window for atomic execution is less than 12 microseconds.

[0107] Preferably, in the FPGA logic unit, the DMA descriptor ring of the 8-level hardware queue is configured as follows:

[0108] Level 0: Dedicated to abnormal data, 128 descriptors, each descriptor points to a 2KB data buffer;

[0109] Levels 1-6: Normal business data, 64 descriptors per level;

[0110] Level 7: Redundant data, 32 descriptors, uploaded in batches only when the network is idle;

[0111] The descriptor ring is allocated in the FPGA's internal Block RAM and interacts with the CPU via the AXI4-Lite bus.

[0112] Preferably, the head pointer of the zero-copy circular buffer is automatically updated by the DMA controller, specifically implemented as follows:

[0113] The DMA engine of the edge computing gateway's network card is configured in receive-direction circular buffer mode. When redundant data is received, the DMA engine writes the data to the current write pointer position. The write pointer is automatically incremented by 1 and wraps around. The CPU obtains the data position by reading the write pointer register without executing any memory copy instructions.

[0114] Preferably, the current data backlog B and the central server processing queue length Q carried in the bidirectional UDP heartbeat packet payload are encoded in TLV (Type-Length-Value) format, where:

[0115] Type=0x01, Length=4 bytes, Value=B (16-bit unsigned integer);

[0116] Type=0x02, Length=4 bytes, Value=Q (16-bit unsigned integer);

[0117] The heartbeat packet is sent in user space by the FPGA logic unit of the edge computing gateway via RDMA (Remote Direct Memory Access) technology, bypassing the kernel network protocol stack.

[0118] An environmental monitoring data processing system based on the same concept includes:

[0119] The edge computing gateway, deployed at the monitoring site, integrates a real-time operating system, non-volatile Flash memory, and a priority queue controller. The real-time operating system is configured with an interrupt response time of less than 10 microseconds and a task scheduling cycle accurate to 1 millisecond. The priority queue controller is an independent FPGA logic unit configured to perform data push bypassing the TCP stack in step S400. The edge computing gateway's CPU core is a Cortex-M4 with a main frequency of 168MHz. When performing sliding window weighted average preprocessing, it maps the floating-point smoothing coefficient α to integer shift operations, so that a single preprocessing calculation consumes 42 clock cycles, which is equivalent to an execution time of 250 nanoseconds.

[0120] The central server is configured to receive and process priority-tagged data packets from the edge computing gateway. These packets contain exception data that is sent directly by bypassing the TCP stack. The central server's data receiving thread uses memory-mapped I / O technology to directly map the network card's receive buffer to the user-space memory space, bypassing the kernel protocol stack parsing and making the average data write latency less than 50 microseconds.

[0121] The heartbeat monitoring link is used for bidirectional heartbeat detection. The heartbeat monitoring link is implemented in user space through raw sockets. The sending and receiving of heartbeat packets bypasses the kernel TCP / IP protocol stack and is directly processed by the FPGA logic unit of the edge computing gateway, ensuring that the heartbeat detection latency is less than 5 milliseconds.

[0122] Preferably, the memory-mapped I / O technology is specifically implemented as follows:

[0123] The central server maps the receive buffer (BAR) space of the PCIe network card to the user-mode address space of the monitoring process through the mmap() system call. The monitoring process detects buffer updates by polling rather than interrupting. When the FPGA logic unit writes a data packet, the monitoring process reads the data through the CAS (Compare-And-Swap) atomic instruction, reducing the data write latency from the traditional 200 microseconds to 45 microseconds.

[0124] Preferably, the FPGA logic unit of the heartbeat monitoring link integrates a heartbeat state machine, which contains four states: IDLE, SEND, WAIT, and TIMEOUT. The state transition is driven by a 500-millisecond hardware timer. After three consecutive timeouts, the state machine outputs a network disconnection signal. The network disconnection signal directly triggers the GPIO-driven relay controller without CPU intervention, ensuring that the time from network disconnection to the triggering of the audible and visual alarm is less than 15 milliseconds.

[0125] The environmental monitoring data processing system described in this invention is based on a unified edge computing architecture concept. It consists of three core components: an edge computing gateway deployed at the monitoring site, a central server located in the remote monitoring center, and a two-way heartbeat monitoring link connecting the two. Each component achieves real-time, deterministic, and high reliability of data processing through specific hardware configurations and software collaboration.

[0126] The edge computing gateway, serving as the system's field execution unit, utilizes a Cortex-M4 CPU core with a 168MHz clock speed. This processor core integrates a DSP instruction set and a single-cycle multiply-accumulate unit, but omits a floating-point unit (FPU) to reduce power consumption and cost. The gateway circuit board integrates 16MB of non-volatile Flash memory, using a W25Q128FVSSIG chip connected to the CPU via a QSPI four-wire interface. This memory stores the system boot image, configuration parameters, and critical alarm data during network outages. The gateway incorporates a real-time operating system with a tailored and optimized kernel, achieving interrupt response times within 10 microseconds and task scheduling cycles accurate to 1 millisecond, ensuring timely preemption of high-priority tasks. The priority queue controller is implemented as an independent FPGA logic unit, employing the Lattice iCE40UP5K chip. It interacts with the CPU via an FSMC parallel bus. Its internal logic is programmed in Verilog hardware description language and configured as an 8-level DMA hardware queue structure, specifically designed for the exception data push function that bypasses the TCP stack during the S400 step.

[0127] During the sliding window weighted average preprocessing, the CPU immediately calls the preprocessing function after acquiring the raw sensor data dt. This function maps the floating-point smoothing coefficient α to an integer shift operation using a lookup table. Specifically, when α = 0.2, it maps to a logical right shift of 3 bits, equivalent to multiplying by 1 / 8; when α = 0.3, it maps to a logical right shift of 2 bits followed by a logical right shift of 4 bits, equivalent to multiplying by 3 / 16. This mapping is loaded from the Flash configuration area to the CPU instruction cache by the BootLoader during system startup, ensuring that the shift operation can be completed in only 42 clock cycles when the cache is hit, equivalent to an execution time of 250 nanoseconds (42 cycles ÷ 168MHz). After preprocessing, the result Vt is stored in a circular buffer in main memory for subsequent decision-making.

[0128] The central server is deployed in the monitoring center, using an x86 architecture multi-core processor and running a Linux operating system. The server is configured with a dedicated monitoring process, which, upon creation, binds to a specific UDP port via a socket API to listen for data packets from the edge computing gateway. The data receiving thread employs memory-mapped I / O technology: the server connects to an Intel 82599ES 10 Gigabit Ethernet card via a PCIe bus, and the network card's internal receive buffer is mapped to the system memory address space in the form of a base address register (BAR). The monitoring process calls the mmap() system call in user space to map the physical address of the network card's BAR space to the process's virtual address space, bypassing the layered copying and parsing of the kernel protocol stack. When the FPGA logic unit writes abnormal data packets to the network card's receive buffer via DMA, the monitoring process uses polling instead of interrupts to detect buffer updates, ensures data visibility through memory barrier instructions, and uses CAS (Compare-And-Swap) atomic instructions to read the data packet content from the mapped virtual address. This mechanism reduces the time delay for data to travel from the network card to the user-space process from 200 microseconds in the traditional interrupt-driven mode to 45 microseconds, and keeps the average latency for writing to the database below 50 microseconds.

[0129] The heartbeat monitoring link in the system architecture is responsible for connection status monitoring and triggering autonomous network outages. This link is implemented in user space using raw sockets. When the edge computing gateway creates a raw socket, the protocol type is set to IPPROTO_UDP and bound to a specific port. The sending and receiving of heartbeat packets bypasses the complex processing flow of the kernel TCP / IP protocol stack and is directly handled by the FPGA logic unit. The FPGA integrates a dedicated heartbeat processing engine, which contains a 4-state heartbeat state machine with 2-bit state encoding. The states include IDLE, SEND, WAIT, and TIMEOUT. The state machine is driven by an independent 500ms hardware timer. The timer counter decrements on the rising edge of the clock, triggering a state transition event when it reaches zero. When the state machine is in the IDLE state, a timer overflow event causes it to transition to the SEND state. The FPGA automatically constructs a UDP heartbeat packet, with the payload encapsulated in TLV format as the current data backlog B of the edge gateway and the server processing queue length Q, and sent via the network card DMA engine. After sending, the state machine transitions to the WAIT state and starts a response waiting timer. If a valid heartbeat response is received from the server within a 500-millisecond window, the state machine returns to the IDLE state and resets the timeout counter. If no response is received, the state machine transitions to the TIMEOUT state, and the timeout counter increments by 1. When the timeout counter accumulates three times, the state machine outputs a continuously valid network disconnection signal. This signal is directly connected to the FPGA's GPIO control module at the circuit level, without CPU intervention. The GPIO module immediately drives the external relay controller to connect the power circuit of the audible and visual alarm, achieving a rapid response with a time of less than 15 milliseconds from network disconnection to alarm triggering. Simultaneously, in autonomous mode, critical abnormal data is written in batches to the Flash memory via the DMA channel. The write address is managed using a ring pointer to ensure no data loss. After the network is restored, the edge gateway prioritizes reading the accumulated alarm data in the Flash memory and re-uploads it to the central server via the FPGA's level 0 DMA queue, completing the breakpoint resume transmission.

[0130] By adopting the above-disclosed technical solution of this invention, the following beneficial effects are obtained:

[0131] First, it drastically reduces the I / O load and storage costs of the central server. Through edge-side sliding window integer shift preprocessing and dynamic benchmark model filtering, over 95% of redundant data is intercepted locally, with only abnormal data uploaded to the central server. Real-world testing shows that with 10,000 sensor nodes, the central database write IOPS has decreased from 8,000 times / second in traditional solutions to 620 times / second, a reduction of 92.3%, while extending server hard drive lifespan by more than three times. Simultaneously, data storage is compressed by 90%, historical data query response time is shortened from an average of 15 seconds to 1.2 seconds, report generation efficiency is improved tenfold, and storage hardware procurement and maintenance costs are significantly reduced.

[0132] Secondly, it completely eliminates the risk of intranet congestion. The FPGA hardware queue manager bypasses the regular TCP stack queue, and abnormal data is sent directly through a dedicated DMA descriptor ring, without occupying protocol stack buffer resources. Even under extreme conditions of 95% network load, abnormal data packets can still achieve zero-blocking transmission. Redundant data is temporarily stored in a zero-copy ring buffer, and the CPU does not participate in memory copying, significantly reducing the processing load of the edge gateway itself. Real-world testing shows that when network burst traffic reaches 90% of the link bandwidth, the traditional solution has a packet loss rate of 12%, while this invention achieves zero packet loss for abnormal data, ensuring the reliable issuance of remote control commands.

[0133] Third, it achieves millisecond-level deterministic alarm response. The three-level pipelined decision structure executes atomically within a hardware timer interrupt, with a decision time window of <12 microseconds, ensuring no task preemption delay in alarm detection. Combined with the <8 microsecond forwarding latency of the FPGA hardware queue and the <50 microsecond write latency of the central server's memory-mapped I / O, the end-to-end average alarm latency is <8 milliseconds, and the P99 latency is <15 milliseconds, a 25-fold improvement over the traditional 200 millisecond latency, fully meeting the stringent real-time requirements of alarms in emergency scenarios such as fires and water leaks. In simulated fire tests, the total time from abnormal smoke sensor data to the central platform alarm pop-up was only 7.3 milliseconds, gaining valuable time for personnel evacuation and equipment protection.

[0134] Fourth, it establishes highly reliable autonomous network outage capabilities. The FPGA state machine directly drives the GPIO interface, eliminating the need for CPU intervention throughout the entire process of network outage detection and audible / visual alarm triggering, with a response time of less than 15 milliseconds, solving the 50-200 millisecond lag problem of traditional CPU polling solutions. During autonomous operation, critical data is written to non-volatile Flash memory in a circular queue, supporting data storage for more than 7 days of network outage. After network recovery, data is automatically resumed and alarm data is uploaded first, ensuring monitoring continuity. Real-world testing verified that in 100 simulated network outage tests, the local audible / visual alarm success rate was 100%, with zero data loss, and the data integrity verification pass rate after recovery was 100%.

[0135] Fifth, it enhances system scalability and deployment flexibility. The number of sensors that can be connected to a single edge computing gateway (Cortex-M4, 168MHz) increases from 500 in traditional solutions to 2000, and the number of edge nodes that a single central server can manage expands from 100 to 500, resulting in a 5-fold increase in overall system scalability. Furthermore, this invention has no special requirements for sensor type, is compatible with mainstream protocols such as Modbus, SNMP, and dry contact, supports smooth upgrades of new and old environmental systems, and lowers the technical threshold and transformation costs for large-scale networking.

[0136] Sixth, reduce the hardware cost and power consumption of edge devices. Through algorithm hardening and integer shift optimization, the CPU does not need to enable the FPU, and the main frequency can be reduced to 168MHz to meet the performance requirements. Compared with the traditional solution that requires a Cortex-A7 (above 1GHz) processor, the hardware cost is reduced by 60%, and the power consumption is reduced from 5W to 1.2W. It supports green energy deployment such as solar power and is particularly suitable for power-constrained scenarios such as base stations and remote sites.

[0137] Seventh, enhancing the universality and evolvability of the technology. The FPGA hardware queue manager and zero-copy buffer design of this invention can be reused in other IoT scenarios (such as industrial control and smart security). Its "algorithm hardening + protocol bypass" concept provides a general paradigm for the deployment of edge computing on resource-constrained devices. At the same time, the system architecture supports online upgrades of FPGA logic, and can flexibly expand the decision rules or add new filtering dimensions according to future needs, possessing good technological vitality and sustainable development potential.

[0138] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for real-time filtering of abnormal data based on edge computing in a moving ring system, characterized in that, The method comprises the following steps: S100, periodically collecting a raw data sequence from a bottom sensor according to an edge computing gateway, and performing a sliding window weighted average preprocessing on the raw data to obtain a preprocessing value at a current time, wherein the edge computing gateway implements the sliding window weighted average preprocessing by fixed point number operation, converts a floating point smoothing coefficient α into an integer shift operation, makes a single preprocessing calculation consume less than 50 clock cycles of CPU period, and the integer shift operation is specifically: when α=0.2, it is mapped to a right shift 3-bit operation, when α=0.3, it is mapped to a right shift 2-bit operation minus a right shift 4-bit operation, and the mapping relationship is automatically configured according to a preset smoothing coefficient when the edge computing gateway starts through a lookup table method; S200, storing historical data of N time periods in the local memory of the edge computing gateway, calculating a dynamic characteristic value in real time, and constructing a dynamic reference model, wherein the determination of the N time periods adopts an adaptive adjustment mechanism: the edge computing gateway dynamically adjusts the N value according to the ratio of the current network load L to the sensor sampling frequency F, when L / F>10, N is reduced to 5 minutes, and when L / F<1, N is extended to 15 minutes, and the adaptive adjustment mechanism is triggered to execute at the end of each heartbeat period through a load monitoring interrupt service program of the edge computing gateway; S300, based on the dynamic reference model, performing a multi-level abnormality filtering strategy on the current preprocessing value to classify the data into a first-level abnormality, a second-level abnormality or redundant data, wherein the multi-level abnormality filtering strategy adopts a three-level flow decision structure: a first level is a hard threshold comparator, a second level is a mutation rate accumulator, and a third level is a statistical interval discriminator, the three-level flow decision structure is executed atomically in a hardware timer interrupt of the edge computing gateway, and the decision process cannot be preempted by other tasks; S400, performing differentiated data transmission according to the classification result: if it is a first-level abnormality or a second-level abnormality, the edge computing gateway immediately pushes the data to a central server with the highest priority through a priority queue controller, the highest priority pushing bypasses the regular queue of the TCP stack for direct sending, and the priority queue controller is an independent FPGA logic unit, which integrates 8-level hardware queues, each queue is configured with an independent DMA descriptor ring, and the highest priority data is directly written into the 0-level DMA descriptor ring and triggers a network card hardware sending interrupt; if it is redundant data, it is temporarily stored in a local cache, the local cache adopts a zero-copy ring buffer structure, the buffer head pointer is directly managed by a DMA controller of the edge computing gateway, and the CPU is avoided to participate in memory copying; S500, the edge computing gateway monitors the connection state with the center server in real time through a heartbeat monitoring link, and automatically switches to an autonomous mode when detecting that the intranet connection is interrupted, directly drives a GPIO interface to control a peripheral audible and visual alarm device according to a local strategy, and writes key abnormal data into a local non-volatile memory, and after the network is restored, preferentially uploads the accumulated alarm data, wherein the heartbeat monitoring link adopts a bidirectional UDP heartbeat packet mechanism, a heartbeat period is 500 milliseconds, and three continuous timeouts are determined as the intranet connection being interrupted, and the bidirectional UDP heartbeat packet carries a current data accumulation amount B of the edge computing gateway and a processing queue length Q of the center server, and the center server dynamically adjusts the heartbeat period according to the Q value, and when Q>1000, the heartbeat period is actively extended to 1000 milliseconds to reduce network pressure.

2. The method of claim 1, wherein, In the fixed-point number operation, when α=0.2~0.3, the specific mapping relationship configured by the table lookup method is: α=0.2→right shift 3 bits; α=0.25→right shift 2 bits; α=0.3→right shift 2 bits and subtract right shift 4 bits; The table lookup method is stored in the startup configuration Flash of the edge computing gateway, occupies 16 bytes of space, and is loaded into the instruction cache of the CPU by BootLoader during system power-on initialization.

3. The method of claim 1, wherein, In the adaptive adjustment mechanism, the network load L is calculated by the edge computing gateway by monitoring the queue length of the data packets to be sent in a unit of time, the sensor sampling frequency F is a system preset value, and the network load L / sensor sampling frequency F ratio is stored in a 16-bit fixed-point number format, the load monitoring interrupt service program is executed every 500 milliseconds, the N value is updated according to the network load L / sensor sampling frequency F ratio, and the sliding window size is adjusted synchronously, the sliding window size adjustment is realized by modifying the cyclic buffer pointer modulus value, and there is no need to reallocate memory.

4. The method of claim 1, wherein, The three-level flow decision structure is realized in the Cortex-M4 core by the following methods: The three functions of the hard threshold comparator, the mutation rate accumulator and the statistical interval discriminator are encapsulated as an inline assembly code block, and the global interrupt is turned off by the __disable_irq() instruction before execution; After the decision is made, the interrupt is restored by __enable_irq(), ensuring that the entire decision process is continuously executed on the CPU pipeline and cannot be preempted, and the time window of the atomic execution is less than 12 microseconds.

5. The method of claim 1, wherein, In the FPGA logic unit, the DMA descriptor ring of the 8-level hardware queue is configured as: Level 0: dedicated for abnormal data, 128 descriptors, each pointing to a 2KB data buffer; Levels 1-6: normal business data, 64 descriptors per level; Level 7: redundant data, 32 descriptors, only uploaded in batches when the network is idle; The descriptor ring is allocated in the internal Block RAM of the FPGA and interacts with the CPU through the AXI4-Lite bus.

6. The method of claim 1, wherein, The head pointer of the zero-copy ring buffer is automatically updated by the DMA controller, and the specific implementation is as follows: The network card DMA engine of the edge computing gateway is configured in a receive direction ring buffer mode, when redundant data is received, the DMA engine writes the data at the current write pointer position, the write pointer is automatically incremented by 1 and wraps around, the CPU obtains the data position by reading the write pointer register, without executing any memory copy instruction.

7. The method of claim 1, wherein, The current data backlog B carried in the bidirectional UDP heartbeat packet load and the center server processing queue length Q are encoded in TLV format, wherein: Type=0x01, Length=4 bytes, Value=B; Type=0x02, Length=4 bytes, Value=Q; The heartbeat packet is sent by the FPGA logic unit of the edge computing gateway in the user mode through the RDMA technology, bypassing the kernel network protocol stack.

8. A moving loop monitoring data processing system, characterized by, Comprise: The edge computing gateway is deployed in the monitoring site, the edge computing gateway is built-in real-time operating system, non-volatile flash memory and priority queue controller, the real-time operating system is configured to interrupt response time less than 10 microseconds, task scheduling period accurate to 1 millisecond, the priority queue controller is an independent FPGA logic unit, configured to execute the data pushing bypassing the TCP stack in step S400; The CPU core of the edge computing gateway is Cortex-M4, the frequency is configured to 168MHz, when executing the sliding window weighted average preprocessing, the floating point smoothing coefficient alpha is mapped to integer shift operation, so that the single preprocessing calculation consumes 42 clock cycles, the equivalent execution time is 250 nanoseconds; The center server is configured to receive and process priority marked data packets from the edge computing gateway, the data packets contain abnormal data sent directly bypassing the TCP stack, the data receiving thread of the center server uses the memory mapping I / O technology to directly map the network card receiving buffer to the user mode memory space, bypassing the kernel protocol stack analysis, so that the data writing average delay is less than 50 microseconds; The heartbeat monitoring link is used for bidirectional heartbeat detection, the heartbeat monitoring link is realized through the raw socket in the user mode, the heartbeat packet sending and receiving bypasses the kernel TCP / IP protocol stack, and is directly processed by the FPGA logic unit of the edge computing gateway, so as to ensure that the heartbeat detection delay is less than 5 milliseconds.

9. The system of claim 8, wherein, The memory mapping I / O technology is specifically implemented as: The center server maps the receiving buffer BAR space of the PCIe network card through the mmap() system call to the user mode address space of the monitoring process, the monitoring process detects the buffer update in a polling mode rather than an interrupt mode, when the FPGA logic unit writes the data packet, the monitoring process reads the data through the CAS atomic instruction, so that the data writing delay is reduced from the traditional 200 microseconds to 45 microseconds.

10. The system of claim 8, wherein, The heartbeat monitoring link is internally integrated with a heartbeat state machine in the FPGA logic unit. The state machine includes four states: IDLE, SEND, WAIT, and TIMEOUT. The state transition is driven by a 500 ms hardware timer. When the timeout occurs consecutively for three times, the state machine outputs a network disconnection signal, which directly triggers the GPIO driving relay controller without the intervention of the CPU, ensuring that the trigger time of the network disconnection to the audible and visual alarm is less than 15 ms.

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