Coarse-grained reconfigurable architecture loop mapping method and device based on graph neural network

Abstract

The invention discloses a coarse-grained reconfigurable architecture cyclic mapping method and device based on a graph neural network, and relates to the technical field of computer reconfigurable computing. The method comprises the following steps: based on a priority prediction model, performing list scheduling according to a data flow diagram and hardware information to obtain a list scheduling table; performing modular scheduling according to the data flow diagram and the hardware information; pre-scheduling the data flow diagram on the basis of a list scheduling table according to the modular data flow diagram and the time extension coarse-grained array to obtain a time step attribute data flow diagram; obtaining a mapping result by using a mapping algorithm based on pattern diagram matching according to the time step attribute data flow diagram on the basis of the time extension coarse-grained array; based on the hardware information, processing unit isomorphism verification is carried out according to the mapping result; and compiling the verified mapping result to obtain an executable configuration information file. The invention provides an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on a graph neural network.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer reconfigurable computing, in particular to a coarse-grained reconfigurable architecture loop mapping method and device based on a graph neural network. BACKGROUND

[0002] With the rapid development of big data, artificial intelligence and other technologies, the demand for computing resources of compute-intensive applications is increasing. Traditional chip architecture gradually reaches a bottleneck in performance and energy efficiency, and it is difficult to meet the growing computing demand. As a new hardware architecture, the coarse-grained reconfigurable architecture (CGRA) compiler combines the flexibility of general-purpose processors such as CPU and GPU and the high performance of application-specific integrated circuits (ASIC), and becomes an effective way to solve the acceleration problem of compute-intensive applications.

[0003] CGRA can efficiently execute various computing tasks through its highly parallel processing element array (PEA) and dynamic reconfigurability. CGRA compiler faces great challenges in generating effective mapping results for complex applications, especially within a limited time. Loop mapping, as a key step in the CGRA compilation process, directly affects the performance of CGRA.

[0004] The main task of loop mapping is to map the data flow graph (DFG) of the loop kernel to the PEA of CGRA to optimize the execution performance of the loop on CGRA. This process needs to minimize the start-up interval of loop iterations, that is, the minimum clock cycle number between consecutive iterations. With the increase of DFG size, the complexity of loop mapping problem increases sharply, becoming the main bottleneck in CGRA compilation process.

[0005] CGRA compiler uses a variety of methods to solve the loop mapping problem, including heuristic methods and optimization-based methods. Heuristic methods such as simulated annealing can find approximate optimal solutions within a reasonable time, but it is difficult to guarantee the optimality of the solution; optimization-based methods such as integer linear programming (ILP) can find optimal solutions, but the computational complexity is extremely high, and it takes a long time to solve large and complex loop mapping problems.

[0006] In the prior art, there is a lack of an efficient and accurate coarse-grained reconfigurable architecture loop mapping method based on a graph neural network. SUMMARY

[0007] In order to solve the technical problems that the existing coarse-grained reconfigurable architecture compiler has a huge search space and a long solution time for the loop mapping problem of a complex application, an embodiment of the present application provides a coarse-grained reconfigurable architecture loop mapping method and device based on a graph neural network. The technical solution is as follows:

[0008] In one aspect, a coarse-grained reconfigurable architecture loop mapping method based on a graph neural network is provided. The method is implemented by a coarse-grained reconfigurable architecture loop mapping device, and the method comprises the following steps:

[0009] A general graph data set and a preset CGRA+DFG data set are used to generate operation priority labels using an integer linear programming method. A training data set is constructed based on the general graph data set, the preset CGRA+DFG data set, and the operation priority labels.

[0010] A model structure based on a graph neural network is used to construct a to-be-trained priority prediction model. The to-be-trained priority prediction model is optimized and trained using the training data set based on a ranking loss function, and a priority prediction model is obtained.

[0011] In the loop mapping task of an application program, current task information is read, and a data flow graph and hardware information are obtained.

[0012] Based on the priority prediction model, list scheduling is performed based on the data flow graph and the hardware information, and a list scheduling table is obtained.

[0013] Based on a data flow critical path analysis method and a CGRA resource conflict detection algorithm, module scheduling is performed based on the data flow graph and the hardware information, and a module data flow graph and a time-expanded coarse-grained array are obtained.

[0014] Based on the list scheduling table, the data flow graph is pre-scheduled based on the module data flow graph and the time-expanded coarse-grained array, and a time step attribute data flow graph is obtained.

[0015] Based on the time-expanded coarse-grained array, a mapping algorithm based on pattern graph matching is used to obtain a mapping result based on the time step attribute data flow graph.

[0016] Based on the hardware information, processing unit isomorphism verification is performed based on the mapping result, and a verified mapping result is obtained. The verified mapping result is compiled to obtain an executable configuration information file.

[0017] In another aspect, a coarse-grained reconfigurable architecture loop mapping device based on a graph neural network is provided. The device is applied to a coarse-grained reconfigurable architecture loop mapping method based on a graph neural network, and the device comprises the following components:

[0018] The training data acquisition module is configured to generate operation priority labels by using an integer linear programming method based on a general graph data set and a preset CGRA+DFG data set; and construct a training data set based on the general graph data set, the preset CGRA+DFG data set, and the operation priority labels.

[0019] The prediction model training module is configured to construct a to-be-trained priority prediction model based on a model structure of a graph neural network; and optimize and train the to-be-trained priority prediction model based on a ranking loss function and by using the training data set, to obtain a priority prediction model.

[0020] The task information acquisition module is configured to read current task information, obtain a data flow graph, and obtain hardware information in a loop mapping task of an application program.

[0021] The list scheduling module is configured to perform list scheduling based on the priority prediction model, the data flow graph, and the hardware information, to obtain a list scheduling table.

[0022] The module scheduling module is configured to perform module scheduling based on a data flow critical path analysis method and a CGRA resource conflict detection algorithm, the data flow graph, and the hardware information, to obtain a module data flow graph and a time-expanded coarse-grained array.

[0023] The pre-scheduling module is configured to perform pre-scheduling on the data flow graph based on the list scheduling table, the module data flow graph, and the time-expanded coarse-grained array, to obtain a time-step attribute data flow graph.

[0024] The result mapping module is configured to obtain a mapping result by using a mapping algorithm based on pattern graph matching, based on the time-step attribute data flow graph and the time-expanded coarse-grained array.

[0025] The isomorphism verification module is configured to perform processing unit isomorphism verification based on the mapping result and the hardware information, to obtain a verified mapping result; and compile the verified mapping result, to obtain an executable configuration information file.

[0026] In another aspect, a coarse-grained reconfigurable architecture loop mapping device is provided, which includes a processor and a memory having computer readable instructions stored thereon, the computer readable instructions being executed by the processor to implement any one of the above-described graph neural network-based coarse-grained reconfigurable architecture loop mapping methods.

[0027] In another aspect, a computer readable storage medium is provided, which stores at least one instruction, the at least one instruction being loaded and executed by a processor to implement any one of the above-described graph neural network-based coarse-grained reconfigurable architecture loop mapping methods.

[0028] The technical scheme provided by the embodiment of the present application brings at least the following beneficial effects:

[0029] The present application provides a coarse-grained reconfigurable architecture loop mapping method based on a graph neural network, which decomposes the loop mapping problem into two independent stages of pre-scheduling and loop mapping through a GNN scheduling decoupling mechanism, avoids resource competition conflicts in the traditional single-stage method, significantly improves the mapping success rate, effectively reduces the compilation retry probability, introduces a graph isomorphism network model to automatically learn the topological features and node dependency of the data flow graph, significantly improves the accuracy and stability of the scheduling decision, constructs a time expansion model to realize fine-grained resource modeling in the time-space dimension, makes the path search process more comprehensive and efficient, intelligently predicts the node priority to assess the scheduling risk of the operation node under resource constraints in advance, actively avoids high-conflict areas in the pre-scheduling stage, effectively improves the hardware resource utilization rate, and generates a high-performance mapping scheme that meets the architecture constraints. The present application is an efficient and accurate coarse-grained reconfigurable architecture loop mapping method based on a graph neural network. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0031] Figure 1 is a flow chart of a coarse-grained reconfigurable architecture loop mapping method based on a graph neural network provided by the embodiment of the present application;

[0032] Figure 2 is a block diagram of a coarse-grained reconfigurable architecture loop mapping device based on a graph neural network provided by the embodiment of the present application;

[0033] Figure 3 is a structural schematic diagram of a coarse-grained reconfigurable architecture loop mapping device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the present application will be described below with reference to the drawings.

[0035] In the embodiments of the present application, the words "example", "for example", etc. are used to represent an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the word "example" is intended to present the concept in a specific manner. In addition, in the embodiments of the present application, the meaning expressed by "and / or" can be both, or can be one of the two.

[0036] In the embodiments of the present application, "image" and "picture" can be used interchangeably, and it should be pointed out that their meanings are consistent when their differences are not emphasized. "Of", "corresponding" and "corresponding" can be used interchangeably, and it should be pointed out that their meanings are consistent when their differences are not emphasized.

[0037] In the embodiments of the present application, sometimes the subscript such as W1 can be written in the form of non-subscript such as W1, and their meanings are consistent when their differences are not emphasized.

[0038] In order to make the technical problems, technical solutions and advantages to be solved by the present application more clear, the following will be described in detail in conjunction with the drawings and specific embodiments.

[0039] The embodiment of the present application provides a coarse-grained reconfigurable architecture cycle mapping method based on a graph neural network. The method can be implemented by a coarse-grained reconfigurable architecture cycle mapping device, which can be a terminal or a server. As shown in the flow chart of the coarse-grained reconfigurable architecture cycle mapping method based on the graph neural network, the processing flow of the method can include the following steps: Figure 1

[0040] S1, using a general graph dataset and a preset CGRA+DFG dataset, using an integer linear programming method to generate an operation priority label; constructing a training dataset according to the general graph dataset, the preset CGRA+DFG dataset and the operation priority label;

[0041] In a feasible implementation manner, the present application adopts a general graph dataset (TUDataset: A collection of benchmark datasets for learning with graphs, TUDataset) and a preset CGRA+DFG dataset, uses an integer linear programming method to generate an operation priority label for training, and constructs a training dataset according to the above contents.

[0042] Integer linear programming (Integer Linear Programming, ILP) is an extension of linear programming, which requires part or all of the decision variables to take integer values. This method is widely used when variables must represent indivisible units (such as personnel, equipment, project selection, etc.).

[0043] ​S2, constructing a priority prediction model to be trained based on a model structure of a graph neural network; based on a ranking loss function, using a training data set to optimize and train the priority prediction model to be trained, to obtain a priority prediction model;

[0044] Optionally, based on the ranking loss function, the training data set is used to optimize and train the priority prediction model to be trained, to obtain the priority prediction model, including:

[0045] According to the training data set, the operation priority prediction is performed using the priority prediction model to be trained, to obtain a first predicted priority label;

[0046] Based on the ranking loss function, the training data set and the first predicted priority label are calculated to obtain a ranking loss;

[0047] According to the ranking loss, the priority prediction model to be trained is optimized in parameters, to obtain the priority prediction model.

[0048] In a feasible implementation, the priority prediction model is constructed based on a graph neural network (GNN); the model is trained using a training data set, and the model is optimized using a ranking loss function.

[0049] In the training process, a curriculum learning strategy is adopted to gradually increase the complexity of the training samples; an adversarial sample is introduced to enhance the robustness of the model; and a dynamic weight adjustment mechanism is deployed to balance the precision and the generalization ability. After the training is completed, the final performance of the model needs to be evaluated on an independent test set to ensure the generalization ability.

[0050] The priority prediction model includes a graph isomorphism network layer and a feed-forward neural network layer.

[0051] The graph isomorphism network layer is used to extract an operation embedding representation of the data flow graph.

[0052] The feed-forward neural network layer is used to regress a priority label of the operation embedding representation.

[0053] In a feasible implementation, in the priority prediction model, an embedding representation of each operation is learned through a graph isomorphism network (GIN); a feed-forward neural network (FFN) is used to regress the embedding representation to predict the priority of the operation.

[0054] S3, in the loop mapping task of the application program, current task information is read to obtain a data flow graph and hardware information;

[0055] The data flow graph includes operation nodes and relationship dependency edges.

[0056] The hardware information includes a coarse-grained reconfigurable array; the coarse-grained reconfigurable array includes a processing unit array size, a functional unit type, a functional unit quantity distribution, a data routing delay constraint, and a storage bandwidth limit.

[0057] In an available implementation, a data flow graph (DFG) is obtained from a loop kernel of an application; the hardware information includes a coarse-grained reconfigurable array, and a description of the coarse-grained reconfigurable array includes but is not limited to a processing unit array size, a functional unit type and quantity distribution, a data routing delay constraint, and a storage bandwidth limit.

[0058] By obtaining detailed data flow graph and hardware information, comprehensive and accurate basic information can be provided for subsequent processes, and such comprehensive data collection can provide key constraint conditions required in subsequent processes, thereby improving mapping efficiency.

[0059] S4, based on a priority prediction model, performing list scheduling according to the data flow graph and the hardware information to obtain a list scheduling table;

[0060] Optionally, based on the priority prediction model, performing list scheduling according to the data flow graph and the hardware information to obtain a list scheduling table, including:

[0061] Based on a dependent edge of the data flow graph, performing operation filtering according to an operation node of the data flow graph to obtain a ready operation set;

[0062] According to the ready operation set, performing operation priority prediction using the priority prediction model to obtain a second predicted priority label;

[0063] Based on the hardware information, performing execution resource verification on the ready operation set to obtain a verified operation set;

[0064] Based on the second predicted priority label, performing scheduling according to the verified operation set, and recording an operation time period set;

[0065] According to the verified operation set and the operation time period set, obtaining a list scheduling table.

[0066] In an available implementation, a priority prediction model is used to generate node priority, operations are sorted and scheduled, execution positions of each operation in a time dimension are determined, and preliminary scheduling arrangement results are obtained by comprehensively considering previous operations.

[0067] The second prediction priority label can make high-priority nodes preferentially bind to high-throughput processing elements (PEs) to avoid resource contention; by performing list scheduling, the state of node dependence is dynamically detected during scheduling, and new ready nodes are released to the queue, which can avoid resource idling and make resource allocation conform to the overall optimization goal; by allocating time steps to each operation, not only can timing conflicts be effectively eliminated, but also high-priority nodes can be compressed by moving forward in time steps.

[0068] In this step, the set of operation nodes is divided into three subsets: the completed operation set (V_F), the ready operation set (V_R), and the unscheduled operation set (V_U). All operations in the data flow graph are traversed and classified according to their dependence relationships. If an operation has no precedent dependence, it is included in the ready operation set V_R, and the rest remains in the unscheduled operation set V_U, while the time step counter is set to zero.

[0069] If the current time step exceeds the threshold (t>T_max) or a deadlock occurs (V_R is empty but V_U is not empty), the scheduling is determined to fail. Then, the resource allocation phase is entered: all processing elements in the coarse-grained reconfigurable architecture (CGRA) are traversed, and only the resources that are idle in the current period are retained;

[0070] Next, the operation with the highest priority from V_R is selected for scheduling. The candidate operation is verified for effectiveness, and if the dependence is satisfied and the hardware resources are available, the operation is allocated and its state is updated; if the conditions are not met, the next operation is skipped and the process continues.

[0071] After resource allocation is completed, the constraints of the successor operations are released according to the dependence relationship, and the operations that meet the conditions are added to the ready operation set V_R, while the time step counter is incremented and the next period is entered. This process continues iteratively until all operations are scheduled (i.e., V_U is empty), at which point the complete scheduling scheme is output; if the termination condition is not met, the next loop is entered.

[0072] S5, based on the data flow critical path analysis method and the CGRA resource conflict detection algorithm, the module scheduling is performed according to the data flow graph and the hardware information to obtain a module data flow graph and a time-expanded coarse-grained array;

[0073] Optionally, based on the data flow critical path analysis method and the CGRA resource conflict detection algorithm, the module scheduling is performed according to the data flow graph and the hardware information to obtain a module data flow graph and a time-expanded coarse-grained array, including:

[0074] Based on the critical path analysis method of data flow, the initiation interval is calculated according to the data flow graph to obtain the lower limit of the cyclic iteration interval of data flow constraints;

[0075] Based on the hardware information, a coarse-grained reconfigurable array is obtained; based on the CGRA resource conflict detection algorithm, the startup interval is calculated according to the coarse-grained reconfigurable array to obtain the lower limit of the cyclic iteration interval of resource constraints.

[0076] Based on the lower bound of the loop iteration interval for data flow constraints and the lower bound of the loop iteration interval for resource constraints, the minimum value is selected as the loop iteration interval.

[0077] Based on the time period of the data flow graph, a modulo operation is performed on the loop iteration interval to obtain a modulo data flow graph;

[0078] Based on the iteration interval and hardware information, the coarse-grained reconfigurable array is temporally extended to obtain a time-extended coarse-grained array.

[0079] In one feasible implementation, by using an incremental update mechanism that dynamically adjusts the cyclic iteration interval II value, a II lower bound prediction based on data flow critical path analysis, and a time-extended CGRA resource conflict detection algorithm, invalid iterations can be avoided, the spatiotemporal stability of bound nodes can be maintained, and oscillations in the optimization process can be prevented.

[0080] S6. Based on the list scheduling table, pre-schedule the data flow graph according to the modular data flow graph and the time-extended coarse-grained array to obtain the time-step attribute data flow graph.

[0081] In one feasible implementation, the data flow graph is pre-scheduled based on a list scheduling table, and labels with time step attributes are added to the data flow graph.

[0082] Polyhedral cyclic transformations are performed before mapping to optimize the storage efficiency, operational parallelism, and tensor shape of the loops. The cyclic transformations used include cyclic tiling, cyclic merging, cyclic swapping, cyclic fission, cyclic inversion, and cyclic unrolling.

[0083] S7. Based on the time-extended coarse-grained array, the mapping result is obtained by using a pattern graph matching-based mapping algorithm according to the time step attribute data flow graph.

[0084] Optionally, based on the time-extended coarse-grained array, and according to the time-step attribute data flow graph, a mapping algorithm based on pattern graph matching is used to obtain the mapping result, including:

[0085] Based on the time-extended coarse-grained array, the node matching probability is calculated according to the time-step attribute data flow graph.

[0086] Based on the node matching probability, the nodes of the time step attribute data flow graph are sorted in descending order to obtain the node criticality order;

[0087] Based on the time-step attribute data flow graph, perform neighborhood connection relationship-node label filtering to obtain a candidate node set;

[0088] Based on the node criticality order, the temporally extended coarse-grained array is mapped according to the candidate node set to obtain the mapping result.

[0089] In one feasible implementation, for each node in the time-step attribute data flow graph, its matching probability is evaluated by calculating the proportion of nodes in the time-extended coarse-grained array that share the same label and have large in-degree and out-degree.

[0090] Nodes are sorted according to their probability and degree, prioritizing the search of strongly constrained nodes. Generating a node sequence helps reduce the width of the search tree in the early stages of the search. Candidate nodes are filtered by set-level connectivity and node labels to determine the candidate set for the next matching step.

[0091] Explore the neighborhood of candidate nodes to facilitate subsequent matching. Starting from an empty mapping state, gradually search for new matching pairs until a complete mapping solution is found.

[0092] In this step, through a comprehensive analysis of the relationships and connectivity between sets, the algorithm proactively identifies mapping pairs that can match in the current step but may not generate new mapping pairs in subsequent iterations. The output is the mapping results on CGRA, including the specific execution time period and processing unit location for each operation.

[0093] S8. Based on hardware information, perform isomorphic verification of the processing unit according to the mapping result to obtain the verification mapping result; compile the verified mapping result to obtain an executable configuration information file.

[0094] In one feasible implementation, in the core verification step, it is determined whether the topological isomorphism is satisfied: if the data flow structure is completely matched with the PE array ("isomorphic verification" passes), the final mapping configuration is output; if the verification fails, the iteration interval (II+1) is increased to relax the timing constraints, and the first step is returned to regenerate TEC, forming a closed-loop optimization until a valid solution is found.

[0095] The verification mapping results are transformed into an executable configuration information file containing a binary control instruction set that can be directly loaded by hardware. This executable configuration information file is the core output for industrial deployment. Through spatiotemporal decoupling and hardware-aware compilation, it solves the NP-hard complexity problem of CGRA deployment, achieving seamless implementation from algorithm theory to industrial chips.

[0096] This invention proposes a coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks. By decoupling the scheduling mechanism of GNNs, the cyclic mapping problem is decomposed into two independent stages: pre-scheduling and cyclic mapping. This avoids resource contention conflicts in traditional single-stage methods, significantly improving the mapping success rate and effectively reducing the probability of compilation retry. By introducing a graph isomorphic network model, the topological features and node dependencies of the data flow graph can be automatically learned, significantly improving the accuracy and stability of scheduling decisions. By constructing a time-extended model, fine-grained resource modeling is achieved in the spatiotemporal dimension, making the path search process more comprehensive and efficient. Through intelligent prediction of node priorities, the scheduling risk of operating nodes under resource constraints can be assessed in advance, and high-conflict areas can be actively avoided in the pre-scheduling stage, effectively improving hardware resource utilization and generating high-performance mapping schemes that conform to architectural constraints. This invention is an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks.

[0097] Figure 2 This is a block diagram of a coarse-grained reconfigurable architecture cyclic mapping device based on graph neural networks, provided in an embodiment of the present invention. This device is used in a coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks. (Refer to...) Figure 2 The device includes a training data acquisition module 210, a prediction model training module 220, a task information acquisition module 230, a list scheduling module 240, a model scheduling module 250, a pre-scheduling module 260, a result mapping module 270, and a isomorphic verification module 280. Among them:

[0098] The training data acquisition module 210 is used to generate operation priority labels using an integer linear programming method with a general graph dataset and a preset CGRA+DFG dataset; and to construct a training dataset based on the general graph dataset, the preset CGRA+DFG dataset and the operation priority labels.

[0099] The prediction model training module 220 is used to construct a priority prediction model to be trained based on the model structure of a graph neural network; and to optimize and train the priority prediction model to be trained using the training dataset based on the ranking loss function to obtain the priority prediction model.

[0100] The task information acquisition module 230 is used to read the current task information and obtain the data flow graph and hardware information in the application's cyclic mapping task.

[0101] The list scheduling module 240 is used to perform list scheduling based on the priority prediction model, according to the data flow graph and hardware information, and obtain the list scheduling table.

[0102] The modular scheduling module 250 is used to perform modular scheduling based on the data flow critical path analysis method and the CGRA resource conflict detection algorithm, according to the data flow graph and hardware information, to obtain the modular data flow graph and the time-extended coarse-grained array.

[0103] The pre-scheduling module 260 is used to pre-schedule the data flow graph based on the list scheduling table, according to the modular data flow graph and the time-extended coarse-grained array, to obtain the time-step attribute data flow graph.

[0104] The result mapping module 270 is used to obtain the mapping result based on the time-extended coarse-grained array and the time step attribute data flow graph using a pattern graph matching-based mapping algorithm.

[0105] The isomorphic verification module 280 is used to perform isomorphic verification of the processing unit based on the hardware information and the mapping result to obtain the verification mapping result; and to compile the verified mapping result to obtain an executable configuration information file.

[0106] The data flow graph includes operation nodes and relational dependency edges;

[0107] Hardware information includes coarse-grained reconfigurable arrays; coarse-grained reconfigurable arrays include processing unit array size, functional unit type, functional unit quantity distribution, data routing latency constraints, and storage bandwidth limitations.

[0108] Optionally, the prediction model training module 220 is further used for:

[0109] Based on the training dataset, the operation priority is predicted using the priority prediction model to be trained, and the first predicted priority label is obtained.

[0110] The ranking loss is calculated based on the ranking loss function, using the training dataset and the first predicted priority label.

[0111] Based on the ranking loss, the parameters of the priority prediction model to be trained are optimized to obtain the priority prediction model.

[0112] The priority prediction model includes a graph isomorphic network layer and a feedforward neural network layer.

[0113] Graph isomorphic network layers are used to extract operational embedding representations of data flow graphs;

[0114] The feedforward neural network layer is used to embed priority labels in the regression prediction operation.

[0115] Optionally, the list scheduling module 240 is further configured to:

[0116] Based on the dependency edges of the data flow graph, operations are filtered according to the operation nodes of the data flow graph to obtain a set of ready operations;

[0117] Based on the ready operation set, the operation priority is predicted using the priority prediction model to obtain the second predicted priority label;

[0118] Based on hardware information, the ready operation set is executed resource verification to obtain the verified operation set.

[0119] Based on the second predicted priority label, the scheduling is performed according to the verified operation set, and the operation time period set is recorded;

[0120] Based on the verified operation set and the operation time period set, obtain the list scheduling table.

[0121] Optionally, the module scheduling module 250 is further used for:

[0122] Based on the critical path analysis method of data flow, the initiation interval is calculated according to the data flow graph to obtain the lower limit of the cyclic iteration interval of data flow constraints;

[0123] Based on the hardware information, a coarse-grained reconfigurable array is obtained; based on the CGRA resource conflict detection algorithm, the startup interval is calculated according to the coarse-grained reconfigurable array to obtain the lower limit of the cyclic iteration interval of resource constraints.

[0124] Based on the lower bound of the loop iteration interval for data flow constraints and the lower bound of the loop iteration interval for resource constraints, the minimum value is selected as the loop iteration interval.

[0125] Based on the time period of the data flow graph, a modulo operation is performed on the loop iteration interval to obtain a modulo data flow graph;

[0126] Based on the iteration interval and hardware information, the coarse-grained reconfigurable array is temporally extended to obtain a time-extended coarse-grained array.

[0127] Optionally, the result mapping module 270 is further used for:

[0128] Based on the time-extended coarse-grained array, the node matching probability is calculated according to the time-step attribute data flow graph.

[0129] Based on the node matching probability, the nodes of the time step attribute data flow graph are sorted in descending order to obtain the node criticality order;

[0130] Based on the time-step attribute data flow graph, perform neighborhood connection relationship-node label filtering to obtain a candidate node set;

[0131] Based on the node criticality order, the temporally extended coarse-grained array is mapped according to the candidate node set to obtain the mapping result.

[0132] This invention proposes a coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks. By decoupling the scheduling mechanism of GNNs, the cyclic mapping problem is decomposed into two independent stages: pre-scheduling and cyclic mapping. This avoids resource contention conflicts in traditional single-stage methods, significantly improving the mapping success rate and effectively reducing the probability of compilation retry. By introducing a graph isomorphic network model, the topological features and node dependencies of the data flow graph can be automatically learned, significantly improving the accuracy and stability of scheduling decisions. By constructing a time-extended model, fine-grained resource modeling is achieved in the spatiotemporal dimension, making the path search process more comprehensive and efficient. Through intelligent prediction of node priorities, the scheduling risk of operating nodes under resource constraints can be assessed in advance, and high-conflict areas can be actively avoided in the pre-scheduling stage, effectively improving hardware resource utilization and generating high-performance mapping schemes that conform to architectural constraints. This invention is an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks.

[0133] Figure 3 This is a schematic diagram of the structure of a coarse-grained reconfigurable architecture cyclic mapping device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, a coarse-grained reconfigurable architecture cyclic mapping device may include the above-mentioned Figure 2 The diagram illustrates a coarse-grained reconfigurable architecture cyclic mapping device based on graph neural networks. Optionally, the coarse-grained reconfigurable architecture cyclic mapping device 310 may include a first processor 2001.

[0134] Optionally, the coarse-grained reconfigurable architecture cyclic mapping device 310 may also include a memory 2002 and a transceiver 2003.

[0135] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0136] The following is combined with Figure 3 A detailed description of each component of the coarse-grained reconfigurable architecture cyclic mapping device 310 is provided below:

[0137] The first processor 2001 is the control center of the coarse-grained reconfigurable architecture cyclic mapping device 310. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0138] Optionally, the first processor 2001 can perform various functions of the coarse-grained reconfigurable architecture cyclic mapping device 310 by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0139] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 3 CPU0 and CPU1 are shown in the diagram.

[0140] In a specific implementation, as one example, the coarse-grained reconfigurable architecture cyclic mapping device 310 may also include multiple processors, for example... Figure 3 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0141] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0142] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently, and may be accessed through the interface circuit of the coarse-grained reconfigurable architecture cyclic mapping device 310. Figure 3 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0143] The transceiver 2003 is used to communicate with network devices or with terminal devices.

[0144] Alternatively, transceiver 2003 may include a receiver and a transmitter. Figure 3 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0145] Optionally, the transceiver 2003 can be integrated with the first processor 2001 or exist independently, and can be interfaced with the coarse-grained reconfigurable architecture cyclically mapped device 310 via its interface circuitry. Figure 3 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0146] It should be noted that, Figure 3 The structure of the coarse-grained reconfigurable architecture cyclic mapping device 310 shown does not constitute a limitation on the router. Actual coarse-grained reconfigurable architecture cyclic mapping devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0147] Furthermore, the technical effects of the coarse-grained reconfigurable architecture cyclic mapping device 310 can be referred to the technical effects of the coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks described in the above method embodiments, and will not be repeated here.

[0148] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or it may be any conventional processor, etc.

[0149] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0150] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0151] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0152] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0153] It should be understood that, in various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0154] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0155] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0156] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0157] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0158] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0159] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0160] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks, characterized in that, The method includes: Using a general graph dataset and a pre-defined CGRA+DFG dataset, operation priority labels are generated using an integer linear programming method; a training dataset is constructed based on the general graph dataset, the pre-defined CGRA+DFG dataset, and the operation priority labels. A priority prediction model to be trained is constructed based on the model structure of a graph neural network; based on the ranking loss function, the priority prediction model to be trained is optimized and trained using the training dataset to obtain the priority prediction model. In the application's cyclic mapping task, read the current task information to obtain the data flow graph and hardware information; Based on the priority prediction model, a list scheduling table is obtained by performing list scheduling based on the data flow graph and hardware information. Based on the data flow critical path analysis method and the CGRA resource conflict detection algorithm, modular scheduling is performed according to the data flow graph and hardware information to obtain the modular data flow graph and time-extended coarse-grained array. Based on the list scheduling table, the data flow graph is pre-scheduled according to the modular data flow graph and the time-extended coarse-grained array to obtain the time-step attribute data flow graph; Based on the time-extended coarse-grained array, the mapping result is obtained by using a pattern graph matching-based mapping algorithm according to the time step attribute data flow graph; Based on the hardware information, isomorphic verification of the processing unit is performed according to the mapping result to obtain the verification mapping result; the verified mapping result is then compiled to obtain an executable configuration information file.

2. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 1, characterized in that, The process of optimizing and training the priority prediction model based on the ranking loss function using the training dataset to obtain the priority prediction model includes: Based on the training dataset, the operation priority is predicted using the priority prediction model to be trained, and the first predicted priority label is obtained. The ranking loss is calculated based on the ranking loss function, using the training dataset and the first predicted priority label. Based on the ranking loss, the parameters of the priority prediction model to be trained are optimized to obtain the priority prediction model.

3. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 2, characterized in that, The priority prediction model includes a graph isomorphic network layer and a feedforward neural network layer; The graph isomorphic network layer is used to extract the operation embedding representation of the data flow graph; The feedforward neural network layer is used to embed priority labels in the regression prediction operation.

4. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 1, characterized in that, The data flow graph includes operation nodes and relational dependency edges; The hardware information includes a coarse-grained reconfigurable array; the coarse-grained reconfigurable array includes the processing unit array size, functional unit type, functional unit quantity distribution, data routing delay constraints, and storage bandwidth limitations.

5. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 1, characterized in that, The priority prediction model, based on the data flow graph and hardware information, performs list scheduling to obtain a list scheduling table, including: Based on the dependency edges of the data flow graph, operations are filtered according to the operation nodes of the data flow graph to obtain a set of ready operations; Based on the ready operation set, the operation priority is predicted using the priority prediction model to obtain the second predicted priority label; Based on hardware information, the ready operation set is executed resource verification to obtain the verified operation set. Based on the second predicted priority label, the scheduling is performed according to the verified operation set, and the operation time period set is recorded; Based on the verified operation set and the operation time period set, obtain the list scheduling table.

6. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 1, characterized in that, The data flow critical path analysis method and CGRA resource conflict detection algorithm perform modular scheduling based on the data flow graph and hardware information to obtain a modular data flow graph and a time-extended coarse-grained array, including: Based on the critical path analysis method of data flow, the initiation interval is calculated according to the data flow graph to obtain the lower limit of the cyclic iteration interval of data flow constraints; Based on the hardware information, a coarse-grained reconfigurable array is obtained; based on the CGRA resource conflict detection algorithm, the startup interval is calculated according to the coarse-grained reconfigurable array to obtain the lower limit of the cyclic iteration interval of resource constraints. Based on the lower bound of the loop iteration interval for data flow constraints and the lower bound of the loop iteration interval for resource constraints, the minimum value is selected as the loop iteration interval. Based on the time period of the data flow graph, a modulo operation is performed on the loop iteration interval to obtain a modulo data flow graph; Based on the iteration interval and hardware information, the coarse-grained reconfigurable array is temporally extended to obtain a time-extended coarse-grained array.

7. The coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks according to claim 1, characterized in that, The time-extended coarse-grained array, based on the time-step attribute data flow graph, uses a pattern graph matching-based mapping algorithm to obtain the mapping result, including: Based on the time-extended coarse-grained array, the node matching probability is calculated according to the time-step attribute data flow graph. Based on the node matching probability, the nodes of the time step attribute data flow graph are sorted in descending order to obtain the node criticality order; Based on the time-step attribute data flow graph, perform neighborhood connection relationship-node label filtering to obtain a candidate node set; Based on the node criticality order, the temporally extended coarse-grained array is mapped according to the candidate node set to obtain the mapping result.

8. A coarse-grained reconfigurable architecture cyclic mapping device based on graph neural networks, wherein the coarse-grained reconfigurable architecture cyclic mapping device based on graph neural networks is used to implement the coarse-grained reconfigurable architecture cyclic mapping method based on graph neural networks as described in any one of claims 1-7, characterized in that, The device includes: The training data acquisition module is used to generate operation priority labels using an integer linear programming method with a general graph dataset and a preset CGRA+DFG dataset; and to construct a training dataset based on the general graph dataset, the preset CGRA+DFG dataset, and the operation priority labels. The prediction model training module is used to construct a priority prediction model to be trained based on the model structure of a graph neural network; based on the ranking loss function, using the training dataset, the priority prediction model to be trained is optimized and trained to obtain the priority prediction model. The task information acquisition module is used to read the current task information, obtain the data flow graph and hardware information in the application's cyclic mapping task; The list scheduling module is used to perform list scheduling based on the priority prediction model, data flow graph and hardware information, and obtain the list scheduling table. The module scheduling module is used to perform module scheduling based on the data flow critical path analysis method and the CGRA resource conflict detection algorithm, according to the data flow graph and hardware information, to obtain the module data flow graph and time-extended coarse-grained array. The pre-scheduling module is used to pre-schedule the data flow graph based on the list scheduling table, the modular data flow graph, and the time-extended coarse-grained array to obtain the time-step attribute data flow graph. The result mapping module is used to obtain mapping results based on the time-extended coarse-grained array and the time-step attribute data flow graph using a pattern graph matching-based mapping algorithm. The isomorphic verification module is used to perform isomorphic verification of processing units based on hardware information and mapping results to obtain verification mapping results; the verified mapping results are then compiled to obtain an executable configuration information file.

9. A coarse-grained reconfigurable architecture cyclic mapping device, characterized in that, The coarse-grained reconfigurable architecture cyclic mapping device includes: processor; A memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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