Architecture design method of TSN network end system with dual-processor collaboration

Abstract

The invention belongs to the technical field of avionics, and particularly relates to an architecture design method of a TSN network end system with dual-processor collaboration. The system architecture comprises a main processor and a network card; a buffer A, a register A, a buffer B, a register B, a coprocessor and a protocol conversion module are arranged in the network card; the main processor performs data interaction with a buffer A and a register A in the network card; the coprocessor performs data interaction with a buffer B and a register B in the network card; the protocol conversion module performs data interaction with the buffer A, the register A, the buffer B, the register B and an external network; the main processor is used for receiving an airborne light thunder signal, a sensor signal, an avionics / electromechanical control signal and a graphic video signal, and outputting light thunder sensor data, an avionics / electromechanical control instruction and a graphic video signal; the coprocessor is used for receiving avionics network management data, network time synchronization data and built-in self-inspection data and outputting corresponding data packets.

Description

Technical Field

[0001] This invention belongs to the field of avionics technology, and specifically relates to an architecture design method for a dual-processor collaborative TSN network end system. Background Technology

[0002] In the aerospace field, Time-Sensitive Networking (TSN) is gradually establishing itself as the unified deterministic backbone of next-generation avionics and spacecraft networks, transitioning from "laboratory verification" to "real-world aircraft and mission applications," bringing significant "quantifiable and predictable" improvements to avionics system performance. TSN networks possess advantages such as "determinism, high bandwidth, and clock synchronization," enhancing the determinism of network data transmission, reducing transmission latency, and decreasing product variety and system wiring complexity. Based on TSN's excellent performance in avionics networks, aircraft designers are driving the transformation from "multi-protocol dedicated buses" to "unified TSN networks," integrating network buses from avionics, electromechanical systems, flight control, and navigation into the same protocol suite, bringing comprehensive advantages of "cost reduction, weight reduction, and predictability" to other airborne systems. However, due to differences in power consumption constraints and mission priorities across various fields, the processor computing power used in electromechanical and flight control systems is relatively low, and the computing resources used to support network interface card (NIC) functions are also relatively limited. Therefore, the functional requirements of NICs in these fields differ significantly from those of avionics NICs. In designing network interface cards (NICs) for new application areas, the differences in transmission mechanisms and the processor's allocation strategy for computing resources during TSN network operation should be given priority consideration. Summary of the Invention

[0003] Objective: This invention proposes a dual-processor collaborative TSN network end-system architecture design method based on the traditional single-processor, single-NIC end-system architecture. By rationally allocating the computing resources of the main processor and coprocessor, the load pressure on the main processor is reduced, thereby alleviating the burden on the main processor and effectively addressing the risk of main processor failure. The coprocessor can temporarily take over some network functions of the main processor and report fault status, thereby improving the security and reliability of the entire end-system. Technical solution: A method for designing a TSN network end system architecture with dual processor collaboration, the system architecture including a main processor and a network interface card; The network card has built-in buffer A, register A, buffer B, register B, coprocessor, and protocol conversion module; The main processor interacts with cache A and register A in the network card; The coprocessor interacts with buffer B and register B in the network interface card; The protocol conversion module interacts with buffer A, register A, buffer B, register B, and the external network. The main processor is used to receive airborne optical and radar signals, sensor signals, avionics / electromechanical control signals, and graphics and video signals, and output optical and radar sensor data, avionics / electromechanical control commands, and graphics and video signals. The coprocessor is used to receive avionics network management data, network time synchronization data, and internal self-test data, and output the corresponding data packets.

[0004] Furthermore, the main processor stores the data to be transmitted into the transmit area of ​​register A and writes the control information into register A; The protocol conversion module encapsulates the data into protocol frames and sends them to the external network; When the network card receives an external data frame, it performs protocol offloading and stores the data in the receive area of ​​buffer A, while marking the reception completion status through register A; The main processor periodically checks the receive completion flag bit in register A. If the receive completion flag is detected to be set, data is read from the receive area of ​​register A.

[0005] Furthermore, the coprocessor sends four types of data frames, namely: Time-Sensitive Management Protocol (TSMP) frames are used for time-sensitive protocol time synchronization. Network control and management protocol frames are used for Ethernet network management. Address resolution protocol frames and BIT transport frames; The content of the first three types of data frames comes from the main protocol configuration, while the content of the fourth type of data frames comes from the operation of the network card. After the coprocessor completes the data frame encapsulation, it sends it to the transmission arbitration module, where it is arbitrated together with the data sent by the main processor and then sent to the link in sequence. Upon receiving data, the receiving arbitration module identifies the data frame required by the coprocessor and passes the data frame to the coprocessor for processing.

[0006] Furthermore, the main processor and the coprocessor exchange status information through register A and register B, and determine each other's working status by checking the status information; The main processor periodically writes the characteristic value 32'h5A5AA5A5 into register A; when the coprocessor detects this characteristic value, it determines that the main processor is working normally and clears the characteristic value to zero. If abnormal feature values ​​are detected for three consecutive cycles, it is confirmed that the main processor has failed. Similarly, the coprocessor periodically writes the characteristic value 32'hA5A55A5A into register B; when the main processor detects this characteristic value, it determines that the coprocessor is working normally and clears it to zero. If abnormal feature values ​​are detected for three consecutive cycles, a coprocessor malfunction is confirmed. When the main processor fails, the coprocessor will receive additional interaction information between the main processor and the remote processor, and output a broadcast message indicating the node's failure status. When the coprocessor fails, the main processor will receive additional network management data and time synchronization data, and output network management response data and time synchronization correction data. After a coprocessor failure, the main processor additionally receives network management and time synchronization data, and outputs network management response data and time synchronization correction data.

[0007] Furthermore, by configuring registers A and B, different functional domains are configured for the main processor and coprocessor, enabling them to perform different functions; The normal configuration method is as follows: ① After power-on, the network card configures the functional domains of the main processor and coprocessor according to the default settings; ② If the application software on the main processor needs to change the functional domain during initialization, it should do so through the configuration register; ③ Turn on the main switch for the functional domain to enable all functions.

[0008] Furthermore, ① upon detecting a main processor failure, all functional modules are shut down to ensure the system is in a safe state; ② Update the configuration table and reconfigure the functions, adjusting the configuration according to the requirements of the new functional domain; ③ Load the new configuration and restore functionality; ④ During disconnection and restart, detected erroneous data frames should be discarded and included in the fault statistics to distinguish them from other fault phenomena.

[0009] Furthermore, ① upon detecting a coprocessor failure, all functional modules are shut down to ensure the system is in a safe state; ② Update the configuration table and reconfigure the functions, adjusting the configuration according to the requirements of the new functional domain; ③ Load the new configuration and restore functionality; ④ During disconnection and restart, detected erroneous data frames should be discarded and included in the fault statistics to distinguish them from other fault phenomena.

[0010] Furthermore, the coprocessor connects to an external debugging cable via a serial port to report status information to an external debugging terminal; and connects to the MCU on the carrier board via the I²C bus to report and record status information via the MCU.

[0011] Beneficial effects: 1) A dual-processor collaborative TSN network end-system architecture design method is proposed; 2) The implementation of this architecture can effectively reduce the load pressure of traditional avionics network cards on the main control processor, and has the characteristics of high data processing efficiency, low overall power consumption and high security. 3) This architecture is mainly applicable to TSN network end systems in avionics, electromechanical and flight control subsystems in the aerospace field. It can also be extended to other network end systems. It has the characteristics of simple interface, excellent compatibility and versatility. 4) Through flexible configuration of end system functions, when a processor fails, the functions can be temporarily migrated to another processor to maintain basic communication functions, thereby further improving the security and reliability of the system. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a dual-processor collaborative architecture; Figure 2 This is a diagram illustrating the implementation of functional domain switching. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0014] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0015] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0017] This invention proposes a dual-processor collaborative TSN network end-system architecture design, with the functional framework as follows: Figure 1 .

[0018] Its main contents are as follows: 1) This invention proposes a TSN network end-system architecture design method based on dual-processor collaboration. A coprocessor is added to the network interface card (NIC) side of the existing main processor. By balancing the computing resources between the main processor and the coprocessor, the rational allocation and execution of relevant functions of the TSN network end-system are achieved. In specific application scenarios, this design can effectively reduce the computational burden on the main processor, thereby reducing transmission latency and processor power consumption. The architecture design proposed in this invention consumes few resources and has good compatibility with the original architecture. Even when the main processor fails, the coprocessor can still process basic network information and report the fault status, which helps the end system recover quickly, thereby improving the overall system security.

[0019] 2) Architectural Comparability of Main Processor and Coprocessor: The main processor and coprocessor are architecturally equivalent and can both communicate through the network card's internal registers (e.g., Figure 1 REG, register) and cache (such as Figure 2 The BRAM / block RAM access protocol suite includes register interfaces primarily used for exchanging control and status information, while buffers are used for the interactive transmission of data packets.

[0020] 3) Functional Role of the Main Processor: The main processor is primarily responsible for processing functions closely related to the product domain, such as electromechanical control commands, flight control commands, and video images in the display and control field. The main processor acquires instructions and data information from the network interface card (NIC) and, in conjunction with the application algorithms it runs, completes critical decisions. The NIC configuration information required by both the main processor and coprocessors is loaded uniformly by the application loaded by the main processor. The main processor's configuration information is stored in cache A, and the coprocessor's configuration information is stored in cache B.

[0021] 4) Main Processor's Transmit / Receive Process: When sending data, the main processor first writes the data to be sent into buffer A, and then writes control information (such as data length, message type, transmission 5-tuple, etc.) into register A. The network interface card (NIC) logic encapsulates the data into a protocol frame and sends it to the network. When the NIC receives a data frame, it performs a protocol offload operation and stores the data in another space of the buffer, while simultaneously marking the completion status through the register. The main processor periodically queries this status flag; if the flag is detected, it reads the data from the designated buffer area.

[0022] 5) Functional Role of the Coprocessor: The coprocessor on the network interface card (NIC) side is primarily responsible for handling functions related to network protocols, such as sub-protocols of the TSN network and common network management protocols for Ethernet. The coprocessor performs closed-loop processing of relevant data, reporting only through status registers and data statistics, effectively reducing data transmission volume and facilitating decision-making by the main processor. In the event of a main processor failure, the coprocessor can temporarily take over some non-core services (incoming status display or loading backup data) and report fault information to support emergency system operation.

[0023] 6) Coprocessor's transmit / receive process: The coprocessor can send four types of data frames, namely: TSMP frames (Time-Sensitive Management Protocol Frames) are used for time synchronization; ICMP frames (Internet Control Message Protocol frames) are used for Ethernet network management; An ARP (Address Resolution Protocol) frame is used for address resolution. The BIT (Built-In Test Frame) is used to report local message statistics and fault statistics to the remote end.

[0024] The first three types of data frames originate from the main processor's configuration, while the fourth type is generated by the network interface card (NIC). After encapsulation by the coprocessor, the data frame is sent to the transmission arbitration module, where it participates in arbitration along with the main processor's data, and is then sent to the link in sequence. Upon reception, the reception arbitration module identifies the data frame required by the coprocessor and forwards it to the coprocessor for processing.

[0025] 7) Functional domain configuration: such as Figure 2As can be seen, the network transmission process below the arbitration module is a shared structure for both the main processor and the coprocessor. Above the arbitration module, some functions are configurable. The main processor and coprocessor can configure their respective functional domains during the initialization phase by configuring the control registers. The main processor is configured by default for instruction and large data transfer functions, while the coprocessors are configured by default for time synchronization, network management, and status detection and transmission functions. These default configurations help each processor focus on its core business, thereby improving overall processing efficiency.

[0026] 8) Basic Function Domain Switching: such as Figure 2 As shown, the basis of functional domain switching lies in the network interface card (NIC) achieving logical isolation between hardware and software by encapsulating low-level protocol functions and offloading high-level protocols. The main processor and coprocessor each have independent queue buffers; when functional domain switching occurs, hardware processing logic is transferred to software processing. Normally, both the main and coprocessors operate according to their respective configured functional domains; switching is only activated as an emergency measure when a single processor fails. The main and coprocessors exchange status information through registers A and B, determining each other's operating status through status detection.

[0027] 9) Function Domain Switching Procedure: If a function domain needs to be switched during normal operation of the network system, the following steps must be followed: ① Shut down all functional modules: Ensure the system is in a safe state; ② Update the configuration table and reconfigure the functions: Adjust the configuration according to the requirements of the new functional domain; ③ Restart the system: Load the new configuration and restore functionality.

[0028] ④ Error handling: During disconnection and restart, detected error data frames should be discarded and included in the fault statistics to facilitate differentiation from other fault phenomena.

[0029] 10) Significance of Function Domain Switching: The function domain switching mechanism ensures that critical information can still be reported through another processor when one processor fails, providing emergency handling capabilities for the network system in case of failure. It should be noted that the system's transmission efficiency will decrease and processing power consumption will increase after switching; it should only be used as an emergency measure. After the flight mission is completed, the original function domain configuration should be restored as soon as possible, and the cause of the emergency switch should be identified to ensure long-term stable system operation.

[0030] Example This paper presents a dual-processor collaborative TSN network-side system architecture suitable for unified network application scenarios. In this scenario, network-side systems in electromechanical, flight control, and other fields uniformly adopt TSN networks. Existing avionics network-side system architectures suffer from the following problems: firstly, they place a heavy load on the main processor; secondly, they are incompatible with the design habits of application software in electromechanical and flight control systems; and thirdly, directly applying avionics network-side systems would result in low transmission efficiency and insufficient security, leading to numerous inconveniences for users. This architecture is simple in design, fully considers the application habits and practical limitations of electromechanical and flight control fields, solves the aforementioned core problems, and comprehensively considers security, making it the optimal solution for this application scenario.

[0031] 2. Determined dual-processor network-side system architecture design as follows Figure 1 As shown.

[0032] 3. Depending on the specific application requirements, some functions can be flexibly switched. The specific switching architecture is as follows: Figure 2 As shown.

[0033] The above description is merely a specific embodiment of the present invention, providing a detailed description of the invention. Parts not covered herein are conventional techniques. However, the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for designing a TSN network end-system architecture with dual processor collaboration, characterized in that: The system architecture includes a main processor and a network interface card; The network card has built-in buffer A, register A, buffer B, register B, coprocessor, and protocol conversion module; The main processor interacts with cache A and register A in the network card; The coprocessor interacts with buffer B and register B in the network interface card; The protocol conversion module interacts with buffer A, register A, buffer B, register B, and the external network. The main processor is used to receive airborne optical and radar signals, sensor signals, avionics / electromechanical control signals, and graphics and video signals, and output optical and radar sensor data, avionics / electromechanical control commands, and graphics and video signals. The coprocessor is used to receive avionics network management data, network time synchronization data, and internal self-test data, and output the corresponding data packets.

2. The method according to claim 1, characterized in that: The main processor stores the data to be transmitted into the transmit area of ​​register A and writes the control information into register A; The protocol conversion module encapsulates the data into protocol frames and sends them to the external network; When the network card receives an external data frame, it performs protocol offloading and stores the data in the receive area of ​​buffer A, while marking the reception completion status through register A; The main processor periodically checks the receive completion flag bit in register A. If the receive completion flag is detected to be set, data is read from the receive area of ​​register A.

3. The method according to claim 2, characterized in that: The coprocessor sends four types of data frames, namely: Time-Sensitive Management Protocol (TSMP) frames are used for time-sensitive protocol time synchronization. Network control and management protocol frames are used for Ethernet network management. Address resolution protocol frames and BIT transport frames; The content of the first three types of data frames comes from the main protocol configuration, while the content of the fourth type of data frames comes from the operation of the network card. After the coprocessor completes the data frame encapsulation, it sends it to the transmission arbitration module, where it is arbitrated together with the data sent by the main processor and then sent to the link in sequence. Upon receiving data, the receiving arbitration module identifies the data frame required by the coprocessor and passes the data frame to the coprocessor for processing.

4. The method according to claim 3, characterized in that: The main processor and the coprocessor exchange status information through registers A and B, and determine the working status of each other by checking the status information. The main processor periodically writes the characteristic value 32'h5A5AA5A5 into register A; when the coprocessor detects this characteristic value, it determines that the main processor is working normally and clears the characteristic value to zero. If abnormal feature values ​​are detected for three consecutive cycles, it is confirmed that the main processor has failed. Similarly, the coprocessor periodically writes the characteristic value 32'hA5A55A5A into register B; when the main processor detects this characteristic value, it determines that the coprocessor is working normally and clears it to zero. If abnormal feature values ​​are detected for three consecutive cycles, a coprocessor malfunction is confirmed. When the main processor fails, the coprocessor will receive additional interaction information between the main processor and the remote processor, and output a broadcast message indicating the node's failure status. When the coprocessor fails, the main processor will receive additional network management data and time synchronization data, and output network management response data and time synchronization correction data. After a coprocessor failure, the main processor additionally receives network management and time synchronization data, and outputs network management response data and time synchronization correction data.

5. The method according to claim 4, characterized in that: By configuring registers A and B, different functional domains can be configured for the main processor and coprocessor, enabling them to perform different functions. The normal configuration method is as follows: ① After power-on, the network card configures the functional domains of the main processor and coprocessor according to the default settings; ② If the application software on the main processor needs to change the functional domain during initialization, it should do so through the configuration register; ③ Turn on the main switch for the functional domain to enable all functions.

6. The method according to claim 5, characterized in that: ① Upon detecting a main processor failure, shut down all functional modules to ensure the system is in a safe state; ② Update the configuration table and reconfigure the functions, adjusting the configuration according to the requirements of the new functional domain; ③ Load the new configuration and restore functionality; ④ During disconnection and restart, detected erroneous data frames should be discarded and included in the fault statistics to distinguish them from other fault phenomena.

7. The method according to claim 6, characterized in that: ① Upon detecting a coprocessor failure, shut down all functional modules to ensure the system is in a safe state; ② Update the configuration table and reconfigure the functions, adjusting the configuration according to the requirements of the new functional domain; ③ Load the new configuration and restore functionality; ④ During disconnection and restart, detected erroneous data frames should be discarded and included in the fault statistics to distinguish them from other fault phenomena.

8. The method according to claim 7, characterized in that: The coprocessor connects to an external debugging cable via a serial port to report status information to an external debugging terminal; and connects to the MCU on the carrier board via the I²C bus to report and record status information via the MCU.

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