A high-precision modular event timing system

Abstract

The application belongs to the field of embedded system and real-time control technology, and is a high-precision modular event timing system based on microTCA.4 standard and Zynq SoC architecture, which is suitable for industrial control and other scenes with high requirements for time synchronization precision and system stability, adopts a Zynq SoC timing main logic AMC board card conforming to the microTCA.4 standard, uses a ZYNQ-7045 SOC industrial chip, has a heterogeneous firmware module based on the Zynq SoC, supports nanosecond-level event timing precision at the PL end, and realizes high-speed communication between the PS end and the PL end through an AXI bus, has a point-to-point signal real-time transmission and sharing mechanism based on mLVDS, has a standard backplane signal output board card and multiple high-speed photoelectric conversion terminal matching board cards, and fully gives play to the advantages of FPGA, realizes core functions, constructs a high-precision, flexible and expandable system, and improves the performance of the event timing system.

Description

Technical Field

[0001] This invention relates to embedded systems and real-time control technology in the field of next-generation information technology, specifically to a high-precision event timing system based on the microTCA.4 standard and Zynq SoC architecture. Background Technology

[0002] In modern industrial control, scientific research experiments, and large-scale infrastructure systems, precise time synchronization and reliable event timing mechanisms are core elements for ensuring stable system operation and achieving complex functions. For example, in the field of large particle accelerators, highly complex large-scale distributed systems like the China Spallation Neutron Source (CSNS) rely on high-precision trigger signals and strictly synchronized clock signals to achieve precise real-time control of the high-speed proton beam trajectory. Similarly, in scientific research facilities such as synchrotron radiation sources, precise event timing is also required to ensure the accuracy and repeatability of experiments. In industrial fields such as smart grids and rail transportation, numerous devices must also work collaboratively under strict time constraints to ensure the safe and efficient operation of the system.

[0003] Traditional event timing devices have many limitations. From a hardware architecture perspective, many traditional timing devices adopt a fixed architecture design, with hardware and software tightly coupled, lacking modularity and scalability. When facing different application scenarios, the entire system often needs to be redesigned, which not only leads to high development costs but also long development cycles. In terms of time synchronization accuracy, traditional devices also struggle to meet the ever-increasing demands. Especially in multi-node, long-distance distributed systems, time deviations are prone to accumulate, seriously affecting the overall system performance. Taking large particle accelerators as an example, the equipment distributed in different areas requires highly accurate time synchronization. Due to the limited accuracy of traditional timing devices, inaccurate proton beam control may occur, affecting experimental results.

[0004] With the rapid development of embedded and integrated circuit technologies, SoC (System on Chip) chips and modular hardware architectures have brought new ideas to the design of event timing systems. The MicroTCA.4 standard, as an open and modular embedded system standard, boasts advantages such as high density, high reliability, and scalability, and has been widely used in communications, aerospace, and other fields. It provides an ideal hardware platform for building complex distributed control systems, meeting the high hardware requirements of high-precision event timing systems. Xilinx Zynq SoC integrates a high-performance ARM processor and a programmable logic unit (FPGA), forming a heterogeneous computing architecture. This architecture fully leverages the advantages of hardware-software synergy, providing strong hardware support for the core control logic implementation of high-precision event timing functions. The ARM processor runs the operating system and complex algorithms, enabling system-level task scheduling, user interaction, and parameter configuration. Utilizing the parallel processing capabilities and high-precision timing control capabilities of the FPGA, key functions such as parsing event timing data frames and event triggering mechanisms are implemented, achieving nanosecond-level event triggering accuracy.

[0005] However, the high-precision event timing systems based on the MicroTCA.4 standard and Zynq SoC architecture on the market are still imperfect. Some existing systems have limited functionality and can only meet basic timing requirements. They lack the ability to adapt to complex application scenarios. In some scenarios that require multi-channel synchronous control and flexible configuration of each channel, existing systems cannot provide effective solutions. Some systems are also not flexible enough and are difficult to dynamically adjust and expand according to user needs, which limits their application in different fields.

[0006] Furthermore, for the transmission of mLVDS signals, traditional methods often employ bus-based communication, which is prone to signal conflicts and bandwidth bottlenecks, affecting the real-time performance and stability of signal transmission. In some applications with extremely high requirements for signal transmission quality, such as the control of large-scale scientific research experimental equipment, traditional communication methods cannot meet the needs. Summary of the Invention

[0007] To address the aforementioned issues, this invention aims to provide an event timing system with high precision, high flexibility, and high scalability, capable of flexibly adapting to various level interface scenarios, and optimized for mLVDS signal transmission. Based on the microTCA.4 standard and Zynq SoC architecture, this system can meet the needs of industrial control, scientific research experiments, and large-scale infrastructure systems with extremely high requirements for time synchronization accuracy and system stability.

[0008] The technical solution adopted in this invention is: a high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture, characterized in that it includes: a Zynq SoC timing main logic AMC board conforming to the microTCA.4 standard, using the Xilinx ZYNQ7000 Kintex device series ZYNQ-7045 SOC industrial-grade chip, with a dual-width design; based on Zynq... The SoC's heterogeneous firmware module includes a processing subsystem (PS side) and a programmable logic subsystem (PL side). The PL side implements event timing data frame parsing, event trigger control, interrupt response mechanisms, and timing signal output functions, supporting nanosecond-level event timing accuracy. The PS side runs event scheduling algorithms and a user interface, communicating with the PL side at high speed via the AXI bus, supporting multi-event concurrent scheduling, priority management, and remote control. A point-to-point signal real-time transmission and sharing mechanism based on mLVDS supports high-speed, low-latency, and high-reliability transmission of critical control signals. It includes backplane signal output boards compliant with the microTCA.4 standard and multiple high-speed optoelectronic conversion terminal matching boards. The backplane signal output boards integrate high-speed signal transmission channels, and the terminal matching boards use high-speed optoelectronic conversion technology to achieve real-time conversion and isolated transmission of electrical and optical signals, adapting to 3.3V, 5V, and 24V level interface standards and supporting modular expansion.

[0009] The main logic AMC board includes a circuit board, crystal oscillator, programmable logic chip, driver chip, buffer driver chip, connector, data bus, FPGA I / O interface, bus switch, data buffer and DIP switch; the firmware achieves nanosecond-level event timing accuracy and supports dynamic configuration of timing parameters to adapt to different application scenarios.

[0010] The Zynq SoC's PL terminal achieves nanosecond-level event timing accuracy through the FPGA's internal high-speed clock domain and counter structure, supporting precise setting of event trigger time and dynamic parameter configuration; users can adjust the trigger time, timing period, event priority, and delay compensation value according to the application scenario.

[0011] The Zynq SoC's PS terminal communicates with the PL terminal at high speed via the AXI bus, supporting multi-event concurrent scheduling, priority management, and remote control. Key configuration parameters can be modified online through the PS terminal control software and sent to the PL terminal in real time via the AXI bus, enabling dynamic strategy adjustments without restarting the system during operation.

[0012] Each mLVDS signal has an independent input interface, output interface, and enable control interface, which are directly connected to the physical I / O pins of the FPGA, enabling independent control and flexible configuration of each signal, thus improving the system's flexibility and maintainability.

[0013] The RTM board includes: conforming to the mTCA backplane board size and architecture specifications to achieve efficient data signal conversion and transmission; extracting 8 channels of 1.8V LVDS level differential signals from the AMC board, converting them into single-ended signals, and then boosting them to the 3.3V TTL standard through a level conversion chip to generate 8 trigger signals; a signal drive and optical output module, which drives the HFBR-1414T optical module to emit optical signals through an AND gate logic chip; and an external optical signal receiving and processing module, which converts the optical signals into electrical signals through the HFBR-2412T optical receiving module, converts them into 3.3V TTL level through a current converter, and then transmits them to the front panel for fast interlocking mechanism and trigger signal stop control.

[0014] The FMC board includes: conforming to the VITA 57.1 standard HP-type FMC interface specification, supporting standardized and modular design; extracting 12 channels of 1.8V LVDS level differential signals from the template board, converting them into single-ended signals, and then boosting them to the 3.3V TTL standard through a level conversion chip to generate 12 trigger signals; among them, 4 signals are used as inputs to the DS1023-100 programmable delay chip, outputting 4 channels of 100 picosecond precision timing control signals; supporting the reception of 2 external timing signals to enhance time synchronization capability and external control flexibility; and featuring compatibility and scalability design, supporting compatibility with mainstream communication architectures such as mTCA and ATCA, and achieving higher precision signal processing by replacing or upgrading the delay chip.

[0015] The terminal matching board includes: an Altera EPM240T100C5N CPLD as the core controller, responsible for signal analysis and routing, supporting 3.3V and 5V I / O voltage compatibility; an HFBR-2412T optoelectronic receiver module, supporting 650nm wavelength plastic optical fiber communication with a maximum transmission rate of 10Mbps; two HFBR-1414T optoelectronic transmitter modules to achieve secondary optical signal fan-out output; a level conversion circuit supporting 1.2V~5.5V voltage conversion, with the output level flexibly configured as 3.3V TTL or 5V TTL via a jumper selector; and a 24V relay drive circuit, configured with a ULN2003 Darlington transistor array chip, to drive an external 24V relay or actuator.

[0016] The terminal matching board's functions include: optical signal input processing: the optical signal from the originating device is received by the HFBR-2412T and converted into a TTL level signal, which is then sent to the CPLD for processing and routing. A 3.3V or 5V TTL signal is output through the level conversion module; the CPLD controls two HFBR-1414T modules to achieve secondary optical signal fan-out; 24V electrical signal output control: the CPLD outputs a control signal, which, after being driven by the ULN2003, controls the on / off state of the external 24V power supply, triggering mechanical equipment; configuration and debugging interface: a JTAG programming interface is provided, supporting online programming and debugging of the CPLD; configuration information is stored in an external EEPROM, enabling automatic loading after power failure; onboard LED indicators display the optical signal status, power status, and output channel operating status in real time.

[0017] The terminal Fanout board's functions include: optical signal input processing: the optical signal from the originating device is received by the HFBR-2412T and converted into a TTL level signal, which is then sent to the CPLD for processing and routing. A 3.3V or 5V TTL signal is output through the level conversion module. After receiving one input signal, the CPLD independently fans out 12 signals, which are connected to 12 MC100EP138 ultra-high-speed programmable delay chips. Each signal is independently adjusted for phase and delay. By configuring the delay parameters of the MC100EP138 chip, high phase consistency of the 12 timing signal outputs is achieved, improving the synchronous triggering accuracy of multi-channel devices.

[0018] The high-precision event timing system based on the microTCA.4 standard and Zynq SoC architecture of the present invention has the following significant advantages:

[0019] High-precision timing: By leveraging the parallel processing capabilities and high-precision timing control capabilities of the FPGA on the PL side of the Zynq SoC, combined with a high-speed clock domain and counter structure, nanosecond-level event triggering accuracy is achieved, which can meet the application scenarios with extremely high time synchronization requirements, such as beam control of large particle accelerators and precise triggering of synchrotron radiation sources.

[0020] Modular Design: The system hardware platform is built on the microTCA.4 standard and adopts a modular design concept, including a variety of functional boards such as the main control board, rear adapter board (RTM), FMC carrier board, terminal photoelectric conversion board, and terminal signal fan-out board. This modular design enables the system to have high density, high reliability, and scalability. Users can flexibly select and combine different boards according to actual needs to quickly build an event timing system that meets specific application scenarios, reducing system development and maintenance costs.

[0021] Hardware-Software Synergy Advantages: The core control logic for event timing functionality, implemented on a Xilinx Zynq SoC, fully leverages the hardware-software synergy advantages of the ARM processor (PS side) and the programmable logic unit (PL side). The PS side runs the embedded operating system and event scheduling algorithm, responsible for system-level task scheduling, user interaction, and parameter configuration. The PL side implements key functional modules such as parsing event timing data frames, event triggering mechanisms, interrupt controller design, and timing signal output. The two communicate efficiently through the AXI high-speed bus interface, ensuring the system's real-time response capability and programmability, simultaneously meeting the requirements of high precision, programmability, and high reliability.

[0022] Flexible mLVDS Signal Interface: A fully configurable signal interface logic architecture was designed and implemented to meet the transmission requirements of mLVDS signals. Each mLVDS signal has an independent interface design, including input, output, and enable control interfaces. All interfaces are directly connected to the FPGA's physical I / O pins, enabling independent control and flexible configuration of each mLVDS signal. Each mLVDS channel can be independently configured as input, output, or bidirectional, avoiding signal conflicts and bandwidth bottlenecks that may occur in traditional bus-based communication. This improves the real-time performance and stability of signal transmission and enhances the system's adaptability and scalability in different application scenarios.

[0023] Multi-level compatibility: The system integrates multiple boards adapted to different voltage levels for various application scenarios, such as terminal matching boards supporting 5V, 3.3V, and 24V for typical industrial and scientific research applications. This can meet the diverse needs of different control systems for voltage level matching, signal driving capability, and electrical isolation. The terminal matching board has good scalability and modular design features, and the number of photoelectric conversion channels and interface types can be flexibly configured according to actual application scenarios, further enhancing the system's versatility and adaptability.

[0024] Complete system solution: This invention also integrates external interface modules (such as GPIO, SPI, UART, CAN, Ethernet, etc.), a system clock module (supporting external time synchronization, such as GPS second pulse, PTP protocol, etc.), and a power and reset management module, constructing a complete event timing system solution; users do not need to configure multiple independent devices to achieve high-precision timing, remote management, multi-task scheduling and other functions of the system, simplifying the system architecture and improving the system integration and reliability;

[0025] Promising engineering applications: This invention is particularly suitable for scientific research and industrial fields with extremely high requirements for time synchronization accuracy and system stability, such as large particle accelerators and synchrotron radiation sources. In practical applications, this invention has been successfully applied to large-scale scientific facilities such as the China Spallation Neutron Source Phase II (CSNS-II) accelerator, verifying its reliability and effectiveness in practical engineering, and has promising engineering application prospects and promotion value. Attached Figure Description

[0026] Figure 1 This is a physical image of the event timing AMC board used in this invention;

[0027] Figure 2 This is a schematic diagram of the event timing software hierarchy design based on the Zynq SoC architecture of this invention;

[0028] Figure 3 This is a physical image of a domestically produced 2U chassis based on the MicroTCA.4 standard.

[0029] Figure 4 This is a physical image of the event timing RTM board in this invention;

[0030] Figure 5 This is a physical image of the event timing AMC board equipped with an RTM board in this invention;

[0031] Figure 6 This is a physical image of the event timing FMC board in this invention;

[0032] Figure 7 This is a physical image of the event timing AMC board equipped with the FMC board in this invention;

[0033] Figure 8 This is a physical image of the event timing OE-EO board used in this invention;

[0034] Figure 9 This is a physical image of the event timing Fanout board in this invention;

[0035] Figure 10 This is a schematic diagram of the event timing architecture in this invention. Figure 1 (Shares the same MicroTCA.4 standard chassis as the device controller);

[0036] Figure 11 This is a schematic diagram of the event timing architecture in this invention. Figure 2 (Does not share the same MicroTCA.4 standard chassis as the device controller);

[0037] Figure 12 In this invention, the event timing and the device controller share the same MicroTCA.4 standard chassis debugging environment;

[0038] Figure 13 This is a burn-in test of the event timing signal in this invention;

[0039] Figure 14 The event timing signal in this invention enables onboard IOC pulse width setting operation;

[0040] Figure 15 To enable 10ns pulse width step size adjustment for the event timing signal in this invention;

[0041] Figure 16 To enable 500ns pulse width step size adjustment for the event timing signal in this invention;

[0042] Figure 17 This refers to the output delay of each channel before adjusting the output signal of the event timing signal Fanout board in this invention;

[0043] Figure 18 This refers to the output delay of each channel after adjusting the output signal of the event timing signal Fanout board in this invention;

[0044] Figure 19 The event timing signal Fanout board output signal was subjected to a stress test (pk-pk=1.5 ns) for stress testing.

[0045] Figure 20 This is a physical image of the event timing device of the present invention operating online at the CSNS-II accelerator;

[0046] Figure 21 The signal stress test (pk-pk=700 ps) was conducted to test the interaction between the event timing device and the RCS LLRF control board in this invention via the chassis mLVDS.

[0047] Figure 22 This is a schematic diagram of the normal operation timing of the dual-phase beam-cutting power supply generated by the event timing device in this invention. It includes two timing signals for the phase-shifting mode, providing a 650µs, 50Hz macro pulse. The phase-shifting time t is adjustable; for convenience, t is selected as 137ns, 275ns, and 494ns. The micro-pulse width is 549ns (to meet the requirement of an output high-voltage pulse frequency of 1.82MHz), and the micro-pulse frequency is 0.91MHz.

[0048] Figure 23 Debugging the normal operation timing of the dual-phase beam-cutting power supply generated by the event timing device in this invention;

[0049] Figure 24This is a schematic diagram of the timing of the dual-phase beam-cutting power supply generated by the event timing device in this invention. A 40ms pulse is missed within 1 second and replaced with an envelope of 50-800us. Two timing signals provide a 40ms pulse width, with a 12.5Hz macro pulse containing an envelope signal within 1 second. The phase misalignment time t is adjustable, typically 50-800us, but 800us is chosen here. The micro-pulse timing structure is as in the first beam-cutting mode (normal beam-cutting mode). In other words, this beam-cutting mode involves two phase misalignment issues: one for the macro pulse and one for the micro pulse.

[0050] Figure 25 Macro-pulse phase misalignment timing debugging for the dual-phase beam-cutting power supply machine generated by the event timing device in this invention;

[0051] Figure 26 This study focuses on the micropulse phase misalignment timing debugging of the dual-phase beam-cutting power supply generated by the event timing device in this invention. Detailed Implementation

[0052] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings:

[0053] like Figure 1-26 ,like Figure 1 As shown, the core of the event timing device of a high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture is the Advanced Mezzanine Card (AMC) board based on the MicroTCA.4 standard. The AMC board uses the Xilinx Zynq-7000 series SoC as the main control chip, integrating a dual-core ARM Cortex-A9 processor (PS side) and programmable logic (PL side) to achieve hardware and software co-processing. The AMC board strictly follows the MicroTCA.4 mechanical, electrical and thermal design specifications, and supports hot-swapping, redundant power supply and high-precision clock / synchronization signal transmission on the backplane.

[0054] Figure 2 This invention demonstrates the software-layer design of the Zynq SoC architecture; the PS runs the PetaLinux operating system, providing device drivers, network communication (supporting the PTPv2 protocol), IPMI management, and upper-layer application interfaces; the PL constructs hardware logic through VivadoHLS and IP Integrator, including a high-precision timestamp capture unit, a programmable timing signal generator, and an internal AXI bus interconnect structure within the FPGA; high-speed data and control command interaction is achieved between the PS and PL through the AXI4-Stream and AXI4-Lite buses.

[0055] like Figure 3 As shown, the AMC board is installed in a domestically produced 2U MicroTCA.4 standard chassis. This chassis provides a standard-compliant power supply, cooling system, clock backplane (distributing a 10 MHz reference clock and PPS signal), and mLVDS management bus, ensuring high system-level reliability and time synchronization performance. To expand interface functionality, this invention designs various sub-boards; such as... Figure 4 As shown, the RTM (RearTransition Module) board is connected via the AMC rear cabling interface, providing additional LVDS, PECL, and fiber optic I / O channels; Figure 5 This is a physical diagram of the combination of AMC board and RTM board, forming a complete signal input / output front end.

[0056] like Figure 6 As shown, the FMC (FPGA Mezzanine Card) board connects to the AMC board via the FMC-LPC interface for rapid prototyping and interface expansion; Figure 7 The physical connection status of the AMC board equipped with FMC was demonstrated; Figure 8 The OE-EO (optical-electrical / electrical-optical) board shown realizes the mutual conversion between electrical signals and optical signals, and supports long-distance, interference-resistant timing signal transmission; Figure 9 The Fanout board shown is used to fan out a single high-precision timing signal into multiple channels for simultaneous use by multiple downstream devices. Figure 10 and Figure 11 These are schematic diagrams of two system architectures of the present invention; wherein Figure 10 In this system, the event timing AMC board and the device controller (such as LLRF, power controller, etc.) are deployed in the same MicroTCA.4 chassis, and low-latency, high-reliability communication is achieved through backplane mLVDS or Ethernet; Figure 11 In this system, the event timing device and the equipment controller are located in different chassis, and cross-chassis time synchronization is achieved through a fiber optic network (supporting PTPv2); Figure 12 The demonstration showcased a debugging environment where the event timing device and the device controller share the same chassis, facilitating system integration and functional verification. Figure 13 The stress test results of the event timing signal verify the stability of the system during long-term operation; Figures 14 to 16 It demonstrates the precise adjustability of the timing signal; through the programmable delay unit at the PL end, users can finely adjust the pulse width of the output signal in the software interface; Figure 14 The operation interface for setting the pulse width of the onboard IOC (Input / OutputController); Figure 15 The pulse width is adjusted in 10 ns increments. Figure 16 The display adjusts in 500 ns increments, demonstrating the device's flexibility and high resolution.

[0057] Figure 17 and Figure 18 The output delay of the Fanout board before and after adjustment was compared. Before adjustment, each channel had a deviation of approximately several nanoseconds. After using the MC100EP138 chip to independently compensate for the delay of each signal, the consistency of the output delay of each channel was significantly improved, and the peak-to-peak jitter (pk-pk) was controlled within 1.5 ns (e.g., Figure 19 As shown in the figure, it meets the requirements for high-precision synchronization; Figure 20 The image shows a physical picture of the device of the present invention operating online on the CSNS-II (China Spallation Neutron Source Phase II) accelerator, indicating that it has been successfully applied to large-scale scientific facilities. Figure 21 The signal test results for the interaction between the event timing device and the RCS (Rapid Cyclic Synchronous Accelerator) LLRF control board via the chassis mLVDS bus show that the peak-to-peak signal jitter is only 700 ps, ​​verifying the excellent performance of high-speed signal transmission on the backplane. Figure 22 and Figure 23 This invention demonstrates a key application in dual-phase beam-splitting power supply driving; the device generates two macropulse timing signals with a width of 650 μs and a repetition frequency of 50 Hz, operating in "phase-out mode," with an adjustable phase-out time t, typically set to 137 ns, 275 ns, or 494 ns; the micropulse width is 549 ns, and the micropulse frequency is 0.91 MHz, ensuring an output high-voltage pulse frequency of 1.82 MHz; this timing has been verified through actual debugging. Figure 23 It can stably drive bipolar power supplies to achieve precise beam cutting and control.

[0058] As shown in Figure 19, an event timing system based on the microTCA.4 standard and Zynq SoC architecture includes:

[0059] A Zynq SoC timing main logic AMC board conforming to the microTCA.4 standard, using the Xilinx ZYNQ7000Kintex device series ZYNQ-7045 SOC industrial-grade chip, the board conforms to the microTCA.4 standard and has a dual-width size;

[0060] The event timing firmware module based on Zynq SoC includes a processing subsystem (PS side) and a programmable logic subsystem (PL side). The PL side of the Zynq SoC is responsible for parsing event timing data frames, event trigger control, interrupt response mechanism, and timing signal output functions. The PS side runs the event scheduling algorithm and user interface, and communicates with the PL side at high speed through the AXI bus, supporting multi-event concurrent scheduling, priority management, and remote control functions.

[0061] Implement a point-to-point real-time signal transmission and sharing mechanism based on mLVDS among multiple control boards, supporting high-speed, low-latency, and high-reliability real-time transmission and sharing of critical control signals;

[0062] The system employs a backplane signal output board based on the microTCA.4 standard and multiple terminal matching boards based on high-speed photoelectric conversion technology to achieve broad adaptability to various interface levels. The backplane signal output board conforms to the microTCA.4 standard, integrating a high-speed signal transmission channel to support stable transmission of critical control and status signals between various functional modules within the system. The terminal matching boards utilize high-speed photoelectric conversion technology to achieve real-time conversion and isolated transmission between electrical and optical signals, effectively improving the system's anti-interference capability and communication reliability. This board design supports multiple interface standards, adapting to typical industrial and scientific research applications such as 3.3V, 5V, and 24V, meeting the diverse needs of different control systems for level matching, signal driving capability, and electrical isolation. Furthermore, the terminal matching board features excellent scalability and modular design, allowing for flexible configuration of the number of photoelectric conversion channels and interface types according to actual application scenarios, further enhancing the system's versatility and adaptability.

[0063] The main logic AMC board, also known as the timing main logic control board, includes a circuit board, crystal oscillator, programmable logic chip, driver chip, buffer driver chip, connector, data bus, FPGA I / O interface, bus switch, data buffer, DIP switch, etc. Its firmware achieves nanosecond-level event timing accuracy and supports dynamic configuration of various timing parameters to adapt to the needs of different application scenarios.

[0064] The core logic of the event timing function in this invention is implemented by the programmable logic (PL) terminal in the Zynq SoC. Through the high-speed clock domain and counter structure and high-precision timing mechanism inside the FPGA, the hardware logic design based on the FPGA can achieve nanosecond-level event timing accuracy, support the precise setting of event trigger time, and have dynamic parameter configuration capabilities. Users can flexibly adjust timing parameters such as trigger time point, timing period, event priority, delay compensation value, etc. according to the actual needs of different application scenarios.

[0065] The Zynq SoC's PS terminal runs an event scheduling algorithm and user interface, and communicates with the PL terminal at high speed via the AXI bus. It supports multi-event concurrent scheduling, priority management, and remote control functions. Key configuration parameters can be modified online through the control software running on the PS terminal and sent to the PL terminal in real time via the AXI high-speed bus, ensuring that the system can adapt to new control strategies or changes in the external environment without restarting during operation.

[0066] In this invention, each mLVDS signal has an independent input interface, output interface, and enable control interface, which are directly connected to the physical I / O pins of the FPGA. This enables independent control and flexible configuration of each mLVDS signal, ensuring high efficiency and reliability of signal transmission and greatly improving the system's flexibility and maintainability.

[0067] The main features and functional designs of the RTM board include:

[0068] (1) The design of the RTM (Rear Transition Module) board strictly follows the standard mTCA back-transition board size and architecture specifications, aiming to achieve efficient data signal conversion and transmission, and is particularly suitable for application scenarios that require high stability and high speed;

[0069] (2) The RTM board extracts 8 differential signals using the 1.8V LVDS level standard from the AMC (Advanced Mezzanine Card) board and converts them into single-ended signals; these signals are then boosted to the 3.3V TTL standard by an 8-bit, 1.8V to 3.3V level conversion chip to generate 8 trigger signals;

[0070] (3) Signal driving and optical output: The trigger signal after level conversion drives the HFBR-1414T current-driven optical module to emit optical signals under the joint action of three AND gate logic chips; this process ensures the accuracy and stability of the signal and is suitable for data transmission in long distances or complex environments;

[0071] (4) External optical signal reception and processing: The RTM board is also equipped with the function of receiving external optical signals. The input optical signal is converted into an electrical signal using the HFBR-2412T optical receiver module. The received electrical signal is converted back into 3.3V TTL level through the current converter and transmitted to the 3.3V Bank IO on the front panel through the Zone 3 connector. It is mainly used for fast interlocking mechanism and stop control of trigger signal to ensure the safe and stable operation of the system.

[0072] The main features and functional designs of the FMC board described in this invention include:

[0073] (1) The design of the FMC (FPGA Mezzanine Card) board strictly follows the size and architecture specifications of the high-performance HP (High Pin Count) type FMC interface, has good standardization and modular design characteristics, can be widely used in FPGA carrier card platforms that conform to the VITA57.1 standard, and has good versatility and portability;

[0074] (2) The FMC board extracts 12 differential signals of 1.8V LVDS level standard from the template board and converts them into single-ended signals for subsequent processing. These signals are then boosted to 3.3V TTL standard by an 8-bit, 1.8V to 3.3V level conversion chip to generate 12 trigger signals. Among them, 4 signals are used as independent input signals for 4 DS1023-100 programmable delay chips, and the remaining 8 are used as shared data signals input to these chips. Each DS1023-100 chip can output one adjustable timing signal with a delay accuracy of 100 picoseconds, and outputs a total of 4 high-precision timing control signals for the AMC timing board to use for logic signal output and time synchronization.

[0075] (3) The FMC board also supports receiving two external timing signals, which can be used to introduce external clock or control signals, enhancing the system's time synchronization capability and external control flexibility.

[0076] (4) The FMC board can be used not only as a signal processing module, but also as a terminal board. It can realize point-to-point signal transmission and resource sharing between boards in the same chassis, effectively making up for the application limitations of mLVDS (miniature low voltage differential signal) in some high-precision and low-latency scenarios.

[0077] (5) Compatibility and scalability: The FMC board strictly follows the VITA 57.1 standard and supports physical compatibility with standard FMC slots. It can be easily inserted into carrier cards that support HP-type FMC interfaces. It supports interoperability between 1.8V LVDS and 3.3V TTL level standards. Through flexible signal routing and level conversion mechanisms, it ensures error-free signal interaction with various main control boards (such as AMC and FPGA carrier boards). It is compatible with mainstream communication architectures such as mTCA (MicroTCA) and ATCA (AdvancedTCA). In the future, higher precision or more channels of signal processing can be achieved by replacing or upgrading delay chips or logic chips.

[0078] The main features of the terminal matching board described in this invention include:

[0079] (1) The Altera EPM240T100C5N CPLD (Complex Programmable Logic Device) is used as the core controller to receive, parse and route signals from the optical module, and control the level selection and trigger logic of the output channel. The main control chip belongs to the Altera MAX II series, has 240 logic units (LE), 100-pin package, supports 3.3V and 5V I / O voltage compatibility, and has low power consumption, high stability and reprogrammable characteristics, realizing efficient conversion and flexible routing between optical signals and electrical signals.

[0080] (2) The HFBR-2412T optoelectronic receiver module is used, which supports 650nm wavelength plastic optical fiber communication, with a maximum transmission rate of 10Mbps and good anti-electromagnetic interference capability; after the optical signal is received by the module, it is converted into a TTL level signal and sent to the CPLD for processing.

[0081] (3) Signal transmission module: Equipped with two HFBR-1414T optoelectronic transmission modules, supporting 650nm wavelength output and a maximum transmission rate of 10Mbps, used to realize the fan-out output of secondary optical signals, and can connect multiple slave devices to expand the system's communication capabilities;

[0082] (4) Level conversion circuit: adopts bidirectional level conversion chips such as TXB0108 or LVC1G125, supports 1.2V~5.5V voltage conversion, and ensures signal compatibility between 1.8V, 3.3V and 5V; through jumper selector, users can flexibly configure the output level to 3.3V TTL or 5V TTL at the hardware level to meet the level requirements of different device interfaces; (5) 24V relay drive circuit: configured with dedicated ULN2003 Darlington transistor array chip, used to drive external 24V relays or actuators; this circuit has overvoltage protection and reverse electromotive force absorption capability, and can directly control mechanical equipment in the industrial field (such as cylinders, solenoid valves, indicator lights, etc.).

[0083] The functional implementation and signal flow of the terminal matching board include:

[0084] (1) Optical signal input processing flow: The optical signal sent by the starting device is received by HFBR-2412T and converted into a TTL level signal; the signal is sent to CPLD for logic processing and routing; CPLD can select the output channel according to the configuration and output a 3.3V or 5V TTL signal through the level conversion module; at the same time, CPLD controls two HFBR-1414T modules to copy and forward the original optical signal to realize the fan-out of the secondary optical signal;

[0085] (2) 24V electrical signal output control: The CPLD outputs a control signal, which, after being driven by ULN2003, controls the on / off state of the external 24V power supply; this output can be directly used to trigger mechanical equipment, such as pneumatic devices, hydraulic systems, etc., with fast response speed and reliable control;

[0086] (3) Configuration and debugging interface: Provides JTAG programming interface to support online programming and debugging of CPLD; configuration information can be stored in external EEPROM and automatically loaded after power failure;

[0087] (4) Onboard LED indicator lights are used to display the optical signal status, power status and output channel working status in real time, which facilitates on-site debugging and troubleshooting.

[0088] The functional implementation and signal flow of the terminal Fanout board include:

[0089] (1) Optical signal input processing flow: The optical signal sent by the starting device is received by HFBR-2412T and converted into a TTL level signal; the signal is sent to the CPLD for logic processing and routing; the CPLD can select the output channel according to the configuration and output a 3.3V or 5V TTL signal through the level conversion module;

[0090] (2) The CPLD receives one input signal, and after internal logic processing, it independently fans out 12 signals through its I / O port. These 12 signals are further connected to 12 MC100EP138 ultra-high-speed programmable delay chips. Each signal can be independently adjusted in phase and delay. By configuring the delay parameters of the MC100EP138 chip, precise phase alignment between the output signals can be achieved, ensuring that the 12 timing signals maintain a high degree of phase consistency when output. This function effectively improves the accuracy of synchronous triggering of multi-channel devices and ensures the time consistency and reliability of the system in the process of data acquisition and control.

[0091] Example: Deploying the event timing system of the present invention in the China Spallation Neutron Source Phase II (CSNS-II) accelerator, a large-scale scientific facility.

[0092] like Figure 1-26 As shown, a high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture is deployed in the China Spallation Neutron Source Phase II accelerator (CSNS-II), a large-scale scientific facility. The specific implementation method is described in detail below:

[0093] S1, Hardware Setup

[0094] (a) Chassis and main control board installation

[0095] This embodiment uses a domestically produced 2U chassis that conforms to the MicroTCA.4 standard (as shown in Figure 3). This chassis has a standard-compliant power module that can provide a stable and reliable power supply for the entire system; the cooling system can effectively dissipate the heat generated during system operation, ensuring that the hardware operates in a suitable temperature environment; the clock backplane can distribute a 10MHz reference clock and PPS signal to provide the system with an accurate time base; and the mLVDS management bus ensures the stability and reliability of signal transmission within the system.

[0096] The timing main logic AMC board (as shown in Figure 1), which conforms to the microTCA.4 standard and uses the Xilinx ZYNQ-7045 SOC industrial-grade chip from the ZYNQ7000 Kintex device series, is inserted into the 2U chassis. The AMC board strictly adheres to the MicroTCA.4 mechanical, electrical, and thermal design specifications, supports hot-swapping, and facilitates board replacement and maintenance during system operation. The redundant power supply design further improves the system's reliability, ensuring that the system can still operate normally even if a single power supply fails. The high-precision clock / synchronization signal transmission interface on the backplane can be easily connected to the chassis's clock backplane to obtain accurate clock signals.

[0097] (ii) Expansion board connection

[0098] RTM Board Connection: In this embodiment, based on actual needs, the RTM (Rear Transition Module) board (as shown in Figure 4) is connected to the AMC board via the AMC back-wiring interface to form a complete signal input / output front end (as shown in Figure 5). The RTM board strictly adheres to the standard mTCA back-interface board size and architecture specifications, possessing efficient data signal conversion and transmission capabilities. It extracts eight differential signals using the 1.8V LVDS level standard from the AMC board, converts them into single-ended signals through an internal level conversion chip, and boosts the signal level to the 3.3V TTL standard, generating eight trigger signals. These trigger signals, driven by an AND gate logic chip, can control the HFBR-1414T current-driven optical module to emit optical signals, achieving long-distance, stable data transmission. Simultaneously, the RTM board also has the function of receiving external optical signals, using the HFBR-2412T optical receiver module to convert the optical signal into an electrical signal, and then converting it to 3.3V TTL through a current converter. The voltage level is transmitted to the 3.3V Bank IO on the front panel for fast interlocking mechanisms and stop control of trigger signals, ensuring the safe and stable operation of the system.

[0099] FMC Board Connection: In this embodiment, the FMC (FPGA Mezzanine Card) board (as shown in Figure 6) is connected to the AMC board (as shown in Figure 7) via the FMC-LPC interface for rapid prototyping and interface expansion. The FMC board strictly adheres to the size and architecture specifications of the high-performance HP (High Pin Count) type FMC interface, possessing excellent standardization and modular design characteristics, and can be widely used in FPGA carrier card platforms compliant with the VITA 57.1 standard. It extracts 12 differential signals of 1.8V LVDS level standard from the template board, converts them into single-ended signals, and then boosts the signal level to the 3.3V TTL standard through a level conversion chip, generating 12 trigger signals. Among them, 4 signals serve as independent input signals for 4 DS1023-100 programmable delay chips, and the remaining 8 signals are input to these chips as shared data signals. Each DS1023-100 chip can output one adjustable timing signal with a delay accuracy of 100 picoseconds, for a total output of 4... The FMC board provides a high-precision timing control signal for logic signal output and time synchronization to the AMC timing board. In addition, the FMC board also supports receiving two external timing signals, enhancing the system's time synchronization capability and external control flexibility.

[0100] OE-EO board connection: In this embodiment, the OE-EO (optical-electrical / electrical-optical) board (as shown in Figure 8) is connected to the system to realize the mutual conversion between electrical signals and optical signals; the board supports long-distance, interference-resistant timing signal transmission, and can effectively ensure the quality and stability of the signal when the timing signal needs to be transmitted over a long distance or in an environment with strong electromagnetic interference.

[0101] Fanout Board Connection: In this embodiment, according to system requirements, the Fanout board (as shown in Figure 9) is connected to the system to fan out a single high-precision timing signal into multiple channels for synchronous use by multiple downstream devices. After receiving a single input signal, the Fanout board processes it internally and independently fans it out into multiple signals through its I / O ports. These signals can be connected to an ultra-high-speed programmable delay chip to independently adjust the phase and delay of each signal, ensuring precise phase alignment between the output signals and meeting the accuracy requirements for synchronous triggering of multi-channel devices.

[0102] S2, Software Configuration

[0103] (I) Operating System Installation and Configuration

[0104] In this embodiment, the PetaLinux operating system is installed on the Zynq SoC. This operating system is an embedded Linux system that can provide a stable operating environment for the system and supports a wide range of device drivers and application development.

[0105] Configure network communication to support the PTPv2 protocol. PTPv2 (Precision Time Protocol version 2) is a high-precision time synchronization protocol that enables devices in the system to achieve time synchronization at the microsecond or even nanosecond level, meeting the stringent time synchronization requirements of high-precision event timing systems.

[0106] (II) Hardware Logic Design of PL Terminal

[0107] In this embodiment, Vivado HLS and IP Integrator tools are used for the hardware logic design of the PL side; a high-precision timestamp capture unit is designed to accurately capture the time information of event occurrence, providing an accurate time reference for event timing.

[0108] In this embodiment, a programmable timing signal generator is constructed. Through the high-speed clock domain and counter structure and high-precision timing mechanism inside the FPGA, nanosecond-level event triggering accuracy is achieved. Users can flexibly set parameters such as event triggering time and timing period according to actual needs.

[0109] In this embodiment, an interrupt controller is designed to effectively manage and process various interrupt events during system operation, ensuring that the system can respond to external events in a timely manner and guaranteeing the real-time performance and reliability of the system.

[0110] In this embodiment, an internal AXI bus interconnection structure is built within the FPGA to achieve high-speed data transmission and communication between various functional modules within the PL terminal and between the PL terminal and the PS terminal. Through the AXI4-Stream and AXI4-Lite buses, the PS terminal can send control commands to the PL terminal, and the PL terminal can also feed back status information and data to the PS terminal, realizing collaborative work between hardware and software.

[0111] (III) PS-side software design

[0112] In this embodiment, an event scheduling algorithm and a user interface program are run on the PS terminal. The event scheduling algorithm schedules multiple events reasonably according to the task priorities and time requirements set by the user, ensuring that the system can efficiently handle various tasks.

[0113] Develop a user interface program to provide users with a user-friendly interface, making it convenient for users to perform operations such as parameter configuration, task scheduling, and status monitoring of the system. Users can use this interface to understand the system's operating status in real time and make dynamic adjustments to the system according to actual needs.

[0114] In this embodiment, the PS terminal communicates with the PL terminal at high speed via the AXI bus to achieve multi-event concurrent scheduling, priority management, and remote control functions. Key configuration parameters can be modified online through the control software running on the PS terminal and sent to the PL terminal in real time via the AXI high-speed bus, ensuring that the system can adapt to new control strategies or changes in the external environment without restarting during operation.

[0115] S3, System Integration and Debugging

[0116] Based on actual application requirements, the event timing device and the device controller are selected to be deployed in the same chassis (e.g., Figure 10 As shown in Figure 11, low-latency, high-reliability communication can be achieved through backplane mLVDS or Ethernet; or the event timing device and the device controller can be located in different chassis (as shown in Figure 11), and cross-chassis time synchronization can be achieved through fiber optic network (supporting PTPv2).

[0117] If the system needs to synchronize with other devices, a communication link is established using the backplane mLVDS or Ethernet interface to ensure that the time synchronization accuracy between devices meets the system requirements.

[0118] S4, Functional Verification

[0119] Perform a signal stress test (as shown in Figure 13) to allow the system to continuously output a timed signal during long-term operation, verifying the system's stability and reliability; by monitoring various signal parameters, such as frequency, duty cycle, and jitter, ensure that the signal quality meets the design requirements.

[0120] The output signal pulse width was adjusted and tested, and fine-tuned through the software interface, starting from 10ns steps ( Figure 15 The step size ranges from 500 ns to 500 ns (Figure 16), verifying the system's flexibility and accuracy in adjusting the signal pulse width.

[0121] Adjust the output delay of each channel on the Fanout board to keep the peak-to-peak jitter within the ideal range (Figures 17 to 19); ensure the synchronization accuracy of multi-channel signal output by precisely adjusting the delay parameters of each channel to meet the system's requirements for synchronous triggering of multi-channel devices.

[0122] In this embodiment, the event timing device of the present invention is deployed in the China Spallation Neutron Source Phase II (CSNS-II) accelerator, a large-scale scientific facility (Figure 20). When applied to the dual-phase beam-cutting power supply drive, it is set according to the time sequence shown in Figures 22 and 23. The device generates two macropulse timing signals with a width of 650 μs and a repetition frequency of 50 Hz, operating in "phase-out mode". The phase-out time t is adjustable, with typical values ​​set to 137 ns, 275 ns, or 494 ns. The micropulse width is 549 ns and the micropulse frequency is 0.91 MHz, ensuring that the output high-voltage pulse frequency is 1.82 MHz. This timing sequence has been verified through actual debugging (Figure 23) and can stably drive the bipolar power supply, achieving precise beam cutting and control, and meeting the stringent requirements of large-scale scientific facilities for high-precision event timing.

[0123] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture, characterized in that, It adopts a modular design, including a main control board, an RTM board, an FMC board, a terminal matching board, and a terminal signal fan-out board, and also includes: The Zynq SoC timing main logic AMC board conforming to the microTCA.4 standard uses the Xilinx ZYNQ7000 Kintex device series ZYNQ-7045 SOC industrial-grade chip with a dual-width design; The heterogeneous firmware module based on Zynq SoC includes a processing subsystem (PS side) and a programmable logic subsystem (PL side). The PL side implements event timing data frame parsing, event trigger control, interrupt response mechanism and timing signal output functions, and supports nanosecond-level event timing accuracy. The PS side runs event scheduling algorithm and user interface, and communicates with the PL side at high speed through AXI bus, supporting multi-event concurrent scheduling, priority management and remote control. The point-to-point real-time signal transmission and sharing mechanism based on mLVDS supports high-speed, low-latency, and high-reliability transmission of critical control signals. The backplane signal output board conforming to the microTCA.4 standard and a variety of high-speed photoelectric conversion terminal matching boards are available. The backplane signal output board integrates a high-speed signal transmission channel, and the terminal matching board uses high-speed photoelectric conversion technology to realize real-time conversion and isolated transmission of electrical and optical signals. It is compatible with 3.3V, 5V and 24V level interface standards and supports modular expansion.

2. The high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The main logic AMC board includes a circuit board, crystal oscillator, programmable logic chip, driver chip, buffer driver chip, connector, data bus, FPGA I / O interface, bus switch, data buffer and DIP switch; the firmware achieves nanosecond-level event timing accuracy and supports dynamic configuration of timing parameters to adapt to different application scenarios.

3. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The Zynq SoC's PL terminal achieves nanosecond-level event timing accuracy through the FPGA's internal high-speed clock domain and counter structure, supporting precise setting of event trigger time and dynamic parameter configuration; users can adjust the trigger time, timing period, event priority, and delay compensation value according to the application scenario.

4. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The Zynq SoC's PS terminal communicates with the PL terminal at high speed via the AXI bus, supporting multi-event concurrent scheduling, priority management, and remote control. Key configuration parameters can be modified online through the PS terminal control software and sent to the PL terminal in real time via the AXI bus, enabling dynamic strategy adjustments without restarting the system during operation.

5. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, Each mLVDS signal has an independent input interface, output interface, and enable control interface, which are directly connected to the physical I / O pins of the FPGA, enabling independent control and flexible configuration of each signal, thus improving the system's flexibility and maintainability.

6. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The RTM board includes: Following the mTCA backplane board size and architecture specifications, efficient data signal conversion and transmission are achieved; Eight 1.8V LVDS differential signals are extracted from the AMC board, converted into single-ended signals, and then boosted to the 3.3V TTL standard by a level conversion chip to generate eight trigger signals. The signal drive and optical output module drives the HFBR-1414T optical module to emit optical signals through an AND gate logic chip; The external optical signal receiving and processing module converts optical signals into electrical signals through the HFBR-2412T optical receiving module. After being converted to 3.3V TTL level by a current converter, the signals are transmitted to the front panel for fast interlocking mechanism and trigger signal stop control.

7. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The FMC board includes: It conforms to the VITA 57.1 standard HP-type FMC interface specification and supports standardized and modular design; Twelve 1.8V LVDS differential signals are extracted from the template board, converted into single-ended signals, and then boosted to the 3.3V TTL standard by a level conversion chip to generate twelve trigger signals. Four of these signals are used as inputs to the DS1023-100 programmable delay chip, outputting four timing control signals with a precision of 100 picoseconds. It supports receiving two external timing signals, enhancing time synchronization capabilities and external control flexibility; The design features compatibility and scalability, supporting compatibility with mainstream communication architectures such as mTCA and ATCA. Higher precision signal processing can be achieved by replacing or upgrading the delay chip.

8. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The terminal matching board includes: The Altera EPM240T100C5N CPLD serves as the core controller, responsible for signal analysis and routing, and supports 3.3V and 5VI / O voltage compatibility. It uses the HFBR-2412T optoelectronic receiver module, which supports 650nm wavelength plastic optical fiber communication with a maximum transmission rate of 10Mbps. Configure two HFBR-1414T optoelectronic transmitter modules to achieve secondary optical signal fan-out output; The level conversion circuit supports voltage conversion from 1.2V to 5.5V, and the output level can be flexibly configured as 3.3V TTL or 5V TTL via a jumper selector; A 24V relay drive circuit, configured with a ULN2003 Darlington transistor array chip, drives an external 24V relay or actuator.

9. The event timing system according to claim 1, characterized in that, The terminal matching board's functions include: Optical signal input processing flow: The optical signal from the starting device is received by the HFBR-2412T and converted into a TTL level signal, which is then sent to the CPLD for processing and routing. The signal is then output as a 3.3V or 5V TTL signal through the level conversion module. The CPLD controls two HFBR-1414T modules to achieve secondary optical signal fan-out. 24V electrical signal output control: The CPLD outputs a control signal, which is driven by ULN2003 to control the on / off of the external 24V power supply and trigger mechanical equipment; Configuration and debugging interface: Provides a JTAG programming interface to support CPLD online programming and debugging; stores configuration information via external EEPROM to achieve automatic loading after power failure; Onboard LED indicators display the real-time status of the optical signal, power supply, and output channel operation.

10. A high-precision modular event timing system based on the microTCA.4 standard and Zynq SoC architecture according to claim 1, characterized in that, The terminal signal fan-out board's functions include: Optical signal input processing flow: The optical signal from the starting device is received by HFBR-2412T and converted into a TTL level signal, which is then sent to the CPLD for processing and routing. The signal is then output as a 3.3V or 5V TTL signal through the level conversion module. After receiving one input signal, the CPLD independently fans out 12 signals, which are then connected to 12 MC100EP138 ultra-high-speed programmable delay chips. Each signal is independently adjusted in phase and delay. By configuring the delay parameters of the MC100EP138 chip, the output of the 12 timing signals achieves high phase consistency, thereby improving the synchronous triggering accuracy of multi-channel devices.

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