Error injection testing method, system, device, equipment, storage medium and product

Abstract

This application relates to a method, system, apparatus, device, storage medium, and product for error injection testing. The error injection testing method includes: a programmable execution unit, in response to receiving a start operation from a main control processor, reading test case configuration information from a first preset address in shared memory; executing an error injection instruction sequence corresponding to the test case configuration information to trigger a target exception; generating a status code representing the test conclusion based on the matching result between the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information; and triggering a fast interrupt to the main control processor in response to the status code indicating that the test has passed, thereby driving the main control processor to load the next test case. This method improves the efficiency and repeatability of test execution and achieves a high degree of automation and closed-loop management of the error injection testing process.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an error injection testing method, system, apparatus, device, storage medium, and product. Background Technology

[0002] In existing chip verification, error injection and anomaly testing mainly rely on three methods: temporarily modifying registers, addresses, etc. via JTAG or scripts; designing customized anomaly triggering scenarios within each module and relying on manual observation of interrupts and logs; or using random stress testing. These methods generally suffer from poor repeatability, fragmented coverage, non-closed-loop testing, and low levels of regression automation, resulting in poor testing performance. Summary of the Invention

[0003] This application provides a method, system, apparatus, device, storage medium, and product for error injection testing, which can improve the efficiency and repeatability of test execution and achieve a high degree of automation and closed-loop management of the error injection testing process. The technical solution is as follows.

[0004] Firstly, an error injection testing method is provided, the method being executed by a programmable execution unit, the method comprising:

[0005] In response to receiving a startup operation from the main control processor, the test case configuration information is read from the first preset address of the shared memory;

[0006] Execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception;

[0007] Based on the matching result between the actual anomaly information of the target anomaly and the expected anomaly information corresponding to the test case configuration information, a status code representing the test conclusion is generated.

[0008] In response to the status code indicating that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to start loading the next test case.

[0009] Secondly, an error injection testing method is provided, which is executed by a main control processor, and the method includes:

[0010] Write the test case configuration information to the first preset address of the shared memory;

[0011] A startup operation is performed on the programming execution unit so that the programming execution unit performs an error injection test step;

[0012] In response to a rapid interruption from the programming execution unit, the loading of the next test case is initiated.

[0013] Thirdly, an error injection testing apparatus is provided, the apparatus being applied to a programmable execution unit, the apparatus comprising:

[0014] The test case reading module is used to read the test case configuration information from the first preset address of the shared memory in response to the start operation received from the main control processor.

[0015] The first execution module is used to execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception;

[0016] The generation module is used to generate a status code representing the test conclusion based on the matching result between the actual exception information of the target exception obtained and the expected exception information corresponding to the test case configuration information.

[0017] The triggering module is used to trigger a fast interrupt to the main control processor in response to the status code indicating that the test has passed, so as to drive the main control processor to start loading the next test case.

[0018] In one possible implementation, the generation module is used for,

[0019] If the actual anomaly information matches the expected anomaly information, the status code indicates that the test has passed.

[0020] If the actual anomaly information fails to match the expected anomaly information, the status code indicates that the test has failed.

[0021] In one possible implementation, the device further includes:

[0022] The first execution module is configured to execute a preset failure handling operation in response to the status code indicating that the test has failed; the failure handling operation includes at least one of the following: entering a standby state, or stopping execution.

[0023] In one possible implementation, the device further includes:

[0024] The clearing module is used to clear the residual interrupt state corresponding to the target exception before the first execution module executes the error injection instruction sequence corresponding to the use case configuration information.

[0025] In one possible implementation, the device further includes:

[0026] The result writing module is used to write the test result, which includes the status code, the test case configuration information, and the actual exception information, into the second preset address of the shared memory after the generation module generates the status code representing the test conclusion.

[0027] Fourthly, an error injection testing device is provided, the device being applied to a main control processor, the device comprising:

[0028] The test case writing module is used to write the test case configuration information to the first preset address of the shared memory;

[0029] The second execution module is used to perform a startup operation on the programming execution unit, so that the programming execution unit performs the error injection test steps;

[0030] The test case loading module is used to initiate the loading of the next test case in response to a rapid interruption from the programming execution unit.

[0031] In one possible implementation, the use case loading module is used for,

[0032] Read the test results written by the programming execution unit from the second preset address of the shared memory;

[0033] Based on the test results, the test case configuration information for the next test case is written to the first preset address.

[0034] In one possible implementation, the device further includes:

[0035] The result reading module is used to read the test result from the second preset address of the shared memory in response to the absence of the fast interrupt within a preset timeout period.

[0036] Fifthly, an error injection testing system is provided, the system including a main control processor, a programmable execution unit, and a shared memory;

[0037] The shared memory is configured with a first preset address for the main control processor and the programmable execution unit to access together, and a second preset address for the programmable execution unit to write test results;

[0038] The main control processor is used to write test case configuration information to the first preset address, perform a startup operation on the programmable execution unit, and, in response to a fast interrupt from the programmable execution unit, start loading the next test case;

[0039] The programmable execution unit is configured to, in response to the startup operation, read the test case configuration information of the test case from the first preset address, execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception, generate a status code representing the test conclusion based on the matching result of the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information, write the test result containing the status code to the second preset address, and trigger a fast interrupt to the main control processor in response to the status code indicating that the test has passed.

[0040] On the other hand, an electronic device is provided, comprising a processor and a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to implement the above-described error injection testing method.

[0041] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described error injection testing method.

[0042] On the other hand, a computer program product is provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to execute to implement the error injection testing method provided in the various optional implementations described above.

[0043] The error injection testing method provided in this application embodiment involves a programmable execution unit (PLU) responding to a startup operation received from the main control processor. The PLU reads the test case configuration information from a first preset address in the shared memory, executes the error injection instruction sequence corresponding to the configuration information, triggering a target exception. Then, it matches the actual exception information of the target exception with its corresponding expected exception information, generates a status code representing the test conclusion based on the matching result, and triggers a fast interrupt to the main control processor when the status code indicates the test has passed, driving the main control processor to load the next test case. This method seamlessly connects the configuration, triggering, execution, testing, and iteration stages of the test. Through shared memory and an interrupt mechanism, it achieves efficient decoupling and collaboration between the main control unit and the execution unit, improving the efficiency and repeatability of test execution and realizing a high degree of automation and closed-loop management of the error injection testing process.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] Figure 1 A flowchart of an exemplary embodiment of this application is shown;

[0047] Figure 2 A flowchart of an error injection testing method provided in another exemplary embodiment of this application is shown;

[0048] Figure 3 This invention provides a schematic diagram of the structure of an exemplary embodiment of the error injection testing system.

[0049] Figure 4 A block diagram of an error injection testing apparatus provided in an exemplary embodiment of this application is shown;

[0050] Figure 5 A block diagram of an error injection testing apparatus provided in another exemplary embodiment of this application is shown. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods consistent with some aspects of this application as detailed in the appended claims.

[0052] To improve the effectiveness of error injection testing, this application provides an error injection testing method that can achieve batch automatic regression testing during the testing process. Figure 1 A flowchart of an exemplary embodiment of this application is shown. This method can be executed by a programmable execution unit, such as... Figure 1 As shown, this error injection testing method may include the following steps.

[0053] Step 110: In response to receiving the start operation from the main control processor, read the test case configuration information from the first preset address of the shared memory.

[0054] The startup operation refers to the active processor sending a startup signal to the programmable execution unit to trigger the programmable confidence unit to begin executing the error injection test process. In one possible implementation, the startup operation of the main control processor can be a reset startup operation or a power-on startup operation. In the embodiments of this application, the first startup operation executed by the main control processor can be a power-on startup operation, and subsequent startup operations can be reset startup operations.

[0055] The shared memory supports joint access by the main control processor and the programmable execution unit (PMU) as an area for data exchange and state synchronization between the two. In this embodiment, the main control processor can write the test case configuration information of the test cases into the first preset address of the shared memory. In response to the start operation, the PMU can read the test case configuration information from the first preset address of the shared memory to execute the error injection test process. In addition, the test results of the PMU executing the error injection test process can also be written into the shared memory for the main control processor to obtain the test results.

[0056] The test case configuration information can be the test case identifier or the test case configuration parameters. When the test case configuration information is the test case identifier, the programmable execution unit can query and obtain the complete configuration parameters from the pre-set test case library or a specified structure of the shared memory based on the test case identifier after reading the test case identifier. The appropriate configuration parameters may include the error type to be injected, the target module or address to be injected, the injection triggering conditions and timing, and the expected exception information for verification, etc.

[0057] Step 120: Execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception.

[0058] An error injection instruction sequence is a series of low-level control instructions dynamically generated or retrieved by a programmable execution unit (PEP) based on the test case configuration information. It is used to simulate specific hardware failures or software state errors. The PEP executes the error injection instruction sequence to cause an abnormal operating state, i.e., the target anomaly corresponding to the test case. For example, the error injection instruction sequence can be address out of bounds, illegal opcode, illegal CSR (Control and Status Register) access, parameter overflow, queue overflow, or NAN-INF (Not a Number - Infinity) data, etc.

[0059] During system operation, the interrupt controller and related hardware modules may retain unprocessed interrupt flags or error states due to historical operations. If these residual interrupt states are not cleared, the method further includes the following steps to ensure the independence and accuracy of the test: Before executing the error injection instruction sequence corresponding to the test case configuration information.

[0060] Clear the residual interrupt state corresponding to the target anomaly.

[0061] By taking the above steps, we can isolate any legacy issues that may have arisen from historical testing, ensuring that each triggered target anomaly uniquely originates from the currently configured sequence of error injection instructions, thereby improving the accuracy and reliability of the test structure.

[0062] Step 130: Based on the matching results between the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information, generate a status code representing the test conclusion.

[0063] The actual exception information of the target exception is collected and read by the programmable execution unit after executing the error injection instruction sequence by capturing and entering the interrupt service routine corresponding to the target exception. This information comprehensively records the system's real-time response to the injected fault, typically including the specific exception type triggered, the precise memory address where the exception occurred, a snapshot of the status of key registers, a timestamp, and detailed error logs generated by the system. Expected exception information, on the other hand, is predefined in the test case configuration information, describing the standard abnormal behavior that the system should exhibit under an ideal fault-tolerant model, and constitutes the test baseline.

[0064] In addition, after reading the actual exception information of the target exception, the programmable execution unit performs an interrupt clearing operation, that is, writes a specific value to the status register of the interrupt controller to clear the current interrupt pending state, thereby ensuring the integrity of the interrupt response logic and the normal triggering of subsequent interrupts.

[0065] The matching result between actual and expected anomaly information can include both successful and unsuccessful matches. The matching process is achieved by comparing the consistency of each field in the actual and expected anomaly information item by item: if both are completely consistent across preset comparison dimensions, the match is considered successful; if there is a difference in any dimension, the match is considered unsuccessful. For example, the preset comparison dimensions may include at least one: anomaly type, address, logs, etc. This mechanism enables automated and refined testing of system anomaly response behavior.

[0066] If the actual abnormal information matches the expected abnormal information, a status code is determined to indicate that the test has passed. Indicatively, this status code can be defined as PASS or the value 0.

[0067] If the actual exception information fails to match the expected exception information, the status code indicates that the test has failed. Indicatively, this status code can be defined as FAIL or a non-zero error code.

[0068] After generating the status code representing the test results, the method further includes:

[0069] The test results, which include status codes, test case configuration information, and actual exception information, are written to a second preset address in the shared memory.

[0070] The test case configuration information in the test results can be used to identify test cases, thereby reducing information redundancy in the test results.

[0071] In one possible implementation, the programmable execution unit can write the test result into a second preset address of the shared memory in an encoded manner; by persistently recording the test result, the main control processor can extract the test result, providing a data basis for subsequent test report generation, test result statistics, and test failure analysis, thereby realizing a test closed loop.

[0072] Step 140: In response to the status code indicating that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to start loading the next test case.

[0073] This fast interrupt is an efficient signal indicating task completion and success. Upon receiving the fast interrupt, the main processor initiates the loading of the next test case, eliminating the need for continuous polling and thus reducing resource overhead. Illustratively, the main processor initiating the loading of the next test case can be implemented as follows:

[0074] Read the test results written by the programming execution unit from the second preset address of the shared memory;

[0075] Based on the test results, write the test case configuration information for the next test case to the first preset address.

[0076] In other words, the main control processor responds to fast interrupts and actively executes the preset test sequence management logic. For example, it retrieves the next test case from the test queue, writes its test case configuration information to the first preset address of the shared memory, and performs a start operation (such as a reset start operation) to the programmable execution unit again, thereby driving the entire test process to run continuously and automatically.

[0077] To ensure continuous automation and accuracy of the testing process, the main control processor can write the configuration information of the next test case to a first preset address by overwriting. In other words, the first preset address is designed as a reusable test configuration buffer. The configuration information of the new test case overwrites the old data of the previous test case. In this way, the main control processor does not need to perform additional memory allocation and release operations when writing test cases, ensuring the efficiency and determinism of the testing process.

[0078] In another possible implementation, in response to a status code indicating that the test has failed, a preset failure handling operation is executed; the failure handling operation includes at least one of the following: entering a standby state, or stopping execution.

[0079] The standby state refers to the programmable execution unit pausing subsequent test sequences, maintaining the current target abnormal data, and providing real-time online diagnostic opportunities for the main control processor or external debugging tools; the stop execution state terminates the entire test process after persistently storing the test results to prevent irreversible damage to the system.

[0080] In summary, the error injection testing method provided in this application embodiment involves a programmable execution unit (PLU) responding to a startup operation received from the main control processor. The PLU reads the test case configuration information from a first preset address in the shared memory, executes the error injection instruction sequence corresponding to the configuration information, triggering a target exception. Then, it matches the actual exception information of the target exception with its corresponding expected exception information, generates a status code representing the test conclusion based on the matching result, and triggers a fast interrupt to the main control processor when the status code indicates the test has passed, driving the main control processor to load the next test case. This method seamlessly connects the configuration, triggering, execution, testing, and iteration stages of the test. Through shared memory and an interrupt mechanism, it achieves efficient decoupling and collaboration between the main control unit and the PLU, improving the efficiency and repeatability of test execution and realizing a high degree of automation and closed-loop management of the error injection testing process.

[0081] With Figure 1 The error injection test method for the programming execution unit shown corresponds to that of the program execution unit. Figure 2 A flowchart of an error injection testing method provided in another exemplary embodiment of this application is shown. This method can be executed by a main control processor, such as... Figure 2 As shown, the error injection test may include the following steps.

[0082] Step 210: Write the test case configuration information into the first preset address of the shared memory.

[0083] Step 220: Perform a startup operation on the programming execution unit so that the programming execution unit performs the error injection test steps.

[0084] This error can be referenced in the testing steps as follows: Figure 1 The relevant details of the illustrated embodiments will not be repeated here.

[0085] Step 230: In response to a rapid interruption from the programming execution unit, start loading the next test case.

[0086] The process of starting the next test case can be implemented as follows:

[0087] Read the test results written by the programming execution unit from the second preset address of the shared memory;

[0088] Based on the test results, write the test case configuration information for the next test case to the first preset address.

[0089] The implementation process of each step of the main controller in the above processes can be referred to as follows: Figure 1 The relevant details of the illustrated embodiments will not be repeated here.

[0090] Furthermore, if a status code indicates that the test has failed, a fast interrupt cannot be triggered. To prevent the test process from stalling due to the main control processor waiting indefinitely, this method also includes:

[0091] In response to the absence of a fast interrupt within a preset timeout period, the test results are read from the second preset cell of the shared memory.

[0092] By setting up timeout monitoring and active reading mechanisms, the testing process can be continued in a controllable manner or terminated safely in abnormal situations, thus avoiding test freezes.

[0093] In summary, the error injection testing method provided in this application involves the main control processor writing test case configuration information into a first preset address of the shared memory. The programmable execution unit, responding to the start operation received from the main control processor, reads the test case configuration information from the first preset address and executes the error injection instruction sequence corresponding to the configuration information to trigger the target exception. Then, the actual exception information of the target exception is matched with its corresponding expected exception information. Based on the matching result, a status code representing the test conclusion is generated. If the status code indicates that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to load the next test case. This method seamlessly connects the configuration, triggering, execution, testing, and iteration stages of the test. Through shared memory and the interrupt mechanism, it achieves efficient decoupling and collaboration between the main control unit and the execution unit, improving the efficiency and repeatability of test execution and realizing a high degree of automation and closed-loop management of the error injection testing process.

[0094] Figure 3 A schematic diagram of the structure of an error injection testing system provided in an exemplary embodiment of this application is shown, as follows: Figure 3 As shown, the error injection test system includes a main control processor 310, a programmable execution unit 320, and a shared memory 330;

[0095] The shared memory is configured with a first preset address that can be accessed by both the main control processor and the programmable execution unit, and a second preset address that allows the programmable execution unit to write test results.

[0096] The main control processor is used to write test case configuration information to the first preset address, perform a startup operation on the programmable execution unit, and, in response to a fast interrupt from the programmable execution unit, start loading the next test case;

[0097] The programmable execution unit is used to respond to the startup operation by reading the test case configuration information of the test case from the first preset address, executing the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception, generating a status code representing the test conclusion based on the matching result of the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information, writing the test result containing the status code to the second preset address, and triggering a fast interrupt to the main control processor in response to the status code indicating that the test has passed.

[0098] For other related information about programmable execution units and main control processors, please refer to the following: Figure 1 or Figure 2 The relevant details of the illustrated embodiments will not be repeated here.

[0099] To illustrate, consider a fault injection test system using shared memory as a DDR (Double Data Rate) mailbox, programmable execution units as PE-RV (Processing Element-RISC-V architecture), and a TOP controller (i.e., the main controller processor). One test cycle can be implemented as follows: The TOP controller writes test case configuration information (such as test case identifier, case_number) to the first preset address of the DDR mailbox and resets and starts the PE-RV. After power-on, the PE-RV reads the test case configuration information, selects the corresponding injection test case, and executes the test procedure: clearing residual target IRQs (Interrupt Requests), then issuing a sequence of fault injection instructions, and subsequently waiting for the specified exception IRQ, in the ISR / handle (Interrupt Service Routine / Interrupt...) The Handler (interrupt service routine) reads the exception code and clears the interrupt, automatically comparing the read exception code with the expected exception mask. The test result is written to DDR_FLAG (i.e., the second preset address) in encoded form. This test result includes the test case identifier, status code, and actual exception information. In addition, if the status code is PASS, a fast interrupt is triggered to notify the Top controller. After receiving the fast interrupt, the Top controller reads DDR_FLAG, records the test result, writes the test case configuration information for the next test case, and then resets PE-RV to enter the next round of testing, thereby achieving batch automatic regression and state isolation between test cases.

[0100] Figure 4 This illustration shows a block diagram of an error injection testing apparatus provided in an exemplary embodiment of this application. This apparatus can be applied to a programmable execution unit to perform all or part of the steps in the embodiment shown in Figure 1, such as... Figure 4 As shown, the device may include the following modules.

[0101] The test case reading module 410 is used to read the test case configuration information from the first preset address of the shared memory in response to receiving the start operation of the main control processor;

[0102] The first execution module 420 is used to execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception;

[0103] The generation module 430 is used to generate a status code representing the test conclusion based on the matching result between the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information.

[0104] Trigger module 440 is used to trigger a fast interrupt to the main control processor in response to the status code indicating that the test has passed, so as to drive the main control processor to start loading the next test case.

[0105] In one possible implementation, the generation module 430 is used for,

[0106] If the actual anomaly information matches the expected anomaly information, the status code indicates that the test has passed.

[0107] If the actual anomaly information fails to match the expected anomaly information, the status code indicates that the test has failed.

[0108] In one possible implementation, the device further includes:

[0109] The first execution module is configured to execute a preset failure handling operation in response to the status code indicating that the test has failed; the failure handling operation includes at least one of the following: entering a standby state, or stopping execution.

[0110] In one possible implementation, the device further includes:

[0111] The clearing module is used to clear the residual interrupt state corresponding to the target exception before the first execution module executes the error injection instruction sequence corresponding to the use case configuration information.

[0112] In one possible implementation, the device further includes:

[0113] The result writing module is used to write the test result, which includes the status code, the test case configuration information, and the actual exception information, into the second preset address of the shared memory after the generation module 430 generates the status code representing the test conclusion.

[0114] In summary, the error injection testing device provided in this application embodiment allows the programmable execution unit to respond to a startup operation received from the main control processor. It reads the test case configuration information from a first preset address in the shared memory, executes the error injection instruction sequence corresponding to the configuration information to trigger a target exception, and then matches the actual exception information of the target exception with its corresponding expected exception information. Based on the matching result, a status code representing the test conclusion is generated. If the status code indicates that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to load the next test case. This device seamlessly connects the configuration, triggering, execution, testing, and iteration stages of the test. Through shared memory and an interrupt mechanism, it achieves efficient decoupling and collaboration between the main control unit and the execution unit, improving the efficiency and repeatability of test execution and realizing a high degree of automation and closed-loop management of the error injection testing process.

[0115] Figure 5 A block diagram of an error injection testing apparatus provided in another exemplary embodiment of this application is shown. This apparatus can be applied to a main control processor to perform all or part of the steps in the embodiment shown in Figure 2, such as... Figure 5 As shown, the device may include the following modules.

[0116] The test case writing module 510 is used to write the test case configuration information of the test cases into the first preset address of the shared memory;

[0117] The second execution module 520 is used to perform a startup operation on the programming execution unit so that the programming execution unit performs an error injection test step;

[0118] The test case loading module 530 is used to initiate the loading of the next test case in response to a rapid interruption from the programming execution unit.

[0119] In one possible implementation, the use case loading module 530 is used for,

[0120] Read the test results written by the programming execution unit from the second preset address of the shared memory;

[0121] Based on the test results, the test case configuration information for the next test case is written to the first preset address.

[0122] In one possible implementation, the device further includes:

[0123] The result reading module is used to read the test result from the second preset address of the shared memory in response to the absence of the fast interrupt within a preset timeout period.

[0124] In summary, the error injection testing device provided in this application embodiment involves the main control processor writing test case configuration information into a first preset address of the shared memory. The programmable execution unit, responding to the start operation received from the main control processor, reads the test case configuration information from the first preset address and executes the error injection instruction sequence corresponding to the configuration information to trigger the target exception. Then, the actual exception information of the target exception is matched with its corresponding expected exception information. Based on the matching result, a status code representing the test conclusion is generated. If the status code indicates that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to load the next test case. This device seamlessly connects the configuration, triggering, execution, testing, and iteration stages of the test. Through shared memory and the interrupt mechanism, it achieves efficient decoupling and collaboration between the main control unit and the execution unit, improving the efficiency and repeatability of test execution and realizing a high degree of automation and closed-loop management of the error injection testing process.

[0125] In one exemplary embodiment, an electronic device is provided, which can be implemented as a programmable execution unit or a main control processor. The electronic device includes a processor and a memory, the memory storing at least one computer program, which is loaded and executed by the processor to implement the above-described functionality. Figure 1 or Figure 2 All or part of the steps of the error injection testing method shown in any embodiment.

[0126] In one exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program that is loaded and executed by a processor to implement the above. Figure 1 or Figure 2 All or part of the steps of the error injection testing method shown in any embodiment. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0127] In one exemplary embodiment, a computer program product is also provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the above-described actions. Figure 1 or Figure 2 All or part of the steps of the error injection testing method shown in any embodiment.

[0128] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0129] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for error injection testing, characterized in that, The method is executed by a programmable execution unit, and the method includes: In response to receiving a startup operation from the main control processor, the test case configuration information is read from the first preset address of the shared memory; Execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception; Based on the matching result between the actual anomaly information of the target anomaly and the expected anomaly information corresponding to the test case configuration information, a status code representing the test conclusion is generated. The test result, which includes the status code, the test case configuration information, and the actual exception information, is written to the second preset address of the shared memory. In response to the status code indicating that the test has passed, a fast interrupt is triggered to the main control processor to drive the main control processor to start loading the next test case; wherein, starting loading the next test case includes: in response to the fast interrupt, reading the test result written by the programmable execution unit from the second preset address of the shared memory, and writing the test case configuration information of the next test case to the first preset address based on the test result.

2. The method according to claim 1, characterized in that, The step of generating a status code representing the test conclusion based on the matching result between the actual anomaly information of the target anomaly and the expected anomaly information corresponding to the test case configuration information includes: If the actual anomaly information matches the expected anomaly information, the status code indicates that the test has passed. If the actual anomaly information fails to match the expected anomaly information, the status code indicates that the test has failed.

3. The method according to claim 1 or 2, characterized in that, The method further includes: In response to the status code indicating that the test failed, a preset failure handling operation is executed; the failure handling operation includes at least one of the following: entering a standby state, or stopping execution.

4. The method according to claim 1, characterized in that, Before executing the error injection instruction sequence corresponding to the use case configuration information, the method further includes: Clear the residual interruption state corresponding to the target anomaly.

5. A method for error injection testing, characterized in that, The method is executed by the main control processor, and the method includes: Write the test case configuration information to the first preset address of the shared memory; A startup operation is performed on the programmable execution unit so that the programmable execution unit performs the error injection test steps as described in any one of claims 1 to 4; In response to a rapid interrupt from the programmable execution unit, the loading of the next test case is initiated; The loading of the next test case includes: Read the test results written by the programmable execution unit from the second preset address of the shared memory; Based on the test results, the test case configuration information for the next test case is written to the first preset address.

6. The method according to claim 5, characterized in that, The method further includes: In response to the absence of the fast interrupt within a preset timeout period, the test result is read from a second preset address of the shared memory.

7. A fault injection testing system, characterized in that, The system includes a main control processor, a programmable execution unit, and a shared memory; The shared memory is configured with a first preset address for the main control processor and the programmable execution unit to access together, and a second preset address for the programmable execution unit to write test results; The main control processor is used to write test case configuration information of test cases to the first preset address, perform a startup operation on the programmable execution unit, and, in response to a fast interrupt from the programmable execution unit, start loading the next test case; wherein, starting loading the next test case includes: in response to the fast interrupt, reading the test result written by the programmable execution unit from the second preset address of the shared memory, and writing the test case configuration information of the next test case to the first preset address based on the test result; The programmable execution unit is configured to, in response to the startup operation, read the test case configuration information of the test case from the first preset address, execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception, generate a status code representing the test conclusion based on the matching result of the actual exception information of the target exception and the expected exception information corresponding to the test case configuration information, write the test result containing the status code to the second preset address, and trigger a fast interrupt to the main control processor in response to the status code indicating that the test has passed.

8. An error injection testing device, characterized in that, The apparatus is used in a programmable execution unit, and the apparatus includes: The test case reading module is used to read the test case configuration information from the first preset address of the shared memory in response to the start operation received from the main control processor. The first execution module is used to execute the error injection instruction sequence corresponding to the test case configuration information to trigger the target exception; The generation module is used to generate a status code representing the test conclusion based on the matching result between the actual exception information of the target exception obtained and the expected exception information corresponding to the test case configuration information. The result writing module is used to write the test results, which include the status code, the test case configuration information, and the actual exception information, to the second preset address of the shared memory. A triggering module is configured to trigger a fast interrupt to the main control processor in response to the status code indicating that the test has passed, so as to drive the main control processor to start loading the next test case; wherein, starting loading the next test case includes: in response to the fast interrupt, reading the test result written by the programmable execution unit from the second preset address of the shared memory, and writing the test case configuration information of the next test case to the first preset address based on the test result.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing at least one computer program, which is loaded and executed by the processor to implement the error injection testing method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to implement the error injection testing method as described in any one of claims 1 to 6.

11. A computer program product, characterized in that, The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform an error injection test method as described in any one of claims 1 to 6.

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