Temperature and performance cooperative regulation and control method of MODT mainboard central processing unit

Abstract

The invention belongs to the technical field of thermal management and performance regulation and control of a computer hardware system, and particularly discloses a temperature and performance coordinated regulation and control method of an MODT mainboard central processing unit. The entropy production rate of the system is calculated in real time in combination with a thermodynamic entropy production evaluation mechanism, and pre-cooling or advanced frequency reduction pulse type regulation and control are triggered when entropy production exceeds the threshold; meanwhile, a biological rhythm simulation mechanism is introduced, high-frequency and low-frequency alternating periodic oscillation control is carried out on the frequency of the processor in a millisecond-level window, the two mechanisms cooperatively act on the power management unit, and microsecond-level voltage regulation and heat dissipation driving linkage is achieved. According to the technical scheme, on the premise that the hardware cost is not increased, the energy efficiency performance, the transient heat dissipation capacity and the long-term operation reliability of the system under the high dynamic load are improved.

Description

Technical Field

[0001] This invention belongs to the field of thermal management and performance regulation technology of computer hardware systems, specifically relating to a method for coordinated temperature and performance regulation of the central processing unit on a MODT motherboard. Background Technology

[0002] With the evolution of mobile processors towards desktop architecture, MODT motherboards, combining the energy efficiency advantages of mobile platforms with the scalability of desktop platforms, occupy an important position in the field of miniaturized high-performance computing. The CPU's frequency management and thermal control system, as the fundamental framework for ensuring device reliability, plays a decisive role in maintaining the balance between peak performance and energy efficiency of the computing platform. With the increasing complexity of application workloads, building a temperature control and scheduling coordination mechanism that can adapt to high dynamic computing power demands has become a core evolutionary direction for modern motherboard firmware design and power management systems.

[0003] The temperature and performance co-regulation technology for central processing units (CPUs) primarily involves collecting real-time temperature data and operating current status of the processor core, and dynamically intervening in the operating frequency based on a preset heat dissipation envelope. This technical solution aims to maintain the processor's operation within a safe temperature range through closed-loop feedback control, preventing irreversible physical damage to the hardware due to overheating, and attempting to allocate the optimal power budget for varying computational tasks.

[0004] Existing thermal management strategies often employ continuous linear adjustments based on temperature gradients, exhibiting significant latency when handling unsteady load fluctuations. This makes it difficult for the system's response speed to match the instantaneous bursts of processor instruction flow. This static feedback mechanism not only induces substantial wasted power consumption but also results in high entropy loss during heat transfer due to the lack of dynamic intervention on the physical boundary layer thermal resistance of the cooling system. Furthermore, traditional methods fail to fully integrate the trend characteristics and biological regulatory rhythms of computational loads, making it difficult to achieve deep coupling between heat dissipation efficiency and computational frequency within millisecond-level time windows. This severely limits the overall energy efficiency performance of MODT motherboards under high loads. Summary of the Invention

[0005] The purpose of this invention is to provide a method for coordinated temperature and performance control of the central processing unit on a MODT motherboard, thereby solving the problems mentioned in the background art.

[0006] To achieve the above objectives, this invention provides a method for coordinated temperature and performance control of the central processing unit (CPU) on a MODT motherboard, comprising the following steps: A computational load awareness model based on a spiking neural network is constructed to transform the instruction flow characteristics of the central processing unit core into a time-coded pulse sequence to characterize the dynamic trend of the temperature change rate. Establish a thermodynamic entropy production assessment mechanism to calculate the system's entropy production rate per unit time in real time based on the current working state of the central processing unit and the physical parameters of the heat dissipation system. A strategy for minimizing entropy production is set up. When the entropy production rate exceeds a preset threshold, a pulse-type control action of pre-cooling or early frequency reduction is triggered. A biological rhythm simulation mechanism is introduced to implement periodic oscillation control of the central processing unit's operating frequency, alternating between high and low frequencies, within a millisecond-level time window; The pulsed regulation action and periodic oscillation control are combined and applied to the power management unit of the central processing unit to achieve a dynamic balance between temperature and performance.

[0007] Preferably, the construction of the computational load perception model based on a spiking neural network includes: The physical core of the central processing unit is mapped to a basic neuron unit in a spiking neural network; The microarchitectural features of the central processing unit are obtained by using performance monitoring counters. These microarchitectural features include instruction issue queue depth, cache hit rate, and branch prediction failure rate. The instruction issue queue depth, cache hit rate, and branch prediction failure rate are integrated using a nonlinear fusion operator to form a continuous state vector reflecting the current computing intensity of the central processing unit. The perception model uses leakage current integration triggering logic to transform the continuous state vector into pulse events with discrete characteristics. When the increment of the instruction emission queue depth during the sampling period shows an exponential upward trend and the accumulated potential exceeds the preset dynamic threshold, the neuron unit fires a time-domain pulse. The arrangement density and frequency of the pulse sequence characterize the temperature rise rate trend of the central processing unit core within a preset millisecond time period, transforming the lagging temperature values ​​into a predictable pulse event stream.

[0008] Preferably, the establishment of the thermodynamic entropy production assessment mechanism includes: The central processing unit, thermal interface material, thermal dispersion top cover, heat sink contact surface and heat sink fins are abstracted into a multi-level thermodynamic physical system; Obtain the calibration parameter library built into the motherboard firmware. The calibration parameter library is initialized according to the heatsink model, thermal conductivity and airflow structure inside the chassis. The forced convection heat transfer coefficient is derived by real-time fan speed, and the entropy production generated when heat passes through the interfaces of each level of the multi-level thermodynamic physical system is calculated by using the relationship between heat flux density and local temperature gradient. The entropy production rate is defined as the product of the ratio of heat flow to the square of absolute temperature, and is integrated over the entire heat transfer path to reflect the relationship between the proportion of electrical energy converted into effective computational power consumption and the proportion converted into ineffective heat energy. An ambient temperature compensation logic is introduced. By sensing the ambient temperature through thermistors arranged in different areas of the motherboard, when the ambient temperature rises and the heat dissipation temperature difference decreases, the nonlinear mapping coefficient is automatically adjusted so that the calculation result of the entropy production rate tends to be conservative, triggering the control action.

[0009] Preferably, the pulsed control action that triggers pre-cooling or early frequency reduction includes: When the perception model predicts an impending load surge and the entropy production rate indicates that the current heat dissipation path cannot efficiently handle the heat, intervention is initiated before the temperature reaches the critical point. The precooling action is achieved by instantaneously increasing the driving current of the thermoelectric cooler, applying a short-duration, high-amplitude current pulse to the thermoelectric cooler, and the duration of the current pulse is controlled within a predetermined range of milliseconds; The Peltier effect generated by the current pulse produces an instantaneous low temperature at the contact surface between the central processing unit and the heat sink, thereby breaking down the thermal boundary layer formed by the hysteresis of molecular thermal motion, reducing transient thermal resistance and stimulating the heat sink's heat absorption capacity. The pre-frequency reduction action, based on the prediction results of the pulse neural network, actively reduces the frequency multiplier or power supply voltage of the central processing unit within a preset lead time before the actual temperature rises, thereby reducing the rate of heat generation.

[0010] Preferably, the introduction of the biological rhythm simulation mechanism includes: The frequency scheduling layer enables the central processing unit to switch its operating frequency rapidly between two states, and the periodic oscillation control adopts a frequency modulation method with a fixed period and duty cycle. The oscillation period of the periodic oscillation control is set in the range of milliseconds, and within each period, the high frequency band corresponds to the maximum turbo frequency of the central processing unit, and the low frequency band corresponds to the minimum stable frequency required to maintain basic computing tasks. The switching process between the high-frequency band and the low-frequency band is directly scheduled by the motherboard firmware layer, and the duty cycle is dynamically adjusted according to the application load type. For sustained peak tasks such as graphics rendering or video processing, a high duty cycle mode is used to increase the duration of the high-frequency band. For background services or lightweight tasks, a low duty cycle mode is used to increase the proportion of the low frequency band and mitigate the accumulation of local hot spots in the kernel caused by continuous current injection.

[0011] Preferably, the power management unit that works in conjunction with the central processing unit includes: The power management unit, acting as an actuator, receives physical constraint instructions from the entropy production assessment mechanism and performance prediction instructions from the perception model. The power management unit adjusts the supply voltage in response to the integrated digital voltage regulator to match the frequency switching requirements of the periodic oscillation control. When the frequency is switched to the higher frequency band, the digital voltage regulator synchronously increases the core voltage to maintain the stability of the logic threshold potential; When the frequency is switched to the low frequency band, the core voltage drops synchronously to reduce leakage current power consumption; The power management unit synchronously coordinates the drive circuit of the thermoelectric cooler with the chassis fan control interface to form a closed-loop multi-physics field collaborative control circuit. During the pre-cooling process, the power management unit suppresses drastic changes in fan speed, maintains stable airflow pressure using aerodynamic inertia, and then increases the fan speed to force heat dissipation after heat has been transferred to the heat sink fins.

[0012] Preferably, the perception model is trained offline using a historical workload dataset during the training phase; The historical load dataset covers command flow patterns and corresponding temperature response curves under different application scenarios; By optimizing synaptic weights, the causal relationship between different command flow combinations and subsequent measured temperature change rates is identified, enabling pulse delivery to precede the actual heat accumulation process. The perception model identifies instruction fingerprints and outputs a marked pulse sequence to inform the power management unit to perform local fine-tuning of the voltage of the processor's floating-point arithmetic unit. The spiking neural network communicates with the power management unit via a lightweight pulse event descriptor, which includes a timestamp of pulse generation, load intensity category, and predicted temperature rise gradient level to reduce data communication latency.

[0013] Preferably, the calibration parameter library has an online correction function, specifically including: During idle periods of system operation, thermal probe tests are automatically performed, which involve applying a known short-term constant load to the central processing unit to monitor the slope of the temperature rise curve and changes in fan speed. By comparing the measured thermal response curves with the theoretical model, we can infer the aging state of the thermal grease, the dust accumulation state of the heat sink fins, and the obstruction state of the chassis airflow. When the measured entropy production rate is consistently higher than the theoretical prediction, the adaptive algorithm increases the thermal resistance deviation coefficient in the calibration parameter library to improve the sensitivity of the threshold determination in the entropy production minimization control strategy.

[0014] Preferably, the periodic oscillation control further includes frequency transition optimization and bus coordination logic: By utilizing the fast frequency locking technology of hardware phase-locked loop, and through the preset of multiple sets of frequency configuration registers, the switching between different frequency levels can be realized; Based on the real-time junction temperature of the central processing unit, the transition slope between the high-frequency band and the low-frequency band is dynamically adjusted. When the junction temperature reaches the safe upper limit, a smooth curve transition is introduced to reduce the inductive load impact caused by voltage transients. The frequency of the ring bus inside the central processing unit is synchronously adjusted. When the core operating frequency is in the high-frequency range, the ring bus bandwidth is synchronously increased. When in the low-frequency band, the bus bandwidth is reduced and the signal toggle rate is decreased, thereby reducing dynamic power consumption.

[0015] Preferably, the synergistic effect also includes parallel regulation optimization and security assurance: For processors with multiple physical core clusters, a distributed perception submodule is adopted, and the submodules interact with each other through a neuron lateral inhibition mechanism. When a core cluster predicts that thermal runaway is about to occur, it sends a suppression signal to the neighboring core clusters, requesting the neighboring clusters to reduce their frequency to free up heat dissipation space. The power management unit has a built-in thermal inertia predictor that simulates the future temperature trend after the control command fails in real time. If the prediction result shows that there is a risk of exceeding the physical tolerance limit, the control command will be forcibly overridden and the unit will enter the hardware-level cooling mode. The control method is integrated into the power management subsystem of the motherboard firmware. Its execution priority is higher than that of the operating system's task scheduler, and it is already in operation during the boot phase before the operating system loads.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention introduces a spiking neural network to proactively perceive the computational load, solving the problem of passive response in traditional temperature control methods that rely solely on the current temperature value, and achieving millisecond-level prediction and intervention for unsteady-state loads; 2. By establishing a control objective centered on minimizing thermodynamic entropy production, heat dissipation efficiency and computational performance are unified under the same physical framework, thereby reducing the generation of ineffective power consumption; 3. By simulating the biological body temperature regulation rhythm to implement high-frequency-low-frequency periodic oscillation control, the transient physical effect of pulse current is used to break down the thermal boundary layer, thereby improving the transient response capability of the heat dissipation system. 4. Without increasing additional hardware costs, the overall solution achieves deep synergy between temperature and performance through firmware-level algorithm innovation, improving the overall energy efficiency and long-term operational reliability of the MODT motherboard under high dynamic load scenarios. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2 This is a schematic diagram of the core principle framework of computational load sensing and thermodynamic entropy production assessment based on spiking neural networks in this invention; Figure 3 This is a logical flow diagram of the coordinated coupling of pulsed control action and periodic oscillation control in this invention; Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow between the power management unit and the multiphysics actuator in this invention; Figure 5 This is a flowchart illustrating the logical flow framework of the biorhythm simulation mechanism parameter adaptive adjustment based on different application load types in this invention. Detailed Implementation

[0018] Example 1: Reference Figures 1 to 5 In the MODT motherboard CPU temperature and performance coordinated control method, the method deeply integrates neuromorphic computing theory and thermodynamic non-equilibrium theory to construct a control system capable of proactively responding to unsteady workloads. Specifically, the method includes the following steps: Step 1 involves constructing a computational load sensing model based on a spiking neural network. This model transforms the instruction flow characteristics of the CPU cores into time-coded pulse sequences to characterize the dynamic trend of temperature change rate. In practice, the sensing model is not simply load monitoring; rather, it maps each physical core of the CPU to a basic neuron unit in a spiking neural network. The input signals to these neurons are no longer traditional utilization percentages, but rather combinations of deep features derived from the microarchitecture level.

[0019] The input layer of the perceptual model continuously acquires the CPU's instruction issue queue depth, cache hit rate, and branch prediction failure rate. These multidimensional features are initially integrated through a nonlinear fusion operator to form a continuous state vector that reflects the processor's current computational intensity.

[0020] The perception model employs a leakage current integration triggering model, transforming the continuous state vector into discrete pulse events. When the instruction issue queue depth increases within a short time window, accompanied by drastic fluctuations in cache hit rate, the corresponding neuron unit accumulates potential. Once the potential exceeds a preset dynamic threshold, a time-domain pulse is emitted. The density and frequency of these pulse sequences directly characterize the rate of temperature rise that the processor core may experience within the next 5 to 20 milliseconds. For example, a high-frequency, dense pulse sequence indicates that the processor is about to enter a high-intensity floating-point operation cycle, generating a heat flux density far exceeding that of steady-state conditions. Through this time-encoding method, the perception model transforms the originally lagging temperature values ​​into a predictive stream of pulse events.

[0021] The spiking neural network model constructed in step 1 was trained offline using a historical workload dataset. This dataset sampled instruction flow patterns from thousands of different application scenarios, recording typical working conditions including compilation tasks, graphics rendering, scientific computing, and daily office work. During training, the algorithm continuously optimized synaptic weights, enabling the model to accurately identify the causal relationship between different instruction flow combinations and subsequent measured temperature change rates. The training objective was to minimize the temporal deviation between the distribution of the predicted pulse sequence on the time axis and the peak value of the actual observed temperature change rate, ensuring that the pulse delivery precedes the actual heat accumulation process, allowing sufficient physical response time for subsequent regulation.

[0022] Step 2 establishes a thermodynamic entropy production assessment mechanism, which calculates the system entropy production rate per unit time in real time based on the current operating state of the central processing unit and the physical parameters of the heat dissipation system. The second law of thermodynamics states that during heat dissipation, energy dissipation is always accompanied by entropy generation, and the magnitude of the entropy production rate directly reflects the irreversibility and efficiency of the heat dissipation process. In this embodiment, the entropy production assessment mechanism abstracts the entire MODT system into a multi-level thermodynamic system, whose physical boundaries encompass the central processing unit chip core, thermal interface material, heat dissipation top cover, heat sink contact surface, and heat sink fins.

[0023] The entropy generation assessment mechanism comprehensively considers the heat conduction path within the central processing unit (CPU) chip. The system has a built-in calibration parameter library for different heat dissipation configurations. This library is initialized at the motherboard factory based on the matching heatsink model, the thermal conductivity of the thermal grease, and the internal airflow structure of the chassis. During operation, the entropy generation assessment mechanism derives the corresponding forced convection heat transfer coefficient by acquiring real-time fan speed. Subsequently, using the relationship between heat flux density and local temperature gradient, the mechanism calculates the entropy generation generated when heat passes through each interface level under the current power output. The entropy generation rate is defined as the integral of the product of heat flux and the square of the absolute temperature over the entire heat transfer path. When the temperature difference between interfaces is too large or the thermal resistance of the heat dissipation medium is too high, the entropy generation rate increases. This means that the proportion of electrical energy converted into effective computing power decreases, while the proportion converted into ineffective heat energy increases.

[0024] Step 3 involves setting an entropy production minimization control strategy. When the entropy production rate exceeds a preset threshold, a pulse-like control action of pre-cooling or early frequency reduction is triggered. The core of this strategy is to change the traditional passive logic of "reducing frequency after high temperature" and instead achieve energy efficiency optimization by minimizing the total entropy production of the system. When the spiking neural network in step 1 predicts an impending load surge, and the entropy production rate calculated in step 2 shows that the current heat dissipation path cannot efficiently handle the heat, the system no longer waits for the temperature to reach the critical point but immediately initiates intervention.

[0025] Specifically, the pre-cooling action is achieved by instantaneously increasing the drive current of the thermoelectric cooler (TEC). Unlike traditional constant drive, this embodiment applies a short-duration, high-amplitude current pulse. The duration of this current pulse is strictly controlled within a predetermined range of 10 to 50 milliseconds. This high-energy pulse can utilize the Peltier effect to generate an instantaneous extreme low temperature at the contact surface between the chip and the heat sink, forcibly breaking down the thermal boundary layer formed by the hysteresis of molecular thermal motion and reducing transient thermal resistance. This "thermal shock" can pre-activate the heat sink's heat absorption capacity, providing a greater heat dissipation margin for the upcoming high load. At the same time, if the temperature rise trend predicted by the spiking neural network is too drastic, the system will simultaneously execute an early frequency reduction action. The early frequency reduction action actively lowers the multiplier or voltage of the central processing unit several milliseconds before the actual temperature rise, reducing the rate of heat generation from the source, so that the system always operates in a high-efficiency range with low entropy production.

[0026] Step 4 introduces a biological rhythm simulation mechanism, implementing periodic oscillation control of the central processing unit's operating frequency by alternating between high and low frequencies within a millisecond-level time window. This mechanism draws inspiration from the principle that organisms accelerate heat dissipation through micro-oscillations of capillaries after strenuous exercise. At the frequency scheduling layer of the MODT motherboard, the system no longer maintains a constant operating frequency, but instead allows the frequency to rapidly switch between two states.

[0027] Specifically, the periodic oscillation control employs a frequency modulation method with a fixed period but a variable duty cycle. The oscillation period is typically set within a short range of 1 to 5 milliseconds, and this rapid switching is imperceptible to human vision and application monitoring at the operating system level. Within each cycle, the high-frequency band corresponds to the CPU's maximum turbo frequency to ensure the instantaneous responsiveness of computing tasks; the low-frequency band corresponds to the minimum stable frequency required to maintain basic computing tasks, allowing the core to "breathe" during short intervals and mitigating the accumulation of localized hotspots in the core caused by continuous current injection.

[0028] This oscillation control is directly scheduled at the motherboard firmware level at the microsecond level, without operating system intervention. The oscillation duty cycle is dynamically adjusted based on the current application load. For tasks requiring continuous peak output, such as graphics rendering or video transcoding, a high duty cycle mode is used, with 80% of the time spent in a high-frequency state; while for lightweight tasks such as background services and web browsing, a low duty cycle mode is used, with 20% of the time spent in a high-frequency state, maximizing energy efficiency by increasing the proportion of the low-frequency band.

[0029] Step 5 involves coordinating the pulsed regulation action with the periodic oscillation control within the power management unit of the central processing unit (PMU) to achieve a dynamic balance between temperature and performance. The PMU acts as the final actuator in the entire regulation system. It receives physical constraint instructions from the entropy production assessment module and performance prediction instructions from the spiking neural network model.

[0030] The power management unit (Power Management Unit) adjusts the supply voltage in response to the integrated digital voltage regulator (SVID interface). This adjustment has a response speed in the microsecond range, perfectly matching the frequency oscillation requirements in step 4. When the frequency switches to a higher frequency band, the voltage regulator synchronously increases the core voltage to maintain stability; when the frequency switches back to a lower frequency band, the voltage drops instantaneously to reduce leakage current power consumption. Simultaneously, the Power Management Unit coordinates the thermoelectric cooler drive circuit and the chassis fan control interface to form a closed-loop multi-physics coordinated control circuit. For example, when a TEC pulse is detected performing pre-cooling, the Power Management Unit temporarily suppresses drastic changes in fan speed to maintain stable airflow pressure using aerodynamic inertia. After pre-cooling is complete and heat is transferred to the fins, the fan speed is then increased to force heat dissipation.

[0031] During the construction of the perception model in step 1, the depth of the instruction issuance queue is obtained by reading the performance monitoring counter inside the processor. The counter samples every 100 microseconds, and the sampled data is transmitted in real time to the processing unit in the firmware via the motherboard's bus system. The perception model not only focuses on the absolute value of the queue depth but also on its differential changes over consecutive sampling periods. If the depth increment increases exponentially for three consecutive sampling periods, the neurons in the spiking neural network will directly enter an over-saturation activation state and issue the highest priority warning pulse.

[0032] Meanwhile, this embodiment also introduces an ambient temperature compensation mechanism for the system entropy production assessment in step 2. Through multiple thermistors deployed in different areas of the motherboard, the system can sense the temperature of the cold air entering the chassis in real time. If the ambient temperature is high, leading to a decrease in the heat exchange temperature difference between the heatsink and the air, the entropy production assessment mechanism will automatically adjust its internal nonlinear mapping coefficients, making the calculated entropy production rate more conservative and prompting the control action in step 3 to be triggered earlier. This adaptive correction process is continuously performed online, ensuring that the control scheme maintains consistent control accuracy in different seasons and geographical environments.

[0033] In step 4, the implementation details of the periodic oscillation control also involve the fast frequency locking technology of a hardware phase-locked loop (PLL). To achieve frequency switching at the millisecond or even microsecond level, the motherboard firmware communicates directly with the processor's clock generator, using multiple preset frequency configuration registers to achieve "seamless switching" between different frequency levels. During this switching process, the system performs voltage compensation in advance through a digital voltage regulator to ensure that there are no fluctuations in the logic threshold potential at the moment of high-frequency to low-frequency switching, thus preventing system crashes.

[0034] The synergistic effect in step 5 also includes the synchronous regulation of the processor's internal ring bus frequency. When the core operating frequency is in the high-frequency range of oscillation, the bandwidth of the ring bus is also increased synchronously to ensure that the core can access data in the L3 cache at the highest rate; while in the low-frequency range, the bus bandwidth shrinks accordingly, further reducing dynamic power consumption by lowering the signal toggle rate on the bus. This comprehensive synergy extends the regulation to the entire chip system.

[0035] The control method in this embodiment is fully integrated into the motherboard firmware's power management subsystem. This means that the method's execution priority is higher than the operating system's task scheduler and power management plan. The control mechanism is already operational during the BIOS boot phase before the operating system loads. This hardware-level implementation avoids control failures caused by operating system kernel delays or third-party driver interference, ensuring real-time temperature control and performance protection even when the system encounters high dynamic loads.

[0036] To more clearly demonstrate the operational logic of this embodiment, the following explanation uses specific typical application scenarios: Imagine a scenario where a user is rendering a high-resolution 4K video. At the instant rendering begins, the instruction stream characteristics change drastically. In step 1, the spiking neural network detects a surge in the instruction issuance queue depth from an average of 15 instructions per cycle to 45, and the L3 cache miss rate increases due to the influx of a large amount of texture data. At this moment, the model fires a series of high-frequency pulses. Step 2's entropy production evaluation mechanism, based on the current room temperature (25 degrees Celsius) and fan speed (1200 RPM), quickly calculates that maintaining the current performance output would result in a 3x increase in the entropy production rate of the cooling system.

[0037] Step 3 triggers a pre-cooling process, causing the TEC drive current to surge from 0 amps to 4 amps within 2 milliseconds, reducing the instantaneous thermal resistance of the chip surface by 40%. Simultaneously, Step 4 initiates a biorhythm oscillation, setting the core frequency to oscillate at 100Hz between 4.8GHz and 2.2GHz, with a duty cycle of 70%. In Step 5, the power management unit precisely coordinates with this oscillation process, providing a core voltage of 1.35 volts for the first 7 milliseconds of each 10-millisecond cycle, then rapidly dropping to 0.95 volts in the following 3 milliseconds.

[0038] Under this coordinated regulation, although the processor's peak frequency remains at a high level, the core temperature rise curve becomes gentler due to the introduction of low-frequency bands and the intervention of TEC pre-cooling.

[0039] Example 2: Building upon Example 1, Example 2 further enhances the intelligence and personalization of the control method. Particularly in adaptive calibration for different MODT hardware configurations, this example provides a complete calibration and self-learning mechanism.

[0040] In step 2, the calibration parameter library built into the thermodynamic entropy production assessment mechanism not only contains factory preset values ​​but also has an online correction function. During idle periods of system operation, the control method automatically executes a series of controlled "thermal probe" tests. The system periodically applies a known short-term constant load to the central processing unit and monitors the slope of the temperature rise curve and changes in fan speed. By comparing the measured thermal response curve with the theoretical model, the system can automatically infer whether the thermal grease has aged, whether dust has accumulated on the heat sink fins, or whether the chassis airflow is obstructed.

[0041] If the measured entropy production rate consistently exceeds the theoretical prediction, the adaptive algorithm will automatically increase the "thermal resistance deviation coefficient" in the calibration parameter library. This change in coefficient will directly make the threshold determination in step 3 more sensitive. For example, if thermal resistance increases due to thermal grease aging, the system will trigger pre-cooling earlier and appropriately reduce the high-frequency duty cycle in step 4 to compensate for the decrease in hardware heat dissipation capacity and ensure the reliability of the system after long-term use.

[0042] Furthermore, in step 1, this embodiment introduces application-aware feature extraction technology for the perceptual model of the spiking neural network. The perceptual model can identify the instruction fingerprint of specific software. For example, for heavy-load computing based on the AVX-512 instruction set, the heat distribution generated is significantly different from that of a typical SSE instruction set. When the model identifies this type of instruction flow, it outputs a tagged pulse sequence. This special pulse informs the power management unit in step 5 that fine-tuning of the voltage is needed for specific functional units of the processor, rather than simply uniformly reducing the frequency of the entire core.

[0043] In the circadian rhythm simulation in step 4, this embodiment adds asymmetric control of frequency oscillation. Unlike the fixed frequency switching in embodiment 1, this embodiment dynamically adjusts the transition slope between high and low frequencies based on the processor's real-time junction temperature. When the junction temperature is low, the frequency switching adopts a step-like approach to pursue the fastest performance response; when the junction temperature reaches a preset safety upper limit, the frequency switching introduces a smooth S-shaped curve transition. This asymmetric transition method can further reduce the inductive load impact caused by voltage transients, protect the power supply inductors and capacitors on the motherboard, and extend the hardware lifespan.

[0044] For MODT motherboards with hybrid characteristics of mobile and desktop platforms, this embodiment also implements a cross-protocol collaborative mechanism in step 5. Since MODT motherboards typically use mobile processors but are equipped with desktop power supply solutions, the system utilizes the large margin of desktop-level power supply to allow short-term current overload during pulse regulation in step 3. Specifically, the power management unit monitors the temperature of the VRM (voltage regulator module) in real time. As long as the VRM temperature is within a safe range, the PMU allows the TEC drive circuit to draw instantaneous current exceeding the normal rated value. This cross-protocol collaboration fully leverages the asymmetric advantages of the MODT platform's hardware configuration, maximizing the effect of pulse cooling.

[0045] This embodiment also details the loosely coupled interaction protocol between the control method and the operating system. Although the control is primarily performed by the firmware, the firmware transmits a virtual "thermal headroom" signal to the operating system via ACPI (Advanced Configuration and Power Interface). Based on this signal, the operating system can perform thread scheduling more intelligently. For example, when the firmware is performing high-frequency pulse pre-cooling, the signal informs the operating system that there is a large thermal headroom, and the operating system will prioritize scheduling computationally intensive threads to the kernel currently being pre-cooled. This firmware-led, system-cooperative hierarchical structure further improves the overall execution efficiency of multi-core processors.

[0046] At the data structure level, this embodiment defines a set of lightweight pulse event descriptors. Each pulse event consists of a 32-bit word, which includes a timestamp of pulse generation (occupying 16 bits), load intensity category (occupying 8 bits), and predicted temperature rise gradient level (occupying 8 bits). This compact data structure reduces the data communication latency between the spiking neural network and the power management unit to the nanosecond level, fully meeting the timeliness requirements of millisecond-level periodic oscillation control.

[0047] Example 3: This example focuses on the parallel regulation and optimization of the method of the present invention in an extreme multi-core environment, as well as the in-depth enhancement of security.

[0048] In modern MODT motherboards, the central processing unit (CPU) typically has multiple high-performance large cores and multiple energy-efficient small cores. The spiking neural network model in step 1 is extended to a distributed structure in this embodiment. Each physical core cluster has an independent sensing submodule. These submodules interact through a mechanism similar to neuron lateral inhibition. When a core cluster predicts impending thermal runaway, it sends an inhibition signal to neighboring core clusters, requesting them to actively lower their frequencies to create cooling space for the overheating clusters. This spatial dynamic coordination, combined with temporal pulse modulation, achieves global optimization of the heat flow distribution within the chip.

[0049] In the thermodynamic entropy production assessment in step 2, this embodiment introduces multi-point heat flow mapping technology. In addition to the main temperature sensor at the chip center, the system also utilizes auxiliary sensor data integrated into key components such as the memory controller and PCIe controller to construct a three-dimensional heat flow distribution map. The entropy production assessment not only calculates the overall entropy production rate but also identifies "entropy production hotspots" within the chip. For these hotspots, the pulsed control actions in step 3 are precisely targeted at the affected functional units. For example, if the entropy production hotspot is located near the memory controller, the system will trigger micro-pulse oscillations targeting the memory voltage and clock frequency, rather than blindly controlling the CPU core.

[0050] Regarding the periodic oscillation control in step 4, Example 3 proposes a spread spectrum modulation strategy. To avoid electromagnetic interference (EMI) generated by fixed-frequency oscillations, the length of the oscillation period is randomly perturbed within a preset small range. This pseudo-random frequency switching retains the heat dissipation advantages of biological rhythms while dispersing electromagnetic radiation energy over a wider frequency spectrum, ensuring that the MODT motherboard meets stringent electromagnetic compatibility standards during high-performance operation. This is particularly important for industrial or commercial workstation scenarios that prioritize stability.

[0051] In step 5, the power management unit's safety mechanism is enhanced. The system incorporates a hardware unit called a "thermal inertia predictor." This unit simulates the system's temperature trajectory over the next 100 milliseconds if the current control command fails. If the prediction indicates a risk of burnout, the predictor will forcibly override all software and firmware commands, directly cutting off the TEC pulse and forcing the processor into a hardware-level cooling mode. This "last line of defense" design ensures that even in extreme situations or algorithmic failures, expensive hardware assets are physically protected.

[0052] In terms of algorithm implementation, the neuron connection weights of the spiking neural network support remote evolution through firmware updates. Motherboard manufacturers can extract the load characteristics of new application software based on big data feedback from global users and issue new weight files. This means that this control method has the ability to learn and evolve throughout life, continuously optimizing its perception accuracy as the software ecosystem evolves.

[0053] This embodiment also details the fault-tolerant handling process for thermoelectric cooler (TEC) failure. During pulsed precooling in step 3, the power management unit monitors the current response of the TEC loop in real time. If the detected current waveform does not match the preset impedance model (e.g., open-circuit or short-circuit characteristics appear), the system immediately determines that the TEC has failed and quickly switches the control logic, shifting the focus to frequency oscillation in step 4 and early frequency reduction in step 3, while simultaneously issuing a hardware alarm to the operating system. This robust fault detection and logic switching mechanism ensures high system availability.

[0054] Regarding software interface interaction, this embodiment also provides a monitoring tool called "Entropy Production Dashboard". Although the regulation process is completed automatically at the firmware level, the monitoring tool can present abstract parameters such as entropy production rate, impulse sensing intensity, and circadian rhythm duty cycle to professional users in a visual manner. Users can switch between three preset modes, namely "ultra-quiet", "performance priority" or "energy efficiency balance", according to their preferences. Each mode essentially adjusts the combination of regulation parameters in steps 3 and 4, such as the threshold level or the bandwidth of the oscillation frequency.

[0055] Example 4: This example applies the method of the present invention to a specific high-performance miniaturized MODT host, detailing the deep coupling process between its hardware structure and software algorithm. In miniaturized hosts, heat dissipation space is limited, making traditional temperature control methods ineffective. This example demonstrates the unique advantages of pulse modulation.

[0056] At the hardware architecture level, the MODT motherboard integrates an actuator called "microchannel pulse liquid cooling," serving as the physical carrier for the control actions in steps 3 and 5. Unlike traditional circulating water cooling, the system embeds a miniature piezoelectric pump assembly inside the CPU cold head. The power management unit in step 5 directly drives these piezoelectric pumps.

[0057] When the spiking neural network in step 1 predicts an impending thermal shock, step 3 triggers not only electrical pre-cooling but also a "pulsed acceleration" of the liquid cooling cycle. The power management unit applies a high-voltage electrical pulse to the piezoelectric pump within microseconds, instantly increasing the coolant flow rate inside the cold head by five times. This fluid flow pulse rapidly removes the core heat generated by the sudden load, similar to the rapid pumping of blood by the heart in a biological circulatory system when startled.

[0058] In step 2, the entropy production assessment mechanism performs a specialized physical modeling for this type of microchannel liquid cooling. It incorporates the fluid's kinetic energy dissipation, the entropy increase caused by local turbulence, and the entropy production due to the temperature difference between the fluid and the wall into the computational framework. Through sophisticated algorithms, the system can calculate the most energy-efficient pumping frequency, enabling the cooling system to achieve the maximum entropy removal rate while consuming minimal pumping power.

[0059] The biorhythm simulation mechanism in step 4 has been given new meaning. The system discovered that when the frequency oscillation frequency matches the fluid resonant frequency of the liquid cooling system, the heat dissipation efficiency undergoes a nonlinear transition. Therefore, in this embodiment, the oscillation period is set to match the fluid standing wave frequency within the microchannel. This resonant synergy of "electro-thermal-mechanical" multiphysics fields enables a leap in the speed of heat transfer from the chip to the outside, increasing it by orders of magnitude.

[0060] In the closed-loop control of step 5, the power management unit introduces feedforward compensation control. Due to the mechanical inertia of the liquid cooling system's response (although the piezoelectric pump is fast, there is still a microsecond-level delay in fluid flow), the system sends an advanced pulse command to the piezoelectric pump simultaneously with the frequency oscillation command. This feedforward compensation ensures that when the CPU core frequency reaches its peak and heat generation is most intense, the coolant flows precisely through the core area.

[0061] This embodiment also addresses the need for quiet operation in miniaturized chassis by acoustically optimizing the oscillation parameters in step 4. By adjusting the rate of change of current (di / dt) during duty cycle switching, the system reduces the magnetostrictive noise generated by the power supply inductor during high-frequency oscillation, making the entire control process completely silent to the physical senses.

[0062] Example 5: This example mainly explores the performance of the method of the present invention in large-scale data processing and AI inference tasks on the MODT motherboard. In this application scenario, the workload is highly repeatable and predictable; therefore, this example makes targeted enhancements to steps 1 and 3.

[0063] In step 1, the spiking neural network introduces the characteristics of "long short-term memory" neurons. The perceptual model not only focuses on the current instruction stream pulses but also identifies the currently running task loop. For example, when the system detects a specific tensor computation instruction sequence, it can predict that this computation process will last for several minutes. Based on this long-term characteristic, the pulse sequence output by the model carries a "long-term flag".

[0064] Upon receiving a pulse with a flag, the control strategy in step 3 switches from "transient intervention" to "steady-state optimization mode." In this mode, the pre-cooling action is no longer sporadic pulses, but rather forms a sequence of energy injections with a specific envelope. The system pre-adjusts the physical state of the cooling system according to the inference rhythm of the AI ​​model.

[0065] In step 2, the entropy generation assessment mechanism adds monitoring of video memory and bus interfaces. Since AI inference involves a large amount of data exchange, the entropy generation generated by the bus cannot be ignored. The system acquires PCIe bus link utilization data and integrates it into the global entropy generation model. If excessive bus power consumption is detected leading to localized temperature rise, the system coordinates the frequency oscillation in step 4, proactively putting the CPU core into a low-power state during gaps in bus bandwidth constraints to avoid unnecessary energy waste.

[0066] To address the "burst" characteristic common in AI inference tasks (i.e., large-scale batch processing occurring at fixed intervals), the biorhythm simulation mechanism in step 4 achieves "phase alignment." The power management unit monitors the operating system's interrupt request signals, precisely aligning the high-frequency band of the frequency oscillation with the execution time of data batch processing, while aligning the low-frequency band with the idle times of data loading and preprocessing. This precise phase matching makes the CPU appear to follow the "breathing" rhythm of the load when executing tasks, maximizing the utilization of the heat sink's transient heat absorption capacity.

[0067] This embodiment also describes a calibration parameter library synchronization mechanism based on blockchain technology. Due to slight process differences between different MODT motherboards during production, by encrypting and uploading the optimal entropy production evaluation parameters learned by each motherboard during actual operation to a private cloud, the system can continuously optimize the control parameters of all motherboards of the same model using collective intelligence. Upon startup, each motherboard downloads the parameter package most suitable for its current hardware wear state from the library, achieving "lifetime preservation" of hardware performance.

[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0069] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for coordinated temperature and performance control of a MODT motherboard central processing unit, characterized in that, Includes the following steps: A computational load awareness model based on a spiking neural network is constructed to transform the instruction flow characteristics of the central processing unit core into a time-coded pulse sequence to characterize the dynamic trend of the temperature change rate. Establish a thermodynamic entropy production assessment mechanism to calculate the system's entropy production rate per unit time in real time based on the current working state of the central processing unit and the physical parameters of the heat dissipation system. A strategy for minimizing entropy production is set up. When the entropy production rate exceeds a preset threshold, a pulse-type control action of pre-cooling or early frequency reduction is triggered. A biological rhythm simulation mechanism is introduced to implement periodic oscillation control of the central processing unit's operating frequency, alternating between high and low frequencies, within a millisecond-level time window; The pulsed regulation action and periodic oscillation control are combined and applied to the power management unit of the central processing unit to achieve a dynamic balance between temperature and performance.

2. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 1, characterized in that, The construction of the computational load perception model based on the spiking neural network includes: The physical core of the central processing unit is mapped to a basic neuron unit in a spiking neural network; The microarchitectural features of the central processing unit are obtained by using performance monitoring counters. These microarchitectural features include instruction issue queue depth, cache hit rate, and branch prediction failure rate. The instruction issue queue depth, cache hit rate, and branch prediction failure rate are integrated using a nonlinear fusion operator to form a continuous state vector reflecting the current computing intensity of the central processing unit. The perception model uses leakage current integration triggering logic to transform the continuous state vector into pulse events with discrete characteristics. When the increment of the instruction emission queue depth during the sampling period shows an exponential upward trend and the accumulated potential exceeds the preset dynamic threshold, the neuron unit fires a time-domain pulse. The arrangement density and frequency of the pulse sequence characterize the temperature rise rate trend of the central processing unit core within a preset millisecond time period, transforming the lagging temperature values ​​into a predictable pulse event stream.

3. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 2, characterized in that, The establishment of the thermodynamic entropy production assessment mechanism includes: The central processing unit, thermal interface material, thermal dispersion top cover, heat sink contact surface and heat sink fins are abstracted into a multi-level thermodynamic physical system; Obtain the calibration parameter library built into the motherboard firmware. The calibration parameter library is initialized according to the heatsink model, thermal conductivity and airflow structure inside the chassis. The forced convection heat transfer coefficient is derived by real-time fan speed, and the entropy production generated when heat passes through the interfaces of each level of the multi-level thermodynamic physical system is calculated by using the relationship between heat flux density and local temperature gradient. The entropy production rate is defined as the product of the ratio of heat flow to the square of absolute temperature, and is integrated over the entire heat transfer path to reflect the relationship between the proportion of electrical energy converted into effective computational power consumption and the proportion converted into ineffective heat energy. An ambient temperature compensation logic is introduced. By using thermistors placed in different areas of the motherboard to sense the ambient temperature, when the ambient temperature rises and the heat dissipation temperature difference decreases, the nonlinear mapping coefficient is automatically adjusted so that the calculated entropy production rate tends to be conservative, triggering a control action.

4. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 3, characterized in that, The pulse-type control action that triggers pre-cooling or early frequency reduction includes: When the perception model predicts an impending load surge and the entropy production rate indicates that the current heat dissipation path cannot efficiently handle the heat, intervention is initiated before the temperature reaches the critical point. The precooling action is achieved by instantaneously increasing the driving current of the thermoelectric cooler, applying a short-duration, high-amplitude current pulse to the thermoelectric cooler, and the duration of the current pulse is controlled within a predetermined range of milliseconds; The Peltier effect generated by the current pulse produces an instantaneous low temperature at the contact surface between the central processing unit and the heat sink, thereby breaking down the thermal boundary layer formed by the hysteresis of molecular thermal motion, reducing transient thermal resistance and stimulating the heat sink's heat absorption capacity. The pre-frequency reduction action, based on the prediction results of the pulse neural network, actively reduces the frequency multiplier or power supply voltage of the central processing unit within a preset lead time before the actual temperature rises, thereby reducing the rate of heat generation.

5. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 4, characterized in that, The introduced biological rhythm simulation mechanism includes: The frequency scheduling layer enables the central processing unit to switch its operating frequency rapidly between two states, and the periodic oscillation control adopts a frequency modulation method with a fixed period and duty cycle. The oscillation period of the periodic oscillation control is set in the range of milliseconds, and within each period, the high frequency band corresponds to the maximum turbo frequency of the central processing unit, and the low frequency band corresponds to the minimum stable frequency required to maintain basic computing tasks. The switching process between the high-frequency band and the low-frequency band is directly scheduled by the motherboard firmware layer, and the duty cycle is dynamically adjusted according to the application load type. For sustained peak tasks such as graphics rendering or video processing, a high duty cycle mode is used to increase the duration of the high-frequency band. For background services or lightweight tasks, a low duty cycle mode is used to increase the proportion of the low frequency band and mitigate the accumulation of local hot spots in the kernel caused by continuous current injection.

6. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 5, characterized in that, The power management unit that works in conjunction with the central processing unit includes: The power management unit, acting as an actuator, receives physical constraint instructions from the entropy production assessment mechanism and performance prediction instructions from the perception model. The power management unit adjusts the supply voltage in response to the integrated digital voltage regulator to match the frequency switching requirements of the periodic oscillation control. When the frequency is switched to the higher frequency band, the digital voltage regulator synchronously increases the core voltage to maintain the stability of the logic threshold potential; When the frequency is switched to the low frequency band, the core voltage drops synchronously to reduce leakage current power consumption; The power management unit synchronously coordinates the drive circuit of the thermoelectric cooler with the chassis fan control interface to form a closed-loop multi-physics field collaborative control circuit. During the pre-cooling process, the power management unit suppresses drastic changes in fan speed, maintains stable airflow pressure using aerodynamic inertia, and then increases the fan speed to force heat dissipation after heat has been transferred to the heat sink fins.

7. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 6, characterized in that, The perception model is trained offline using historical workload datasets during the training phase. The historical load dataset covers command flow patterns and corresponding temperature response curves under different application scenarios; By optimizing synaptic weights, the causal relationship between different command flow combinations and subsequent measured temperature change rates is identified, enabling pulse delivery to precede the actual heat accumulation process. The perception model identifies instruction fingerprints and outputs a marked pulse sequence to inform the power management unit to perform local fine-tuning of the voltage of the processor's floating-point arithmetic unit. The spiking neural network communicates with the power management unit via a lightweight pulse event descriptor, which includes a timestamp of pulse generation, load intensity category, and predicted temperature rise gradient level to reduce data communication latency.

8. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 7, characterized in that, The calibration parameter library has an online correction function, specifically including: During idle periods of system operation, thermal probe tests are automatically performed, which involve applying a known short-term constant load to the central processing unit to monitor the slope of the temperature rise curve and changes in fan speed. By comparing the measured thermal response curves with the theoretical model, we can infer the aging state of the thermal grease, the dust accumulation state of the heat sink fins, and the obstruction state of the chassis airflow. When the measured entropy production rate is consistently higher than the theoretical prediction, the adaptive algorithm increases the thermal resistance deviation coefficient in the calibration parameter library to improve the sensitivity of the threshold determination in the entropy production minimization control strategy.

9. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 8, characterized in that, The periodic oscillation control also includes frequency transition optimization and bus coordination logic: By utilizing the fast frequency locking technology of hardware phase-locked loop, and through the preset of multiple sets of frequency configuration registers, the switching between different frequency levels can be realized; Based on the real-time junction temperature of the central processing unit, the transition slope between the high-frequency band and the low-frequency band is dynamically adjusted. When the junction temperature reaches the safe upper limit, a smooth curve transition is introduced to reduce the inductive load impact caused by voltage transients. The frequency of the ring bus inside the central processing unit is synchronously adjusted. When the core operating frequency is in the high-frequency range, the ring bus bandwidth is synchronously increased. When in the low-frequency band, the bus bandwidth is reduced and the signal toggle rate is decreased, thereby reducing dynamic power consumption.

10. The method for coordinated temperature and performance control of the MODT motherboard central processing unit according to claim 9, characterized in that, The synergistic effect also includes parallel regulation optimization and security assurance: For processors with multiple physical core clusters, a distributed perception submodule is adopted, and the submodules interact with each other through a neuron lateral inhibition mechanism. When a core cluster predicts that thermal runaway is about to occur, it sends a suppression signal to the neighboring core clusters, requesting the neighboring clusters to reduce their frequency to free up heat dissipation space. The power management unit has a built-in thermal inertia predictor that simulates the future temperature trend after the control command fails in real time. If the prediction result shows that there is a risk of exceeding the physical tolerance limit, the control command will be forcibly overridden and the unit will enter the hardware-level cooling mode. The control method is integrated into the power management subsystem of the motherboard firmware. Its execution priority is higher than that of the operating system's task scheduler, and it is already in operation during the boot phase before the operating system loads.

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