Manufacturing method of three-dimensional system chip based on metal bump interconnection
By forming a redistribution metal pillar structure between the mother core structure and the daughter core and growing interconnect metal bodies in situ, the problems of difficult heat dissipation and low integration in existing packaging technologies are solved, and efficient three-dimensional system-on-a-chip manufacturing is realized.
Patent Information
- Application Number
- CN202610065572.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-16
- Publication Date
- 2026-05-01
AI Technical Summary
Existing packaging technologies are difficult to effectively dissipate heat from high-power chips, and require high bonding alignment accuracy and bump coplanarity. Traditional interconnect and thermal conductivity structures have low integration and complex manufacturing processes.
The system employs a vertical interconnection method between a mother core structure and daughter core particles. By forming redistribution metal pillar structures on the surfaces of the mother core structure and daughter core particles, and growing interconnect metal bodies in situ after bonding, three-dimensional flexible wiring is achieved using the metal pillars and redistribution layers. Combined with chemical plating, a low-resistance and high-reliability interconnect is formed.
It improves interconnect flexibility and integration density, reduces thermal stress, ensures electrical performance and reliability, and achieves efficient heat dissipation and signal transmission.
Smart Images
Figure CN121969201A_ABST
Abstract
Description
Manufacturing method of 3D system-on-a-chip based on metal bump interconnect Technical Field
[0001] This invention relates to the field of semiconductor packaging and integration, and more specifically to a method for manufacturing a three-dimensional system chip based on metal bump interconnects. Background Technology
[0002] With the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink, and the requirements for integrated circuit packaging technology are also constantly increasing. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), 3D packaging, and system in package (SiP).
[0003] As Moore's Law slows down, the three-dimensional integration of chips with different process nodes and functions through advanced packaging technology has become the mainstream direction for improving system performance.
[0004] Existing technologies, such as wafer-level fan-out packaging or microbump-based chip bonding technology, can achieve high-density interconnects, but face the following challenges: the interconnect and heat dissipation paths are separated, and the heat generated by high-power chips is difficult to be effectively dissipated through the interconnect structure, resulting in a thermal bottleneck; after bonding alignment, bump connections are formed by reflow soldering, which requires extremely high bonding alignment accuracy and bump coplanarity, and the reflow process may introduce thermal stress; 3) traditional metal pillars or bumps are used as interconnect and heat conduction structures, and the materials and processes of the two are usually separate, resulting in low integration and complex processes. Summary of the Invention
[0005] To address the above problems, this invention provides a three-dimensional system-on-a-chip (SoC) based on metal bump interconnects, comprising: a mother core structure having a first original pad array on its surface; at least one daughter core stacked upside down on the mother core structure, having a second original pad array on its surface; a redistribution metal pillar structure disposed on the surface of the mother core structure and / or the daughter core, the redistribution metal pillar structure comprising: a redistribution layer electrically connected to the first original pad array and / or the second original pad array; a dielectric layer formed on the redistribution layer; and metal pillars penetrating the dielectric layer and electrically connected to the redistribution layer below it; wherein the metal pillars or the first original pad array on the surface of the mother core structure are perpendicularly opposite to the metal pillars or the second original pad array on the surface of the daughter core; and an interconnecting metal body filling the gap between the perpendicularly opposite metal pillars or the gap between the metal pillars and the first / second original pad arrays, and fused with the metal pillars, the interconnecting metal body being a metal structure grown in situ in the gap after the mother core structure and the daughter core are bonded.
[0006] Optionally, the rewiring metal pillar structure is disposed only on the surface of the core structure.
[0007] Optionally, the redistribution metal pillar structure is disposed only on the surface of the sub-core.
[0008] Optionally, the redistribution metal pillar structure is disposed on the surface of both the parent core structure and the daughter core.
[0009] Optionally, the metal column has a size of 0.5um to 50um and a height of 0.2um to 15um.
[0010] Optionally, the core structure includes a carrier substrate and at least two core particles bonded thereto.
[0011] Optionally, the redistribution layers on the surfaces of the at least two mother cores are configured to direct signals from different mother cores to different metal pillars perpendicular to the same sub-core.
[0012] Optionally, the number of sub-cores is at least two, and the redistribution layer is further configured to enable a signal from one of the mother cores to be electrically connected to at least two of the sub-cores via metal pillars and interconnecting metal bodies on its surface.
[0013] Optionally, the in-situ grown metal structure is formed by, but not limited to, electroless plating, electroplating, or chemical vapor deposition processes.
[0014] Optionally, the metal column is made of copper, aluminum, tungsten, nickel, gold, cobalt, or an alloy thereof.
[0015] A method for manufacturing a three-dimensional system-on-a-chip based on metal bump interconnects includes the following steps: S10: providing a mother die structure having a first original pad array on its surface; providing at least one daughter die having a second original pad array on its surface; S20: forming a redistribution metal pillar structure on the surface of the mother die structure and / or the daughter die; S30: inverting the daughter die and aligning it with the mother die structure, and bonding it using a bonding material, wherein the bonding material is located outside the metal pillar region, such that the metal pillars or the first original pad array on the surface of the mother die structure are perpendicularly opposite to the metal pillars or the second original pad array on the surface of the daughter die, and a reserved cavity is formed therebetween; S40: selectively growing metal through the reserved cavity into the perpendicularly opposite surfaces or the surfaces of the metal pillars and the first / second original pad arrays, until the grown metal is connected as one in the reserved cavity to form an interconnect metal body, thereby completing the vertical electrical interconnect between the mother die structure and the daughter die.
[0016] Optionally, step S20 includes: forming a redistribution layer electrically connected to the first original pad array and / or the second original pad array; forming a dielectric layer on the redistribution layer; forming an opening in the dielectric layer to expose the underlying redistribution layer; filling the opening with metal, and forming a metal pillar by CMP or etching, leaving only the metal filling the opening; and etching the dielectric layer around the location of the metal pillar to expose the metal pillar.
[0017] Optionally, step S20 further includes: forming a redistribution layer electrically connected to the first original pad array and / or the second original pad array; forming a dielectric layer on the redistribution layer; forming an opening in the dielectric layer to expose the underlying redistribution layer; growing a metal layer and etching the metal to form metal pillars.
[0018] Optionally, in step S20, the redistribution metal pillar structure is formed only on the surface of the core structure.
[0019] Optionally, in step S20, the redistribution metal pillar structure is formed only on the surface of the sub-core.
[0020] Optionally, in step S20, the redistribution metal pillar structure is formed simultaneously on the surfaces of the mother core structure and the daughter core.
[0021] Optionally, in step S10, providing the core structure includes: providing a carrier substrate and bonding at least two core particles to the carrier substrate to form the core structure.
[0022] Optionally, the core structure includes at least two core particles bonded to a carrier substrate; when forming the redistribution layer, its routing pattern is configured such that signals from different core particles are directed to different metal pillars perpendicular to the same sub-core particle.
[0023] Optionally, the number of sub-cores provided in step S10 is at least two; when forming the redistribution layer, its routing pattern is further configured so that the signal of one of the mother cores can be guided to a metal pillar perpendicular to at least two of the sub-cores.
[0024] The present invention has at least the following beneficial effects: high interconnect flexibility: the redistribution layer (RDL) enables the free redistribution of signals in a two-dimensional plane. Combined with vertical metal pillars and post-growth interconnects, it realizes true three-dimensional flexible wiring, which is particularly suitable for multi-core heterogeneous integration.
[0025] Good process compatibility: The "bonding before growth" interconnect formation method avoids secondary thermal shock to the already bonded structure caused by high-temperature reflow or hot-press bonding, reducing thermal stress and improving reliability. The chemical plating process causes minimal damage to the underlying structure.
[0026] Excellent electrical performance: The integrated interconnect metal body has no intermediate interface and low resistance. By using pre-fabricated metal pillars as a seed layer, the uniformity and controllability of chemical plating initiation and growth are ensured, improving the consistency and yield of interconnects.
[0027] High integration density: The metal pillars can be made smaller and more closely spaced, and the redistribution layer can make full use of the space above the core gaps for routing, improving space utilization. Attached Figure Description
[0028] Figure 1 is a cross-sectional schematic diagram of a three-dimensional system chip based on metal bump interconnect according to the first embodiment of the present invention; Figures 2-4 are schematic diagrams of the process steps for forming a three-dimensional system chip in the structure shown in Figure 1; Figure 5 is a cross-sectional schematic diagram of the manufacturing of a multi-chip cross-interconnect system according to the second embodiment of the present invention; Figure 6 is a flowchart of the manufacturing method of a three-dimensional system chip based on metal bump interconnect according to the present invention.
[0029] Reference numerals: 10-mother core structure; 11-first original pad array; 13-carrier substrate; 14-first mother core; 15-second mother core; 20-sub-core; 21-second original pad array; 30-rewiring metal pillar structure; 31-rewiring layer; 32-dielectric layer; 33-metal pillar; 40-interconnect metal body; 50-bonding material; 2a-first sub-core; 2b-second sub-core. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples
[0031] As shown in Figure 1, this embodiment provides a three-dimensional system-on-a-chip (SoC) based on metal bump interconnect, comprising: a mother die structure 10 having a first original pad array 11 on its surface; at least one daughter die 20, stacked upside down on the mother die structure 10, having a second original pad array 21 on its surface; a redistribution metal pillar structure 30 disposed on the surface of the mother die structure 10 and / or the daughter die 20, the redistribution metal pillar structure 30 comprising: a redistribution layer 31 electrically connected to the first original pad array 11 and / or the second original pad array 21; a dielectric layer 32 formed on the redistribution layer 31; and a through-hole layer 32. The dielectric layer 32 is electrically connected to the redistribution layer 31 below it by metal pillars 33; wherein, the metal pillars 33 or the first original pad array 11 on the surface of the mother core structure 10 are perpendicular to the metal pillars 33 or the second original pad array 21 on the surface of the daughter core 20; the interconnect metal body 40 fills the gap between the perpendicularly opposite metal pillars 33 or between the metal pillars 33 and the first original pad array 11 / second original pad array 21, and is fused with the metal pillars 33 as one unit. The interconnect metal body 40 is a metal structure that is grown in situ in the gap after the mother core structure 10 and the daughter core 20 are bonded.
[0032] Specifically, the metal pillars 33 or the first original pad array 11 on the surface of the mother core structure 10 are perpendicular to the metal pillars 33 or the second original pad array 21 on the surface of the daughter core 20; the interconnecting metal body 40 fills the gap between the perpendicularly opposite metal pillars 33 or between the metal pillars 33 and the first original pad array 11 / second original pad array 21, and is fused with the metal pillars 33. The interconnecting metal body 40 is a metal structure that is grown in situ in the gap after the mother core structure 10 and the daughter core 20 are bonded. In different embodiments, the redistribution metal pillar structure 30 can be formed only on the surface of the parent core structure 10, or it can be formed on the surface of the daughter core 20. Because the metal pillars 33 are formed, the interconnect interface presents two forms during bonding: one is that the metal pillars 33 formed on both sides face each other; the other is that a metal pillar 33 formed on one side faces the original pad on the other side. The material of the metal pillars 33 is copper, aluminum, tungsten, nickel, gold, cobalt, or their alloys. The parent core structure 10 can be a carrier wafer (such as a silicon wafer), an interposer, or a partially integrated system wafer. The first original pad array 11 on its surface is generally made of aluminum or copper. The core chip 20 is the interface between the internal circuitry and the external interconnection. The sub-core chip 20 is the functional core chip to be integrated, such as a processor, memory, or RF module. It is stacked on the parent core structure 10 in a flip-chip manner and has a second original pad array 21 on its surface. It is worth noting the redistribution metal pillar structure 30, as shown in Figures 1, 2, and 3. The redistribution metal pillar structure 30 is disposed on the surface of the parent core structure 10. In other embodiments, it can also be disposed on the surface of the sub-core chip 20, or simultaneously on the surfaces of the parent core structure 10 and the sub-core chip 20. It effectively improves the efficiency and forming quality of the subsequent chemical plating growth of the interconnect metal body 40 by utilizing the metal pillars 33 formed after redistribution.
[0033] This embodiment describes in detail a method for manufacturing a three-dimensional system-on-a-chip based on metal bump interconnects.
[0034] As shown in Figure 6, the manufacturing method mainly includes the following steps: S10: providing a mother core structure 10, the surface of which has a first original pad array 11; providing at least one sub-core 20, the surface of which has a second original pad array 21; in this embodiment, the mother core structure 10 is a silicon-based carrier wafer with a thickness of 775μm; through standard integrated circuit manufacturing process, a first original pad array 11 composed of aluminum-copper alloy (Al-0.5%Cu) is formed on its upper surface, the pad size is 80μm x 80μm, and the pitch is 150μm; a first passivation layer composed of silicon nitride / silicon dioxide stack is covered on the first original pad array 11; the sub-core 20 is a core that has completed front-end device manufacturing and back-end interconnection, with a thickness of 200μm, and its surface also has a second original pad array 21 composed of aluminum.
[0035] S20: A redistribution metal pillar structure 30 is formed on the surface of the mother core structure 10 and / or the daughter core 20; the formation process includes: forming a redistribution layer 31 electrically connected to the first original pad array 11 and / or the second original pad array 21; forming a dielectric layer 32 on the redistribution layer 31; forming an opening in the dielectric layer 32 to expose the underlying redistribution layer 31; filling the opening with metal, and retaining only the metal filling the opening after CMP or etching to form a metal pillar 33; etching the dielectric layer 32 around the location of the metal pillar 33 to expose the metal pillar 33.
[0036] Step S20 further includes: forming a redistribution layer 31 electrically connected to the first original pad array 11 and / or the second original pad array 21; forming a dielectric layer 32 on the redistribution layer 31; forming an opening in the dielectric layer 32 to expose the underlying redistribution layer 31; growing a metal layer and etching the metal to form metal pillars 33.
[0037] Specifically, as shown in Figure 2, an insulating dielectric (such as SiO2 or polymer) is deposited on the surface of the core structure 10 as a first passivation layer (not shown), and the first original solder pad is exposed by photolithography and etching to form a redistribution layer 31 (RDL). First, a seed layer (such as Ti / Cu) is deposited, then a pattern is formed by photolithography, a thickened copper layer is electroplated to form a conductor, and finally the photoresist and the seed layer are removed and etched. The redistribution layer 31 is electrically connected to the first original solder pad and its signal is rerouted to a new position that is more suitable for vertical stacking.
[0038] As shown in Figure 3, a dielectric layer 32 is formed on the redistribution layer 31 and cured. The dielectric layer 32 can be spin-coated polyimide (PI) or benzocyclobutene (BCB). Openings are formed in the dielectric layer 32 by photolithography and etching, exposing the underlying redistribution layer 31. Subsequently, metal is filled into the openings, for example by electroplating copper, to form metal pillars 33. The height of the metal pillars 33 is 5 μm to 50 μm, and the diameter is 2 μm to 20 μm. After completion, chemical mechanical polishing (CMP) can be performed to planarize the surface.
[0039] This step forms a core innovative structure—the "rewiring metal pillar 33 structure"—on the surface of the parent core structure 10. This structure provides an optimized interface for subsequent "bonding-then-growth" interconnect processes. In other embodiments, the sub-core 20 can undergo similar processing as needed, forming the same structure on its surface, including the redistribution layer 31, the dielectric layer 32, and the metal pillars 33.
[0040] S30: The sub-core 20 is inverted and aligned with the mother core structure 10, and bonded using bonding material 50, wherein the bonding material 50 is located outside the area of the metal pillar 33, such that the metal pillar 33 or the first original pad array 11 on the surface of the mother core structure 10 is perpendicular to the metal pillar 33 or the second original pad array 21 on the surface of the sub-core 20, and a reserved cavity is formed therebetween.
[0041] As shown in Figure 4, the sub-core 20 is inverted and aligned with the parent core structure 10, and bonded using a bonding material 50, such as a thermosetting polymer dry film or bonding adhesive. The bonding material 50 is patterned (e.g., by creating windows in the bonding adhesive layer through photolithography-etching, or by using a pre-fabricated dry film with openings) to precisely position it in the peripheral region outside the area of the metal pillar 33. After bonding, the metal pillar 33 on the parent core structure 10 is perpendicularly aligned with the second original pad array 21 on the sub-core 20, forming a reserved cavity between them. The height of this cavity is approximately equal to the thickness of the bonding material 50 minus the height of the metal pillar 33, approximately 5 μm.
[0042] S40: Through the reserved cavity, metal is selectively grown onto the surfaces of the vertically opposite metal pillars 33 and the first original pad array 11 / second original pad array 21 until the grown metal is connected as one in the reserved cavity to form an interconnected metal body 40, thereby completing the vertical electrical interconnection between the mother core structure 10 and the daughter core 20.
[0043] As shown in Figure 1, in-situ growth of the interconnect metal body 40 is performed. A chemical plating solution, such as a copper plating solution, is introduced through a pre-reserved cavity or a microchannel connected to it. In this embodiment, metal ions are selectively reduced and deposited on the top surfaces of the vertically opposite metal pillars 33 and the second original pad array 21. The metal grows simultaneously from both sides, eventually meeting and fusing together in the middle of the pre-reserved cavity to form the interconnect metal body 40. This interconnect metal body 40 is electrically interconnected with the upper second original pad array 21 and the lower metal pillar 33, achieving a low-resistance, highly reliable electrical connection.
[0044] In one embodiment, metal ions are selectively reduced and deposited on the top surfaces of the vertically opposed metal pillars 33. The metal grows simultaneously from both sides and eventually meets and fuses in the middle of the reserved cavity to form an interconnecting metal body 40. This interconnecting metal body 40 is electrically interconnected with the upper and lower metal pillars 33, achieving a low-resistance, highly reliable electrical connection.
[0045] Second embodiment: The fabrication of the multi-core cross-connect system is shown in FIG5. The mother core structure 10 includes a carrier substrate 13 and a first mother core 14 and a second mother core 15 bonded thereon. The sub-cores 20 include a first sub-core 2a and a second sub-core 2b stacked on top of each other.
[0046] In the manufacturing of this system, the original pad layout cannot meet the complex interconnection requirements. The redistribution metal pillar structure 30 described in this invention enables flexible cross-interconnection: the redistribution layer 31 formed on the surface of the first mother core 14 guides some of its signals (such as data buses) to the metal pillar 33 perpendicular to the first sub-core 2a, while guiding another part of the signals (such as control signals) to the metal pillar 33 perpendicular to the second sub-core 2b.
[0047] Similarly, the signal of the second mother core 15 is also guided through the redistribution layer 31 on its surface to the metal pillars 33 connected to the first sub-core 2a and the second sub-core 2b, respectively.
[0048] Metal ions are selectively reduced and deposited on the top surfaces of the vertically opposed metal pillars 33. The metal grows simultaneously from both sides and eventually meets and fuses in the middle of the reserved cavity to form an interconnecting metal body 40. This interconnecting metal body 40 is electrically interconnected with the upper and lower metal pillars 33.
[0049] After bonding and growing the interconnect metal body 40, a highly integrated three-dimensional system is formed, realizing a flexible and configurable signal interconnection network between the first mother core 14, the second mother core 15, and the first daughter core 2a and the second daughter core 2b. The first mother core 14 can communicate with the first daughter core 2a and the second daughter core 2b through the interconnect metal body 40; the second mother core 15 can also communicate with the first daughter core 2a and the second daughter core 2b through another interconnect metal body 40. This achieves signal redistribution in the two-dimensional plane, through the RDL (Redistribution Layer 31) and its extension in the three-dimensional direction, and through the perfect combination of the metal pillars 33 and the post-grown interconnects.
[0050] Subsequently, the first sub-core 2a and the second sub-core 2b can be stacked sequentially. For each stack, the "alignment-bonding to form a cavity-chemical plating to grow interconnects" process, similar to S30 and S40 in the first embodiment, is repeated. When all stacking and interconnection are completed, a highly integrated three-dimensional system is formed.
[0051] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A three-dimensional system-on-a-chip based on metal bump interconnect, characterized in that, include: A mother core structure having a first original pad array on its surface; at least one daughter core, stacked upside down on the mother core structure, having a second original pad array on its surface; A redistribution metal pillar structure is disposed on the surface of the parent core structure and / or the daughter core. The redistribution metal pillar structure includes: a redistribution layer electrically connected to the first original pad array and / or the second original pad array; a dielectric layer formed on the redistribution layer; and metal pillars penetrating the dielectric layer and electrically connected to the redistribution layer below it. The metal pillars or the first original pad array on the surface of the parent core structure are perpendicularly opposite to the metal pillars or the second original pad array on the surface of the daughter core. An interconnecting metal body fills the gap between the perpendicularly opposite metal pillars or the metal pillars and the first / second original pad arrays, and is fused to the metal pillars. The interconnecting metal body is a metal structure grown in situ in the gap after the parent core structure and the daughter core are bonded.
2. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The rewiring metal pillar structure is only disposed on the surface of the core structure.
3. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The redistribution metal pillar structure is only disposed on the surface of the sub-core.
4. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The redistribution metal pillar structure is disposed on the surface of both the parent core structure and the daughter core.
5. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The metal column has a size of 0.5um to 50um and a height of 0.2um to 15um.
6. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The core structure includes a carrier substrate and at least two core particles bonded thereto.
7. The three-dimensional system-on-a-chip as described in claim 6, characterized in that, The redistribution layers on the surfaces of the at least two mother cores are configured to direct signals from different mother cores to different metal pillars perpendicular to the same sub-core.
8. The three-dimensional system-on-a-chip as described in claim 6 or 7, characterized in that, The number of sub-cores is at least two, and the redistribution layer is further configured such that a signal from one of the mother cores can be electrically connected to at least two of the sub-cores via metal pillars and interconnecting metal bodies on its surface.
9. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The in-situ grown metal structure is formed by, but is not limited to, electroless plating, electroplating, or chemical vapor deposition processes.
10. The three-dimensional system-on-a-chip as described in claim 1, characterized in that, The metal pillar is made of copper, aluminum, tungsten, nickel, gold, cobalt, or alloys thereof.
11. A method for manufacturing a three-dimensional system-on-a-chip based on metal bump interconnects, characterized in that, The steps include: S10: providing a core structure having a first original pad array on its surface; providing at least one daughter core having a second original pad array on its surface; S20: forming a redistribution metal pillar structure on the surface of the core structure and / or the daughter core; S30: inverting the daughter core and aligning it with the core structure, and bonding it using a bonding material, wherein the bonding material is located outside the metal pillar region, such that the metal pillars or the first original pad array on the surface of the core structure are perpendicularly opposite to the metal pillars or the second original pad array on the surface of the daughter core, and a reserved cavity is formed therebetween; S40: Through the reserved cavity, metal is selectively grown onto the vertically opposite metal pillars or the surfaces of the first original pad array / second original pad array until the grown metal is connected as one in the reserved cavity to form an interconnected metal body, thereby completing the vertical electrical interconnection between the mother core structure and the daughter core.
12. The manufacturing method as described in claim 11, characterized in that, Step S20 includes: forming a redistribution layer electrically connected to the first original pad array and / or the second original pad array; forming a dielectric layer on the redistribution layer; forming an opening in the dielectric layer to expose the underlying redistribution layer; filling the opening with metal, and forming a metal pillar by CMP or etching, leaving only the metal filling the opening; and etching the dielectric layer around the location of the metal pillar to expose the metal pillar.
13. The manufacturing method as described in claim 11, characterized in that, Step S20 further includes: forming a redistribution layer electrically connected to the first original pad array and / or the second original pad array; forming a dielectric layer on the redistribution layer; forming an opening in the dielectric layer to expose the underlying redistribution layer; growing a metal layer and etching the metal to form metal pillars.
14. The manufacturing method as described in claim 11, characterized in that, In step S20, the redistribution metal pillar structure is formed only on the surface of the core structure.
15. The manufacturing method as described in claim 11, characterized in that, In step S20, the redistribution metal pillar structure is formed only on the surface of the sub-core.
16. The manufacturing method as described in claim 11, characterized in that, In step S20, the redistribution metal pillar structure is formed simultaneously on the surfaces of the mother core structure and the daughter core.
17. The manufacturing method as described in claim 11, characterized in that, In step S10, providing the core structure includes: providing a carrier substrate and bonding at least two core particles to the carrier substrate to form the core structure.
18. The manufacturing method as described in claim 12, characterized in that, The core structure includes at least two core particles bonded to a carrier substrate; when forming the redistribution layer, its routing pattern is configured such that signals from different core particles are directed to different metal pillars perpendicular to the same sub-core particle.
19. The manufacturing method as described in claim 12, characterized in that, The number of sub-cores provided in step S10 is at least two; when forming the redistribution layer, its routing pattern is further configured so that the signal of one of the mother cores can be guided to a metal pillar perpendicular to at least two of the sub-cores.