A quantum chiplet communication system based on enhanced quantum state transmission

Abstract

The application discloses a quantum chiplet communication system based on enhanced quantum state transmission, which converts quantum circuits into blocks, and a set of remote double quantum bit independent gates with high local characteristics and sharing the same logical quantum bit are transferred to a LocalBlock, and the whole is migrated to the same computing chip for execution, only one overall quantum state migration overhead is required, and multiple remote communications generated during scattered execution can be replaced, so that cumulative quantum state loss, error accumulation and execution delay caused by long-range communication are greatly reduced; meanwhile, local centralized execution can fully utilize the high connectivity in the computing area, and the communication execution module is used to schedule and execute the operation and transmission operation in stages, so that mutual interference and resource conflicts between operations are avoided, the execution efficiency of the whole gate set is significantly improved, and the fidelity of quantum chiplet communication is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of quantum computer technology, specifically relating to a quantum chip communication system based on enhanced quantum state transmission. Background Technology

[0002] With the development of quantum computing technology, the demand for qubits in practical quantum algorithms (such as variational quantum algorithms, quantum error correction, and quantum molecular simulation) has expanded to thousands. Scalability has become a core challenge for quantum computing to achieve practical applications. Quantum chiplet architecture, by coupling multiple superconducting chips to achieve modular expansion, effectively avoids the catastrophic error outbreaks, excessively long calibration times, and complex packaging problems faced by large monolithic chips, becoming a key solution to the scalability dilemma of quantum computing. However, the frequent long-range qubit communication during large-scale circuit execution leads to the core bottleneck of low communication fidelity and poor execution efficiency in existing quantum chiplet architectures, severely limiting their performance.

[0003] Currently, long-range quantum communication in quantum chip architecture mainly relies on two types of technical solutions, and the relevant representative studies constitute the prior art closest to this application:

[0004] One type of communication scheme is based on traditional gating or teleportation. The literature (Hezi Zhang, et al. MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets. ASPLOS, 2024.) proposes a multi-entry communication channel (MECH) architecture, which constructs the communication channel through centralized GHZ state preparation and uses teleportation to achieve remote quantum gate execution. This architecture abstracts auxiliary qubits as software-level communication channels, supporting spatiotemporal resource sharing and improving communication concurrency to some extent. However, this scheme still relies on a large number of equivalent CNOT gates for communication, resulting in significant gate error accumulation and limited long-range transmission fidelity. Furthermore, it does not fully consider the heterogeneity of inter-chip coupling and the dynamic adaptability of transmission strategies, making it difficult to select the optimal transmission scheme for different distances and types of qubit communication, leading to sub-optimization problems in communication efficiency.

[0005] Another type of communication scheme is based on enhanced quantum state transfer (EQST). The literature (Liang Xiang, et al. Enhanced quantum state transfer by circumventing quantum chaotic behavior. Nature Communications, 2024, 15:4918.) proposes an EQST implementation scheme that optimizes the coupling strength of qubits through Monte Carlo annealing, and verifies high-fidelity transmission of single-excitation, double-excitation, and Bell states on a superconducting quantum chip. As a Hamiltonian-controlled high-fidelity transmission mechanism, EQST can achieve parallel transmission of quantum information by finely adjusting the coupling strength of adjacent qubit pairs on the transmission link to satisfy the critical resonance condition. Its single-qubit state transmission fidelity has reached 0.992, significantly better than gate-based transmission models. However, this scheme mainly focuses on the physical implementation and coupling optimization of quantum state transmission, and has not formed a systematic solution adapted to the quantum chip architecture. On the one hand, it lacks an effective scheduling mechanism. After EQST transmission is started, it cannot exchange with other quantum states, resulting in low channel utilization and high transmission latency. On the other hand, it has not built a dedicated compilation framework, and cannot dynamically select the optimal transmission strategy based on qubit distance, gate dependency, etc. Blindly applying EQST will lead to efficiency loss in some scenarios. In addition, no effective optimization method has been proposed for the layout design of large-scale quantum on-chip networks. The complexity of brute-force search for the optimal layout increases exponentially, making it difficult to apply to actual large-scale systems.

[0006] In addition, traditional quantum compilation techniques (such as the Qiskit compiler) achieve qubit routing by inserting SWAP gates. However, as chip size increases, the routing path lengthens, leading to a surge in the number of gate operations. This not only increases circuit execution latency but also causes a sharp drop in communication fidelity due to the accumulation of gate errors (fidelity drops below 40% after about 80 operations). Meanwhile, distributed quantum computing compilation schemes make too many assumptions about the fully connected characteristics between processors, which do not match the constraints of sparse coupling and only adjacent connections between chips in the quantum chiplet architecture, making it difficult to directly adapt to applications.

[0007] In summary, while existing technologies have made some progress in the field of quantum chiplet communication, none have effectively solved the three core problems of low fidelity in long-distance communication, suboptimal transmission efficiency, and complex layout design in large-scale quantum chiplet architectures. How to integrate the high-fidelity advantages of EQST and build a full-stack solution that includes architecture design, scheduling mechanisms, compilation optimization, and layout schemes has become the key to breaking through the bottleneck of quantum chiplet communication and is also a technical challenge that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] This invention provides a quantum chip communication system based on enhanced quantum state transmission, which can significantly improve the fidelity and efficiency of quantum circuits.

[0009] This invention provides a quantum chip communication system based on enhanced quantum state transmission, comprising:

[0010] Template-driven encapsulation module is used to divide the encapsulation area, adapt the template, and fill the computing chip to obtain a quantum on-chip network;

[0011] A dependency compiler is used to convert quantum circuits into directed acyclic gate dependency graphs, find the dependency-free gates of the gate dependency graph, and initially allocate logical qubits to physical qubits of computing chips. Based on the dependency-free gates, the physical location and locality of logical qubits, the quantum circuit is converted into a block dependency graph including communication blocks and inter-block dependencies. The communication blocks include LocalBlock, TeleBlock and MoveBlock. The MoveBlock is a set of remote two-qubit dependency-free gates located on different computing chips, with high locality and sharing the same logical qubit. At the same time, the communication blocks are mapped to carry operations and / or transmission operations.

[0012] The communication execution module is used to allocate the mounting operation to the mounting stage scheduling and the transmission operation to the transmission stage scheduling, and execute the mounting stage scheduling and transmission stage scheduling respectively, thereby migrating the logical qubits corresponding to the MoveBlock to the same computing chip to realize quantum chip communication.

[0013] Preferably, the method for obtaining MoveBlock includes:

[0014] (1) The set of core gates obtained is used as the initial gate set. The core gates are two-qubit independent gates that involve different computational regions and require long-distance communication for execution.

[0015] (2) Based on the gate dependency graph, find a set of independent gates that are independent of the gates in the initial gate set and can be emitted in parallel, and select long-range communication independent gates that share the same control qubit with the corresponding gates in the initial gate set from the set of independent gates.

[0016] (3) When the long-range communication-type dependency-free gates selected in step (2) are included in the initial gate set, and the updated initial gate set satisfies the high locality feature, then repeat steps (2) and (3) until the updated initial gate set no longer satisfies the high locality feature and stop repeating to obtain MoveBlock.

[0017] Preferably, mapping MoveBlock to mount and / or transfer operations includes:

[0018] First, the gates of MoveBlock are mapped to source computing chip site routing operations in the transmission operation, and then mapped to the mount operation. The mount operation includes at least the move-in transmission chip operation and the move-out transmission chip operation, and may also include the transfer operation between transmission chips. Finally, it is mapped to the EQST quantum state transmission operation, the target computing chip site routing operation and the local logic gate execution operation in the transmission operation.

[0019] Preferably, the method for obtaining a LocalBlock includes:

[0020] If two logical qubits are located in the same computational region, and the fidelity of local execution is higher than that of execution after transmission via EQST, then the corresponding two-qubit gate is assigned to a LocalBlock. The two logical qubits corresponding to the two-qubit gate assigned to the LocalBlock are directly executed through qubit routing.

[0021] Preferably, after determining LocalBlock and MoveBlock, the method for determining TeleBlock includes:

[0022] To obtain a remote gate that involves different computing regions or requires long-distance communication, first check other independent gates that share the same control qubits with the remote gate. If the number of other independent gates exceeds two, then gather the other independent gates into TeleBlock.

[0023] If the number of other independent gates does not exceed two, then S1, according to the gate dependency graph, find a quantum gate that is independent of any other independent gate and can share the same control qubit, and form a candidate gate set with the other independent gates and the found quantum gate. S2, if the candidate gate set does not meet the high locality feature, then iterate steps S1 and S2 until the candidate gate set meets the high locality feature or there are no gates to collect, stop the iteration, and take the obtained candidate gate set as TeleBlock.

[0024] TeleBLock is mapped to a fixed combination of mount and transmission operations according to the execution logic. First, it is mapped to the GHZ state preparation operation in the mount operation, and then sequentially mapped to the site routing operation, the invisible transmission control gate execution operation, and the local logic gate execution operation in the transmission operation.

[0025] Preferably, allocating the loading operation to the loading phase scheduling includes:

[0026] All loading operations after compilation and mapping are executed during the loading stage. The scheduling follows priority rules, including: priority iterative launch of operations to move out of the transmission chip, transfer between transmission chips and operation to move into the transmission chip, and then scheduling and launch of the GHZ state preparation operation. Before launch, it must be confirmed that the corresponding physical qubit on the target transmission chip is not occupied.

[0027] Preferably, before entering the transmission operation, the EQST operation to be executed is subjected to delay synchronization processing to ensure that all EQST operations scheduled within the same transmission phase can be started synchronously, thereby realizing the shared utilization of the EQST channel of the transmission chip.

[0028] Preferably, allocating the transmission operation to the transmission phase schedule includes:

[0029] All transmission operations after compilation and mapping are executed during the transmission phase. The occupancy state of each physical quantum bit on the transmission chip is established and maintained in each transmission phase through a dictionary. If a physical quantum bit needs to carry a logical quantum bit that is to be taken offline, it is marked as frozen.

[0030] When scheduling EQST quantum state transfer operations, the operation is allocated only if the target physical qubit is not marked as frozen, and after allocation, the target physical qubit is marked as frozen until the transfer operation is completed.

[0031] If the target physical qubit already has a logical qubit, an additional EQST quantum state transfer operation is inserted to synchronously transfer the logical qubit back to the source location, thus completely avoiding hardware resource conflicts.

[0032] By leveraging the hardware resource independence of the computing chip and the transmission chip, the site routing within the computing chip and the EQST quantum state transmission in the transmission stage are scheduled and executed in parallel.

[0033] Preferably, the mounting operation is a pre- or post-operation related to the transmission chip in the packaging area, and the mounting operation includes GHZ state preparation, inter-transmission chip transfer, transmission chip migration in, and transmission chip migration out.

[0034] The transmission operation is a core operation performed within the computing region or transmission chip, and includes quantum state transmission, site routing, local gate, and teleportation.

[0035] Preferably, the encapsulation region is divided using an iterative segmentation algorithm, and the suitable templates include radial templates, grid templates, and stripe templates, including:

[0036] Step a: Treat the encapsulation region as a single initial computation region, select an appropriate template based on the initial computation region, and divide the initial computation region into multiple sub-regions based on the selected template;

[0037] Step b: Assign a suitable template to each sub-region based on its size;

[0038] Step c: Repeat step b to recursively segment and adapt templates for each further segmented region until the width of all sub-regions is less than twice the maximum chip side length.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] This invention transforms the quantum circuit into a block dependency graph, bringing together a set of remote two-qubit dependency-free gates located on different computing chips, possessing high locality characteristics and sharing the same logical qubit, into a MoveBlock. The entire set is then migrated to the same computing chip for execution, requiring only a single overall quantum state migration overhead. This replaces the multiple remote communications required during distributed execution, significantly reducing the cumulative quantum state loss, error accumulation, and execution latency caused by long-distance communication. Simultaneously, local centralized execution fully utilizes the high connectivity within the computing region. Furthermore, the communication execution module schedules the onboard and transmission operations in stages, avoiding mutual interference and resource conflicts between operations. This significantly improves the overall execution efficiency of the gate set while effectively enhancing the fidelity of quantum chip communication. Attached Figure Description

[0041] Figure 1 This is a schematic diagram illustrating the structure and operation of a quantum network-on-a-chip (NoC) provided in a specific embodiment of the present invention. Figure 1 (a) in the diagram represents the quantum on-chip network architecture. Figure 1 (b) in the diagram represents the transmission process in a quantum on-chip network;

[0042] Figure 2 A schematic diagram illustrating the delay reduction achieved by the collaborative scheduling strategy provided in a specific embodiment of the present invention;

[0043] Figure 3 A schematic diagram of a quantum chip communication system based on enhanced quantum state transmission provided for a specific embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the packaging area division provided for a specific embodiment of the present invention, wherein, Figure 4 (a) in the image is a radial template. Figure 4 (b) in the template is a grid type. Figure 4 (c) in the template is a striped pattern. Figure 4 (d) in the example is a template-based design.

[0045] Figure 5 The internal operation dependency graph of TeleBlock and MoveBlock provided for a specific embodiment of the present invention Figure 5(a) in the graph is the internal operation dependency graph of TeleBlock. Figure 5 (b) in the graph is the internal operation dependency graph of MoveBlock;

[0046] Figure 6 The original quantum bit communication path provided for a specific embodiment of the present invention Figure 6 In the diagram, (a) shows the original communication path for qubits that are relatively close together. Figure 6 (b) in the diagram represents the original communication path of the qubit pair that shares the control qubit. Detailed Implementation

[0047] The specific embodiments of the present invention aim to solve the problems of low fidelity, low execution efficiency and complex layout design of long-range quantum communication in existing quantum chiplet architectures, and provide a quantum chiplet communication system and method based on enhanced quantum state transmission (EQST). Through innovative architecture design, transmission mechanism, compilation scheme and packaging optimization, the fidelity and efficiency of quantum circuit execution are significantly improved.

[0048] The core design principle of the quantum on-chip network architecture provided in this specific embodiment of the invention is to separate communication and computation functions, fully leveraging the advantages of different topologies—EQST transmission is suitable for execution on a one-dimensional quantum bit chain, while computational tasks are more efficient in a two-dimensional highly connected quantum bit topology. For example... Figure 1 As shown in (a), the architecture consists of two types of core chips: a one-dimensional transmission chip dedicated to EQST transmission, and a two-dimensional computing chip for carrying out computational tasks. The transmission chip and the computing chip are connected through specific physical qubits to form a dedicated transmission network. Data qubits can enter and exit the transmission network through these connection points, providing the hardware foundation for long-range quantum communication.

[0049] The basic transmission process of quantum bits is as follows Figure 1 As shown in (b) above, this process forms the core framework of all quantum communication:

[0050] (1) Routing to the network entry point: The quantum bits to be transmitted first complete the routing through a small number of SWAP gates in their respective computing chips and move to the nearest transmission network entry point, i.e., routing within the computing chip (IN-C). This entry point is a fixed connection point between the computing chip and the transmission chip, thereby ensuring that the quantum bits can efficiently access the transmission network (CT).

[0051] (2) Transmission within the transmission network: After entering the transmission network, the qubit is carried by a transmission chip and transmitted over long distances using EQST technology. When the transmission target is not within the coverage area of ​​the current transmission chip, the qubit can transfer at a relay station (the connection point of different transmission chips) and switch to the transmission chip in the direction of the target to continue transmission.

[0052] (3) Outgoing network and final route: After the qubit arrives at the exit of the transmission network corresponding to the target computing region, it leaves the transmission network (TC) through an outgoing operation and enters the target computing chip. Then, it completes the final destination route through a small number of SWAP gates, realizing communication with the target qubit or participating in computing tasks.

[0053] When multiple qubits are transmitted simultaneously, they can be mounted at different physical locations on the same transmission chip, sharing the EQST transmission channel. This parallel transmission mode fully utilizes the inherent parallel characteristics of EQST, significantly improving the resource utilization of the transmission network and avoiding the inefficiency caused by a single transmission task monopolizing the channel.

[0054] In order to achieve fine-grained scheduling and unified management, in a specific embodiment of the present invention, we divide all communication-related hardware operations into two categories according to their functions: board operations and travel operations, which correspond to the “entry preparation / exit completion” and “in-transit transportation” stages in the subway system, respectively.

[0055] The board operation provided in the specific embodiments of this invention refers to the pre- or post-operations related to the transmission chip, which prepare for or complete the transmission of quantum bits. Specifically, it includes:

[0056] GHZ state preparation (GHZ): Provides the necessary GHZ state for teleportation communication. When the physical qubits of the computing chip are fully occupied by computing tasks, the GHZ state preparation can be completed directly in the transmission chip network, avoiding the occupation of the quantum computing resources of the computing chip.

[0057] Inter-transfer chip transfer (TT): When there is no direct transfer chip between the source computing chip and the target computing chip, the operation of qubits moving between different transfer chips through inter-chip couplers is analogous to inter-line transfer in a subway system.

[0058] Transfer chip migration (CT): The operation of moving qubits from the computing chip into the transfer chip through the inter-chip coupler, i.e., the "entry" process.

[0059] Transfer-out transfer chip (TC): The operation of moving qubits on the transfer chip to the computing chip through the inter-chip coupler, i.e., the "out-of-station" process.

[0060] The specific embodiments of this invention provide a travel operation, which refers to the core operation performed within the computing region or transmission chip to drive the qubits to complete communication or computation. Specifically, it includes:

[0061] Quantum State Transmission (EQST): The core operation for long-distance transmission of quantum bits is achieved on the transmission chip through EQST technology, analogous to the "on-the-go" operation of a subway.

[0062] Site routing (SWAP routing in IN-C): Within the computing chip or the site coverage area of ​​the transmission chip, the quantum bit completes the routing operation to the target physical location by continuously executing SWAP gates.

[0063] Local gate (local logic gate in IN-C): A logic gate operation that is executed directly within a single computational region, including original local gates that can be executed without remote communication after a qubit is moved.

[0064] Teleportation (transmission control gate in IN-C): Local gate operation required to perform quantum teleportation. Its core function is to load or extract quantum information from an auxiliary GHZ entangled state to realize the remote transfer of quantum states.

[0065] It is important to note that due to the exclusivity of the EQST operation—that is, the transmission chip and the computing chip cannot exchange quantum states during transmission—the boarding and transmission operations cannot be executed concurrently. This constraint provides the design basis for the subsequent interleaved operation launch mechanism. This interleaved operation launch mechanism addresses the scheduling conflict problem caused by the exclusivity of the EQST operation. Specifically, this invention designs an interleaved hardware operation launch mechanism, dividing the execution process into alternating boarding and transmission phases to ensure conflict-free operation execution and maximize transmission channel utilization. In one specific embodiment, its implementation logic is as follows: Figure 2 As shown.

[0066] Figure 2 This paper demonstrates a comparison between two modes: direct first-come, first-served scheduling and the cooperative scheduling of this invention. Q1 is the first-ready qubit to be transmitted, meaning Q1 completes its mounting preparation earlier and can initiate EQST transmission first. Q2 is a qubit that completes mounting slightly later, with a slight preparation delay. Under first-come, first-served scheduling, Q1 immediately starts EQST transmission in stage 3 after becoming ready in stage 2. Because the EQST link is exclusive, Q2 must wait for Q1 to complete its transmission in stage 3 before it can start transmitting. The two transmission segments are partially serial, resulting in extremely high total latency. However, this invention, through cooperative scheduling, imposes a controllable short wait on the already ready Q1, allowing Q1 and Q2 to start EQST transmission synchronously in stage 3. This merges the two originally serial transmission segments into a single round of parallel transmission, achieving an overall transmission latency reduction of 225 ns with minimal waiting time, significantly improving transmission efficiency and channel utilization.

[0067] Based on this, the specific implementation logic of the interleaved operation emission mechanism of the present invention is as follows:

[0068] a. Phase Division and Operation Allocation: The mounting phase is dedicated to performing various mounting operations, specifically including GHZ state preparation, inter-transfer chip transfer, and transfer-in and transfer-out operations. The transmission phase is dedicated to performing various transmission operations, specifically including EQST quantum state transmission, site routing, local access, and teleportation operations. This dedicated phase operation allocation method completely avoids concurrent execution conflicts between the two types of operations, ensuring the stability of the EQST quantum state transmission process and preventing interference from other operations.

[0069] b. Delay Synchronization and Channel Sharing: Different onboard operations have inherent differences in execution delay. To address this characteristic, delay synchronization is performed on all pending EQST operations before entering the transmission phase. This ensures that all EQST operations scheduled within the same transmission phase can be started synchronously, enabling the shared utilization of the transmission chip's EQST channel. This allows each round of transmission to reach its maximum carrying capacity and improves the overall utilization efficiency of the transmission channel.

[0070] c. Parallel Optimization: Leveraging the hardware resource independence of the computing chip and the transmission chip, the site routing operations within the computing chip and the EQST quantum state transmission operations during the transmission phase are scheduled for parallel execution. While the qubits are performing EQST long-distance transmission on the transmission chip, the site routing operations of other qubits can be executed synchronously within the target computing chip, effectively reducing the overall system operation execution latency and improving the communication throughput of the quantum chip network.

[0071] The core of the specific embodiments of this invention is to construct a quantum on-chip network architecture, such as... Figure 3 As shown, EQST is used as a high-fidelity transmission primitive, combined with a cooperative transmission mechanism, a dependency-aware compiler, and a template-driven encapsulation module to form a full-stack optimization framework. The quantum on-chip network architecture consists of a one-dimensional transmission chip and a two-dimensional computing chip. The transmission chip is responsible for long-range quantum communication, and the computing chip is responsible for computation tasks. The cooperative transmission mechanism solves the scheduling and parallelization problems of EQST transmission; the dependency-aware compiler realizes the optimal selection of transmission strategies; and the template-driven encapsulation module efficiently completes the network layout design. The four components work together to achieve high-fidelity and high-efficiency quantum communication and computation. The specific optimization scheme is as follows:

[0072] The template-driven encapsulation module provided in the specific embodiments of the present invention is used to divide the encapsulation area, adapt the template, and fill the computing chip to obtain a quantum on-chip network.

[0073] The core of the template-driven encapsulation module optimization provided in this specific embodiment of the invention is to solve the problem of "exponentially complex spatial design of large-scale quantum on-chip networks." By using predefined layout templates and iterative segmentation algorithms, the layout design complexity is significantly reduced while ensuring transmission performance. Its implementation revolves around three key stages: template design, template selection, and iterative segmentation. Figure 4 As shown.

[0074] Specific embodiments of this invention provide three types of templates—radial, grid, and striped—based on the crossover types (T-shaped, cross-shaped, and no crossover) between transmission chips and combined with the size characteristics of different packaging areas. These templates are adapted to wide, long, and narrow regions, respectively. Figure 4 (a)- Figure 4 As shown in (c):

[0075] a. Radial template ( Figure 4 In (a) of the diagram: The radial template is designed with four transmission chips extending radially from the central region, resembling a windmill. The transmission chips intersect in a cross shape, with the central region acting as a relay station. All transmission chips are connected through the central hub. This template is suitable for wide regions with side lengths x and y exceeding six times the chip size, typically in a 100×100 package. Its core advantage lies in the fact that radial symmetry ensures consistent accessibility in all directions, minimizing the path from each qubit to the central hub and minimizing transfers. Experimental data shows that when this template is used in a 100×100 region, the average transmission fidelity is improved by 13.45% compared to the grid template, and the isotropy is enhanced by 1.57 times. It should be noted that the central region sacrifices some computational density due to the arrangement of the transmission chip hub, making it more suitable for scenarios where communication balance requirements are higher than computational density.

[0076] b. Grid template ( Figure 4 (b) of the template: The structure of the grid template is designed with long transmission chips arranged in the main axis direction of the package and short transmission chips arranged in the vertical direction. The intersection type of the long transmission chips and the short transmission chips is T-shaped intersection, which together form a grid-like transmission network. This template is suitable for narrow and long areas with a single side length exceeding six times the chip size, such as a 100×40 package. Its core advantage lies in the fact that the long transmission chips can ensure efficient long-distance communication in the main axis direction, while the short transmission chips can avoid communication blind spots in the vertical direction, achieving a good balance between global reachability and computing density. Quantitative data shows that when this template is used in a 100×40 area, the fidelity is improved by 11.71% compared with the striped template, and the isotropy is improved by 1.66 times.

[0077] c. Striped template ( Figure 4(c) in the text: The striped template is designed so that all transmission chips are arranged in the same direction without any intersections, and the transmission chips and computing chips are arranged in parallel to form a striped transmission network. This template is suitable for narrow regions with side lengths less than six times the chip size, such as 40×40 packages. Its core advantage is that the unidirectional structure can maximize the effective capacity of EQST along the main axis, with the lowest layout complexity and high communication throughput. In the 40×40 region, compared with the radial template, the fidelity is improved by 2.06% and the isotropy is improved by 1.10 times, which is especially suitable for scenarios where the load presents a strong one-dimensional locality.

[0078] The computing region provided in this embodiment refers to the smallest logical execution unit in a quantum chip system that can independently perform local gate operations of two qubits and complete direct interaction between qubits without the need for long-distance communication or quantum state transmission. One computing region corresponds to a single physical computing chip. Any two qubits in the same computing region can directly perform local two-qubit gate operations. The interaction between qubits in different computing regions must rely on long-distance communication.

[0079] The transmission region provided in this embodiment is a hardware region in the quantum chip specifically responsible for long-range quantum state transmission. It does not execute local quantum logic gates and is only used to realize the transfer of qubits and quantum state transmission between computing regions.

[0080] The optimization criteria for template selection in specific embodiments of this invention are driven by two core criteria directly related to EQST communication quality, ensuring that the selected template maximizes transmission performance: Average transmission fidelity measures the overall efficiency of long-range cross-regional transmission, calculated by uniformly sampling qubit pairs on candidate templates and calculating the mean of transmission fidelity; Transmission isotropy characterizes the uniformity of communication performance in different directions, measured by calculating the coefficient of variation (the ratio of standard deviation to mean) of the sampling fidelity, with lower coefficients of variation indicating better isotropy. During the selection process, templates with high average transmission fidelity and low coefficients of variation are prioritized to ensure consistent and efficient qubit communication performance across different directions and locations.

[0081] In a specific embodiment of the present invention, the encapsulation region is divided using an iterative segmentation algorithm, and the specific steps are as follows:

[0082] The iterative partitioning algorithm provided in this embodiment is designed based on the divide-and-conquer approach. Its core purpose is to address the exponential complexity problem of brute-force search methods in large-scale quantum network-on-a-chip (NoC) packaging layout design. It achieves efficient layout planning for transmission and computing chips, balancing enhanced quantum state transport (EQST) communication performance with computational density. The algorithm's input includes the overall quantum package size, maximum chip side length, three types of preset templates (radial / grid / striped), and chip manufacturing constraints. The output is a complete quantum network-on-a-chip packaging layout that fills the computing chip and adapts to EQST communication. The following uses a 100×100 quantum package region as an example to explain the algorithm implementation process in detail:

[0083] Step a. Initial Division: Treat the entire encapsulation area as a single computational region and select a suitable initial template based on its size characteristics. A 100×100 region is a wide area; a radial template is selected as the initial template, dividing it into 5 sub-regions (1 in the center and 4 around the perimeter).

[0084] Step b. Sub-region template adaptation: The size of each sub-region is determined, and the corresponding template is selected for further refinement. The central sub-region is relatively small (approximately 20×20), a narrow area, so a striped template is selected for refinement, with densely arranged computing chips to increase computational density. Each sub-region in the surrounding areas is a long and narrow area (approximately 40×80), so a grid template is selected for refinement, with long and short transmission chips arranged to support bidirectional high-efficiency transmission.

[0085] Step c. Recursive processing: Repeat step b, recursively segmenting and adapting templates for each further segmented region until the width of all sub-regions is less than twice the maximum chip side length (20 qubits in this embodiment). This ensures that short-distance communication within the sub-regions can be completed through local operation or simple gated transmission without complex routing. Experiments have verified that when the transmission distance of the qubits exceeds twice the maximum chip side length, EQST's long-distance transmission fidelity and execution efficiency significantly surpass traditional quantum gate-based transmission (such as SWAP gate cascade). When the distance is less than this threshold, the local operation overhead of quantum gate-based transmission is lower, and communication can be completed without the need for EQST's dedicated transmission chip.

[0086] Step d. Computation chip filling: For each final sub-region, fill it with the largest available computing chip (in this embodiment, a 10×10 grid qubit chip) to complete the packaging design of the entire quantum on-chip network, such as... Figure 4 As shown in (d) in the figure.

[0087] This algorithm reduces the layout design complexity from O(x^k) (where x is the package side length and k is the number of transmission chips) of brute-force search to the linear level of the number of templates. For example, for the design of a 100×100 quantum on-chip network with 4 transmission chips, brute-force search using an AMD EPYC 9554 CPU would take more than 50 years, while this algorithm can complete it in just a few hours, and the transmission fidelity of the layout design is close to the optimal level.

[0088] The dependency compiler provided in this specific embodiment of the invention is used to convert quantum circuits into directed acyclic gate dependency graphs, find the dependency-free gates of the gate dependency graphs, and initially allocate logical qubits to physical qubits of computing chips. Based on the dependency-free gates, the physical location and locality characteristics of the logical qubits, the quantum circuits are converted into block dependency graphs including communication blocks and inter-block dependencies. The communication blocks include LocalBlock, TeleBlock and MoveBlock. The MoveBlock is a set of remote two-qubit dependency-free gates located on different computing chips, with high locality characteristics and sharing the same logical qubit. At the same time, the mounting operation and / or transmission operation corresponding to the communication block are obtained.

[0089] The core of the dependency compiler provided by this invention is to achieve a complete compilation mapping from quantum circuits to hardware executable operations, maximizing the parallelism of operations while strictly adhering to data dependencies and hardware resource constraints. Its implementation revolves around three core steps: compilation mapping from quantum circuits to hardware operations, data dependency analysis, and execution of conservative scheduling strategies. The specific process is as follows:

[0090] (1) Construction and initial mapping of gate dependency graph: The construction of gate dependency graph is the core process of transforming various control gates in quantum circuits, i.e. quantum programs, into directed acyclic gate dependency graphs. Specifically, it is achieved by capturing the execution order of quantum gates and the commutative relationship between gate pairs: First, according to the logic of the quantum program, the execution pre-constraints of each control gate are clarified, and the control gates with execution order dependencies are connected by directed edges to form basic dependency links; then, for control gates without clear execution order constraints, their commutativity is further determined, and finally a directed acyclic gate dependency graph with no loops and clear characterization of logical associations between gates is constructed, which accurately reflects the execution logic and association characteristics of quantum gates.

[0091] The criterion for determining the commutativity between gate pairs is as follows: when two control gates act on sets of non-intersecting qubits, or share only one common control qubit, the two control gates are determined to be commutative. This determination provides the core basis for the parallel scheduling of subsequent hardware operations—control gates determined to be commutative have no data dependencies or resource conflicts after being compiled and mapped to hardware operations, and can be executed in parallel during the scheduling process; while non-commutative control gates, due to qubit interactions or execution constraints, need to be scheduled serially according to the directed links of the gate dependency graph. Based on this, the parallel execution potential of hardware operations can be maximized and scheduling efficiency can be improved.

[0092] The initial mapping provided in this specific embodiment of the invention adopts a random mapping method to allocate logical qubits to physical qubits on the computing chip. For large-scale quantum programs, dense two-qubit interactions are common. The impact of the initial layout will be quickly eliminated during subsequent compilation and scheduling. The benefits of additional optimization of the initial mapping are limited, and it will also increase the overall compilation overhead. At the same time, for each inter-chip coupler between the computing chip and the transmission chip, adjacent physical qubits are reserved as a buffer, which is used exclusively for logical qubits to cross the transmission network, avoiding resource conflicts during the qubit routing process from the hardware layout level.

[0093] (2) Communication block conversion logic: Iteratively select dependency-free gates in the gate dependency graph (i.e., quantum gates with no preceding execution dependencies and which can be preferentially selected for execution) according to the topological order. Based on the physical location of the qubits and the locality characteristics of the gates, convert them into three types of communication blocks: LocalBlock, TeleBlock, or MoveBlock. The division of LocalBlock and MoveBlock is completed first, and then the remaining dependency-free gates are judged according to the rules to generate TeleBlocks. The specific conversion logic is as follows:

[0094] MoveBlock is a set of two-qubit gates that can be executed directly within a single computational region without the need for Enhanced Quantum State Transmission (EQST). If the two qubits are located in the same computational region and the fidelity of local execution (without EQST) is higher than that of execution after EQST transmission, then the two-qubit gate is converted into MoveBlock and executed through direct qubit routing. This method can avoid quantum state loss and operational overhead caused by cross-chip transmission, reduce unnecessary communication latency, and improve the fidelity and efficiency of single-gate execution by utilizing the high connectivity within the computational region.

[0095] The method for obtaining MoveBlock provided in specific embodiments of the present invention includes:

[0096] (1) The set of core gates obtained is used as the initial gate set. The core gates are two-qubit independent gates that involve different computation regions and require long-distance communication for execution.

[0097] (2) Based on the gate dependency graph, find the gates that are not dependent on the gates in the initial gate set (the gates that are not dependent on the gates in the initial gate set can be understood as gates that are not connected to the gates in the initial gate set in the gate dependency graph), and be able to transmit in parallel from the same batch of gates that are not dependent on the gates, and select long-range communication gates that share the same control qubit with the corresponding gates in the initial gate set.

[0098] (3) When the long-range communication-type dependency-free gates selected in step (2) are included in the initial gate set, and the updated initial gate set satisfies the high locality feature, then repeat steps (2) and (3) until the updated initial gate set no longer satisfies the high locality feature and stop repeating to obtain MoveBlock.

[0099] Specifically, the MoveBlock provided in this embodiment of the invention is a set of quantum gates that need to be centrally executed after migrating the entire set of qubits to the same computational region. The initial gate set is a temporary set of dependency-free gates with potential aggregation execution possibility, constructed by screening long-range two-qubit gates without prior execution dependencies in the quantum gate dependency graph as core gates. The core gates are two-qubit gates that involve different computational regions and require long-distance communication for execution. During the screening process, long-distance communication-type dependency-free gates that share the same control qubit are first selected from the dependency-free gates in the same batch as the core gates and included in the initial gate set. Then, the heuristic inequality "number of gates > Using "n(n-1) / 2" (where n is the total number of qubits in the current gate set, and n(n-1) / 2 is the maximum number of different qubit pairs that can be formed by all qubits in the gate set) as the criterion, iteratively collects dependent gates with high locality characteristics and includes them in the gate set. If the inequality is still satisfied after adding a gate, the expansion continues; otherwise, the expansion stops. The final updated initial gate set is a set of dependent gates with a relatively small number of qubits and frequent interactions between gates. All gates in the set are qubits that require long-distance communication, excluding qubits that can be executed locally. When the candidate gate set satisfies the above heuristic inequality, it indicates that its corresponding sub-circuit exhibits dense connectivity and strong locality. Such gates involve a relatively small number of qubits but frequent interactions. They are converted into MoveBlocks and migrated to the same computing chip for execution. Only one overall quantum state migration overhead is needed to replace the multiple remote communications generated during decentralized execution, which greatly reduces the cumulative quantum state loss and execution delay caused by long-distance communication. At the same time, local centralized execution can make full use of the high connectivity within the computing area and significantly improve the overall execution efficiency of the gate set.

[0100] TeleBlock is a set of quantum gates suitable for long-range communication execution via teleportation. For "remote gates" not classified as LocalBlock or MoveBlock, involving different computational regions, or requiring long-range communication, it first checks other independent gates that share the same control qubit with the remote gate (i.e., long-range communication quantum gates without prior execution dependencies and sharing a control qubit with the remote gate). If there are more than two such gates, these gates are converted into TeleBlocks and executed via teleportation. This fully utilizes the efficient support of teleportation for multi-target gates, completing batch teleportation using the same set of GHz states, avoiding the need to establish separate long-range communication links for each group of gates, and significantly reducing the resource consumption of long-range communication. If the shared control qubit... If the number of other independent gates does not exceed two, and the number of gates with high locality features collected subsequently does not reach the preset threshold (the threshold is the maximum number of different qubit pairs that can be formed by all qubits in the candidate gate set, calculated by the formula n(n-1) / 2, where n is the number of qubits in the candidate gate set, i.e., high locality features), these gates will also be grouped into TeleBlock. At this time, the GHZ state preparation location is determined by exhaustive search, minimizing the sum of its distances to each involved data qubit, reducing the transmission loss between the qubit and the GHZ state preparation point, reducing the overall execution delay of teleportation, and ensuring the efficiency and fidelity of long-distance communication.

[0101] If the number of other independent gates sharing the control qubit does not exceed two, and the number of gates with high locality features collected subsequently does not reach a preset threshold, these gates will also be grouped into a TeleBlock. This includes: if the number of other independent gates does not exceed two, S1, find a quantum gate that is independent of any other independent gate and can share the same control qubit according to the gate dependency graph, and form a candidate gate set with the other independent gates and the found quantum gate; S2, if the candidate gate set does not meet the high locality feature, iterate steps S1 and S2 until the candidate gate set meets the high locality feature or there are no gates to collect, stop the iteration, and take the obtained candidate gate set as a TeleBlock.

[0102] In specific embodiments of this invention, communication blocks are compiled and mapped one by one into two types of hardware-executable operations defined by the system: board operations and travel operations, according to the execution characteristics of various communication blocks and preset hardware operation specifications. This achieves a precise conversion from abstract quantum circuits to physical hardware operations. The specific mapping rules are as follows:

[0103] LocalBlock is a set of logic operations that can be directly executed within a single computing chip. It does not require cross-chip transmission and is only mapped to transmission operations. Specifically, it consists of site routing operations and local logic gate execution operations within the computing chip, without the need to call on-board operations.

[0104] TeleBlock is a set of logical operations for long-range communication based on stealth state transfer. It is mapped to a fixed combination of carry-on and transmission operations according to the execution logic. First, it is mapped to the GHZ state preparation operation in the carry-on operation, and then sequentially mapped to the site routing operation, stealth state transfer control gate execution operation and local logic gate execution operation in the transmission operation.

[0105] MoveBlock is a set of logic operations that need to be executed after the entire qubit is migrated to the same computing chip. It is mapped sequentially according to the qubit migration and computing process. First, it is mapped to the source computing chip site routing operation in the transmission operation. Then, it is mapped to the migration into the transmission chip operation, the transfer operation between transmission chips (mapped on demand), and the migration out of the transmission chip operation in the mounting operation. Finally, it is mapped to the EQST quantum state transmission operation, the target computing chip site routing operation, and the local logic gate execution operation in the transmission operation.

[0106] The data dependencies provided in the specific embodiments of this invention are the core hard constraints of hardware operation scheduling. These constraints exist between communication blocks and within the hardware operations after the communication blocks are transformed. Figure 5 shows a generalized abstract representation of the data dependencies within a communication block, clearly demonstrating the serial dependency chain of hardware operations within the two core communication blocks, TeleBlock and LocalBlock. It also reflects the execution dependency logic between communication blocks. All data dependencies are inherited layer by layer in the compilation mapping process from quantum circuits to communication blocks and then to hardware operations. The specific analysis is as follows:

[0107] Inter-block data dependency: The execution order constraint is formed between different communication blocks due to the interaction of quantum bit data. This constraint is clear in the communication block generation stage. After compilation and mapping into hardware operations, it directly manifests as the execution order constraint between the hardware operation sequences of the corresponding communication blocks. That is, all hardware operations of the dependent communication block must be completed and the quantum data transmission and interaction must be completed before the hardware operations of the dependent communication block can be started. There is no dependency constraint between communication blocks without data interaction.

[0108] Intra-block data dependency: Hardware operations within the same communication block form a fixed, sequential dependency chain due to the physical logic and execution flow of quantum state transmission, coupling, and computation. Figure 5 The document clearly defines the core rules for intra-block dependencies of two types of core communication blocks:

[0109] For TeleBlock, the dependency chain of intra-block hardware operations begins at GHZ state preparation and splits into two parallel execution chains from this node, ending at the execution of the teleportation control gate. The execution dependency chain splits into two paths from GHZ state preparation (GHZ): one is intra-chip site routing (INC); the other is enhanced quantum state transfer (EQST) → inter-chip transfer (TT) → enhanced quantum state transfer (EQST), ultimately converging at the point where the quantum bit is moved out of the transfer chip (TC) to execute the teleportation control gate. After the teleportation is completed, subsequent local logic gate operations are executed. Auxiliary quantum bits prepared for the transfer can be moved out to the buffer area of ​​the computing chip in advance, releasing physical quantum bit resources on the transfer chip and avoiding blocking of subsequent hardware operation scheduling, such as... Figure 5 As shown in (a) of the diagram.

[0110] For LocalBlock, intra-block hardware operations follow a serial dependency based on the physical flow of qubit migration. They must be executed in the following order: "Source computing chip site routing (IN-C) → Migration-in transfer chip (CT) → Enhanced quantum state transfer (EQST) → Qubit migration-out transfer chip (TC) → Target computing chip site routing (INC)". Local logic gate operations are executed only after migration is complete. Simultaneously, migration-in / migration-out pairing constraints must be set: the corresponding migration-out transfer chip operation can only be executed after the paired qubit has completed its migration-in transfer chip operation. This ensures the target computing chip has a free buffer area to receive qubits and avoids resource conflicts. Figure 5 As shown in (b) of the diagram.

[0111] The core advantage of the compiler utilizing the aforementioned dependency relationships in this invention lies in its dynamic selection of the optimal transmission strategy based on the quantum bit distance and gate characteristics, rather than blindly employing EQST.

[0112] a. Short-range communication: When two qubits are close enough (e.g., ... Figure 6 In the (a) black qubit pair, the gated transmission scheme is better. In this case, LocalBlock is selected to execute directly, avoiding the routing path extension caused by the additional cross-chip SWAP gate required by EQST.

[0113] b. Multi-objective gate communication: For qubit pairs that share control qubits (e.g.) Figure 6 (b) white qubit pair), choosing TeleBlock to perform teleportation avoids the detours required for qubit movement and improves transmission efficiency.

[0114] c. High locality and dense communication: For gate sets that satisfy the heuristic inequality, MoveBlock selects to migrate the entire set of qubits to the same computing chip for execution, reducing the number of remote communications.

[0115] d. Long-distance sparse communication: For qubit pairs with no shared control qubits, long distances, and sparse interactions, EQST transmission is selected to reduce error accumulation in long-distance communication by utilizing its high-fidelity characteristics.

[0116] The communication execution module provided in this specific embodiment of the invention is used to allocate the mounting operation to the mounting stage scheduling and the transmission operation to the transmission stage scheduling, and execute the mounting stage scheduling and transmission stage scheduling respectively, so as to migrate the logical qubits corresponding to the MoveBlock as a whole to the same computing chip, thereby completing the allocation of the physical location of the logical qubits and realizing quantum chip communication, as described in detail below:

[0117] After completing the compilation mapping from quantum circuits to hardware operations and analyzing data dependencies, and combining this with an interleaved hardware operation launch mechanism, all hardware operations are allocated to their corresponding onboarding or transmission stages for execution. A conservative scheduling strategy is adopted to maximize the parallel execution of hardware operations while strictly satisfying data dependencies and hardware resource constraints. The specific scheduling logic is as follows:

[0118] Loading Phase Scheduling: All compiled and mapped loading operations are executed during the loading phase. Scheduling follows a priority rule, prioritizing the iterative launch of transfer-out (TC), transfer-to-transfer (TT), and transfer-in (CT) operations. These operations only realize the physical location migration of qubits, do not change the number of logical qubits in the system, and do not introduce additional hardware resource conflicts. After the high-priority loading operations are scheduled, the GHZ state preparation operation is scheduled for launch. Before launch, it must be confirmed that the corresponding physical qubit on the target transfer chip is not occupied to avoid resource competition between auxiliary qubits and existing transfer qubits, and to ensure that teleportation-related operations are executed normally.

[0119] The iterative launch operations for the outgoing transport chip (TC), the transfer between transport chips (TT), and the incoming transport chip (CT) provided in this specific embodiment of the invention include: after each launch of the outgoing transport chip (TC), the transfer between transport chips (TT), and the incoming transport chip (CT), a check is performed. If there are remaining resources, the corresponding TC, TT, and CT are launched again until all legal payload operations are exhausted. The purpose of iterative launch is to complete all legal payload operations sequentially, conflict-free, and exhaustively under resource constraints. That is, these subsequent operations are not completed in one go, but are performed multiple times, and each launch has a dependency relationship.

[0120] Transmission Phase Scheduling: All compiled and mapped transmission operations are executed during the transmission phase. Scheduling is centered on fine-grained management of hardware resource states, while implementing parallel optimization strategies. A dictionary is used to establish and maintain the occupancy state of each physical qubit on the transmission chip in each transmission phase. If a physical qubit needs to carry a qubit awaiting disconnection, it is marked as "frozen." When scheduling EQST quantum state transmission operations, operation allocation is only performed if the target physical qubit is not marked as frozen, and immediately after allocation, the physical qubit is marked as frozen until the transmission operation is completed. If a logical qubit already exists at the target physical location, an additional EQST quantum state transmission operation is inserted to synchronously transmit the logical qubit back to the source location, completely avoiding hardware resource conflicts. For parallel optimization, leveraging the hardware resource independence of the computing chip and the transmission chip, the site routing operations within the computing chip and the EQST quantum state transmission operations in the transmission phase are scheduled and executed in parallel, reducing overall operation execution latency and improving overall system throughput.

[0121] Based on the above compilation mapping, dependency analysis and scheduling strategies, the parallel execution potential of hardware operations can be fully explored while ensuring all data dependencies and resource constraints, so as to achieve efficient and conflict-free scheduling of network communication and computing operations on quantum chips.

[0122] The overall workflow of the collaborative operation of the modules provided in the specific embodiments of the present invention is as follows: The core advantage of the present invention lies in the organic collaboration of the modules, rather than the independent application of a single technology.

[0123] (1) Packaging design: First, the template-driven packaging optimization module selects the appropriate template according to the target packaging size (e.g., 100×100), and completes the packaging layout of the quantum chip network through the iterative segmentation algorithm, determining the position, connection relationship and buffer configuration of the transmission chip and the computing chip.

[0124] (2) Program compilation: Input the input quantum program (such as QFT, VQE, etc.) into the dependency-aware compiler. Based on the physical topology of the quantum chip network, chip location and communication link information determined by the packaging design, construct the gate dependency graph, allocate qubits through initial mapping, identify the gate locality characteristics and convert them into LocalBlock, TeleBlock and MoveBlock, dynamically select the optimal transmission strategy and generate the block dependency graph.

[0125] (3) Transmission scheduling: The cooperative transmission mechanism receives the block dependency graph output by the compiler, converts each communication block into a corresponding hardware operation (carrying operation or transmission operation), and allocates it to the carrying stage or transmission stage through the interleaved operation issuance mechanism. Parallel scheduling is carried out based on data dependency and resource constraints to ensure that the operation is executed without conflict.

[0126] (4) Communication execution: The quantum bits complete routing, loading, transmission, transfer, migration and final routing in the quantum chip network according to the preset transmission process, realizing long-distance quantum communication and computing tasks. The high-fidelity characteristics and parallel advantages of collaborative scheduling of EQST are utilized throughout the process to improve the overall performance.

Claims

1. A quantum chip communication system based on enhanced quantum state transmission, characterized in that, include: Template-driven packaging module is used to divide the packaging area, adapt the template, and fill the computing chip to obtain a quantum on-chip network; A dependency compiler is used to convert quantum circuits into directed acyclic gate dependency graphs, find the dependency-free gates of the gate dependency graph, and initially allocate logical qubits to physical qubits of computing chips. Based on the dependency-free gates, the physical location and locality of logical qubits, the quantum circuit is converted into a block dependency graph including communication blocks and inter-block dependencies. The communication blocks include LocalBlock, TeleBlock and MoveBlock. The MoveBlock is a set of remote two-qubit dependency-free gates located on different computing chips, with high locality and sharing the same logical qubit. At the same time, the communication blocks are mapped to carry operations and / or transmission operations. The communication execution module is used to allocate the mounting operation to the mounting stage scheduling and the transmission operation to the transmission stage scheduling, and execute the mounting stage scheduling and the transmission stage scheduling respectively, so as to migrate the logical qubits corresponding to the MoveBlock to the same computing chip and realize quantum chip communication. The high locality feature is determined by the heuristic inequality "number of gates > n(n-1) / 2", where n is the total number of qubits in the candidate gate set; Methods for obtaining a LocalBlock include: If two logical qubits are located in the same computational region, and the fidelity of local execution is higher than that of execution after enhanced quantum state transmission, then the corresponding two-qubit gate is assigned to LocalBlock, and the two logical qubits corresponding to the two-qubit gate assigned to LocalBlock are directly executed through qubit routing. After determining the LocalBlock and MoveBlock, the TeleBlock is then determined. Methods for obtaining the TeleBlock include: To obtain a remote gate that involves different computing regions or requires long-distance communication, first check other independent gates that share the same control qubits with the remote gate. If the number of other independent gates exceeds two, then gather the other independent gates into TeleBlock. If the number of other independent gates does not exceed two, then S1, according to the gate dependency graph, find the quantum gate that is independent of other independent gates and can share the same control qubit, and form a candidate gate set with the other independent gates and the found quantum gate. S2, if the candidate gate set does not meet the high locality feature, then iterate steps S1 and S2 until the candidate gate set meets the high locality feature or there are no gates to collect, stop the iteration, and take the obtained candidate gate set as TeleBlock. TeleBLock is mapped to a fixed combination of mount and transmission operations according to the execution logic. First, it is mapped to the GHZ state preparation operation in the mount operation, and then sequentially mapped to the site routing operation, the invisible transmission control gate execution operation, and the local logic gate execution operation in the transmission operation.

2. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, Methods to obtain MoveBlock include: (1) The set of core gates obtained is used as the initial gate set. The core gates are two-qubit independent gates that involve different computational regions and require long-distance communication for execution. (2) Based on the gate dependency graph, find a set of independent gates that are independent of the gates in the initial gate set and can be emitted in parallel, and select long-range communication independent gates that share the same control qubit with the corresponding gates in the initial gate set from the set of independent gates. (3) When the long-range communication-type dependency-free gates selected in step (2) are included in the initial gate set, and the updated initial gate set satisfies the high locality feature, the updated initial gate set is used as the current candidate MoveBlock and steps (2) and (3) are repeated until the high locality feature is no longer satisfied after the long-range communication-type dependency-free gates are included, and the candidate gate set that satisfies the high locality feature for the last time before stopping is determined as MoveBlock.

3. The quantum chip communication system based on enhanced quantum state transmission according to claim 2, characterized in that, Map MoveBlock to carry operations and / or transport operations, including: First, the gates of MoveBlock are mapped to source computing chip site routing operations in the transmission operation, then mapped to the mounting operation, which includes migration into the transmission chip operation, migration out of the transmission chip operation, and transfer operation between transmission chips. Finally, it is mapped to enhanced quantum state transmission, target computing chip site routing operation, and local logic gate execution operation in the transmission operation.

4. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, Assigning the loading operation to the loading phase schedule includes: All loading operations after compilation and mapping are executed during the loading stage. The scheduling follows priority rules, including: priority iterative launch of the transfer chip outgoing operation, transfer chip inter-transfer operation and transfer chip incoming operation, and then the scheduled launch of the GHZ state preparation operation. Before launch, it is necessary to confirm that the corresponding physical qubit on the target transfer chip is not occupied. Prioritize iterative launch of outgoing transport chips, transfer between transport chips, and incoming transport chip operations. This includes checking after each launch of outgoing transport chips, transfer between transport chips, and incoming transport chip operations. If there are remaining resources, launch the corresponding transport chips, transfer between transport chips, and incoming transport chip operations again until all legal carry-on operations are exhausted.

5. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, Before entering the transmission operation, the EQST operation to be executed is delayed and synchronized to ensure that all enhanced quantum state transmissions scheduled within the same transmission phase can be started synchronously, thereby realizing the shared utilization of enhanced quantum state transmissions of the transmission chip.

6. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, Assigning the transmission operation to the transmission phase schedule includes: All transmission operations after compilation and mapping are executed during the transmission phase. The occupancy state of each physical quantum bit on the transmission chip is established and maintained in each transmission phase through a dictionary. If a physical quantum bit needs to carry a logical quantum bit that is to be taken offline, it is marked as frozen. When scheduling enhanced quantum state transmission, the operation allocation is performed only if the target physical qubit is not marked as frozen, and after allocation, the target physical qubit is marked as frozen until the transmission operation is completed; If the target physical qubit already has a logical qubit, then an additional enhanced quantum state transmission is inserted to synchronously transmit the logical qubit back to the source location, thus completely avoiding hardware resource conflicts. By leveraging the hardware resource independence of computing chips and transmission chips, the enhanced quantum state transmission of the site routing and transmission stages within the computing chip is scheduled and executed in parallel.

7. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, The mounting operation is a pre- or post-operation related to the transmission chip in the packaging area. The mounting operation includes GHZ state preparation, inter-transmission chip transfer, transfer chip ingress, and transfer chip egress. The transmission operation is a core operation performed within the computing region or transmission chip, and includes quantum state transmission, site routing, local gate, and teleportation.

8. The quantum chip communication system based on enhanced quantum state transmission according to claim 1, characterized in that, The encapsulation region is divided using an iterative segmentation algorithm. Adaptable templates include radial, grid, and striped templates, among others. Step a: Treat the encapsulation region as a single initial computation region, select an appropriate template based on the initial computation region, and divide the initial computation region into multiple sub-regions based on the selected template; Step b: Assign a suitable template to each sub-region based on its size; Step c: Repeat step b to recursively segment and adapt templates for each further segmented region until the width of all sub-regions is less than twice the maximum chip side length.

Images