Fully-integrated low-dropout linear regulator

Abstract

The invention discloses a low-dropout linear voltage regulator, which relates to the technical field of electronic circuits and is characterized in that bias currents of a main error amplifier and a buffer are dynamically adjusted according to load conditions, and meanwhile, a non-dominant pole in the low-dropout linear voltage regulator is pushed to high frequency and drives a main power tube through the buffer. The auxiliary error amplifier and the secondary power tube are added, when load current is small, output current is provided only through the main error amplifier, the main power tube and the auxiliary path, when the load current is larger than threshold current, the low dropout linear regulator can be converted into a three-level structure, and the secondary power tube can rapidly provide most current. Feedforward zero compensation based on the auxiliary path can be combined with conventional Miller compensation for application, the compensation capacitance can be greatly reduced, and the system bandwidth is improved. The low-dropout linear regulator has larger bandwidth and stronger transient charging and discharging capability, and low power consumption, high stability and excellent transient response performance are considered in a full-load range.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a fully integrated low-dropout linear regulator. Background Technology

[0002] Currently, with the rapid development of data center interconnection, 5G, and high-speed fiber optic communication systems, optical communication modules are evolving towards higher speeds, lower power consumption, and smaller package sizes. In the optical receiver link, the transimpedance amplifier (TIA), as the first-stage key module that converts the weak current signal output from a photodetector (such as a photodiode) into a voltage signal, directly determines the sensitivity, dynamic range, and bit error rate of the entire receiver link. The TIA needs to provide high gain and low noise amplification over an extremely wide frequency band, which places extremely stringent requirements on the purity, stability, and response speed of its power supply.

[0003] To meet the demands of system miniaturization and high integration, low-dropout regulators (LDOs) eliminate the need for expensive, large off-chip capacitors that occupy significant printed circuit board (PCB) area, thus reducing system cost, size, and improving reliability. However, this also means that LDOs lose the crucial role of off-chip capacitors in providing low-frequency poles in the frequency domain and buffering load current abrupt changes in the time domain. Under the constraint of extremely low quiescent current, the loop bandwidth of traditional fully integrated LDOs is limited, resulting in slow response to load transitions and significant overshoot / undershoot in the output voltage. This severely impacts the normal operation of subsequent load circuits and can even lead to system logic errors or performance degradation. Therefore, achieving a synergistic optimization of high stability, high transient response speed, and low quiescent power consumption without relying on off-chip capacitors has become a critical technical challenge that urgently needs to be addressed in this field.

[0004] To address the driving challenges of LDOs in low-power designs, extensive research has been conducted. Currently, a relatively effective solution consists of an error amplifier, a power transistor, a feedback network, a compensation network, and a transient enhancement path. The error amplifier and feedback network stabilize the output voltage near the ideal value, the power transistor provides adjustable load current, the compensation network improves system stability, and the transient enhancement path rapidly injects or extracts current into or from the gate or output of the power transistor by detecting changes in the output voltage.

[0005] While existing solutions effectively improve bandwidth and slew rate by increasing bias current, they significantly increase static power consumption. Transient enhancement path designs, although capable of improving slew rate and overcoming loop bandwidth limitations, also increase power consumption and introduce design challenges. Therefore, existing fully integrated LDOs often compromise between low power consumption and fast transient response, failing to achieve a good balance between both. Summary of the Invention

[0006] Therefore, it is necessary to provide a fully integrated low-dropout linear regulator to address the aforementioned technical problems.

[0007] The present invention adopts the following technical solution: This invention provides a fully integrated low-dropout linear regulator, comprising: a main error amplifier, a bias circuit, a buffer, a main power transistor, an auxiliary error amplifier, a secondary power transistor, a resistor feedback network, and an auxiliary path; The non-inverting input of the main error amplifier is connected to the output of the resistive feedback network, the inverting input is connected to an external reference voltage, and the output is connected to the input of a buffer. The output of the buffer is connected to the gate of the main power transistor. The source of the main power transistor is connected to an external power supply voltage. The main error amplifier provides loop gain to clamp the feedback voltage to the external reference voltage. The buffer pushes the poles of the main power transistor's gate and the main error amplifier's output high to the target frequency range and drives the main power transistor. The main power transistor provides output current through its drain across the entire load range according to the loop gain. The input terminal of the bias circuit is connected to the output terminal of the main error amplifier and the external power supply; the bias circuit is used to sample the current of the main power transistor to realize the adaptive bias of the buffer through the first bias voltage output terminal, and to realize the adaptive bias of the main error amplifier through the second bias voltage output terminal. The input terminal of the auxiliary error amplifier is connected to the first bias voltage output terminal of the bias circuit, and the output terminal of the auxiliary error amplifier is connected to the gate of the secondary power transistor; the source of the secondary power transistor is connected to the external power supply voltage; the auxiliary error amplifier is used to turn on and drive the secondary power transistor when the load of the low dropout linear regulator is higher than a preset threshold; the secondary power transistor is used to provide output current through its drain when the load is higher than the preset threshold. The input terminal of the resistor feedback network is connected to the drain of the main power transistor; the resistor feedback network is used to divide the output voltage of the low dropout linear regulator and feed it back to the non-inverting input terminal of the error amplifier; The input terminal of the auxiliary path is connected to the internal node voltage of the main error amplifier, and the output terminal of the auxiliary path is connected to the gate of the main power transistor. The auxiliary path is used to form a feedforward path to generate zeros for loop stability compensation.

[0008] The above-mentioned at least one technical solution adopted in this invention can achieve the following beneficial effects: This invention dynamically adjusts the bias current of the main error amplifier and the buffer according to the load conditions, achieving automatic switching between low static power consumption under light load and high bandwidth and high slew rate under heavy load. Simultaneously, the buffer pushes the non-dominant poles inside the low-dropout linear regulator to a higher frequency to drive the main power transistor, effectively improving system stability. Building upon this, an auxiliary error amplifier and a secondary power transistor are added. When the load current is small, the output current is provided only through the main error amplifier, the main power transistor, and the auxiliary path. When the load current exceeds the threshold current, the low-dropout linear regulator transforms into a three-stage structure, where the secondary power transistor can quickly provide most of the current, increasing the loop gain of the low-dropout linear regulator and lowering the dominant pole frequency. Furthermore, as the load current of the low-dropout linear regulator increases, the secondary pole frequency increases, further enhancing the stability of the low-dropout linear regulator. The feedforward zero-point compensation based on the auxiliary path can be combined with conventional Miller compensation, significantly reducing the size of the compensation capacitor and increasing the system bandwidth. The low-dropout linear regulator of this invention has a larger bandwidth and stronger transient charge and discharge capability. Therefore, the output voltage has a smaller overshoot / undershoot voltage and a faster recovery time when the load current is transiently switched. It takes into account low power consumption, high stability and excellent transient response performance across the entire load range.

[0009] In this invention, the main error amplifier of the low-dropout linear regulator employs a symmetrical operational amplifier (OPA) with Class-AB output to improve the slew rate of the OPA output stage. The addition of a cross-coupling structure and adaptive biasing of the tail current source effectively reduces static power consumption. The buffer uses a rail-to-rail input / output flip-flop voltage follower, effectively pushing the internal poles of the low-dropout linear regulator to higher frequencies and driving the main power transistor, thus significantly improving system stability. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0011] Figure 1 This invention provides a schematic diagram of a fully integrated LDO application scenario; Figure 2 A schematic diagram of a fully integrated low-dropout linear regulator system provided by the present invention; Figure 3 A schematic diagram of a fully integrated low-dropout linear regulator provided by the present invention; Figure 4 A schematic diagram of the overall circuit of the main error amplifier EA1 provided by the present invention; Figure 5A schematic diagram of phase margin under light and heavy load conditions provided by the present invention; Figure 6 A schematic diagram of simulation results for a linear adjustment rate provided by the present invention; Figure 7 A schematic diagram of simulation results for a load regulation rate provided by the present invention; Figure 8 This is a schematic diagram of the simulation results of a load current jump provided by the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0013] Currently, there are various technical solutions available for the design of fully integrated LDOs. Figure 1 This is a schematic diagram of a fully integrated LDO application scenario in this invention. Figure 1 The fully integrated LDO in the optical receiver powers the TIA (Transient Ionizer) of the analog front-end. The current signal collected by the photodiode is converted into a voltage signal by the TIA. The single-ended signal is then converted into a differential signal by the S2D module before further signal processing to obtain the output signal. To reduce the power supply ripple of the TIA, the external power supply VDD1 is powered by the LDO after power supply ripple suppression. Other circuits that are not sensitive to power supply ripple can be directly powered by the external power supply VDD2.

[0014] Achieving fast response primarily involves using transconductance enhancement techniques to increase unity-gain bandwidth, thereby reducing the response and settling times of the LDO by increasing loop bandwidth. However, this may sacrifice low-frequency gain, easily encounter stability issues, and have limited optimization effects. Furthermore, adding an additional complex transient enhancement module may not be effective within a short timeframe and is limited by power consumption. Digital-assisted solutions offer fast response and design flexibility, but their main drawback is the introduction of significant switching noise and voltage ripple to the output. The high-frequency components of the switching noise may interfere with other sensitive modules on the same chip through substrate coupling, which is unacceptable in many analog / RF loads with high power purity requirements.

[0015] It is evident that existing solutions have significant shortcomings when applied to high-performance TIA power supply, mainly in the following aspects: First, under the constraint of low static power consumption, the gain-bandwidth product of the error amplifier is severely limited, resulting in slow loop response speed, inability of the LDO to respond in time, and significant overshoot and undershoot of the output voltage; Second, technologies based on dynamic bias or auxiliary fast path rely on the delay of the detection circuit, and significant transient current spikes and switching noise are injected into the power rail and output terminal at the moment the auxiliary path is turned on and off. These additional high-frequency noises directly degrade the input reference noise of the TIA, thereby reducing the sensitivity of the optical receiving link; Third, digital control or mixed-signal LDO solutions can theoretically achieve extremely fast response speed by controlling the power transistor array through digital loop, but the switching operation of the power transistors introduces a large amount of voltage ripple and switching noise to the output terminal, greatly degrading the system performance.

[0016] Therefore, existing technologies, in attempting to resolve the conflict between "low power consumption" and "fast response" in fully integrated LDOs, often sacrifice one aspect for the other, either by reducing response speed, introducing new noise sources, or increasing static power consumption and design complexity. For applications like optical communication TIAs, which have extremely high requirements for power supply noise, transient performance, and static power consumption, an ideal solution is still lacking. An innovative fully integrated LDO architecture is needed that can achieve fast transient response speeds under extremely low static power consumption conditions, while maintaining the inherent high power purity, high PSR, and low output noise characteristics of analog LDOs, fundamentally meeting the critical requirements of power management units in high-speed optical communication receiver links.

[0017] The technical problem this invention aims to solve is how to overcome the fundamental contradiction between low quiescent current and high loop response speed under fully integrated conditions. It designs an LDO circuit that maintains extremely low quiescent power consumption while possessing fast and precise voltage regulation capability matching the load switching speed, thereby effectively suppressing output voltage overshoot and undershoot, and avoiding the introduction of additional switching noise, complex control logic, or excessive sensitivity to process variations. Simultaneously, the design of the compensation capacitor needs to comprehensively consider the LDO's loop stability, overshoot / undershoot voltage, and recovery time. A larger compensation capacitor can bring better stability and smaller overshoot / undershoot voltage, but it will severely reduce the LDO's bandwidth, leading to a longer recovery time; a smaller compensation capacitor increases the LDO's loop bandwidth and shortens the recovery time, but it will result in poorer loop stability and larger overshoot / undershoot voltage. The core of the above problems lies in the fact that Miller compensation under low-power design and the excessively low output pole frequency under light load severely limit the LDO's bandwidth, as well as insufficient slew rate in low-power applications.

[0018] To alleviate the trade-offs in the design of Capless LDOs, a more advanced loop compensation scheme and system architecture are needed, focusing on increasing the LDO's bandwidth and slew rate to improve its transient response. To resolve this trade-off, this invention employs a low-power dynamically biased primary error amplifier, a high-slew-rate buffer, a secondary power transistor, a current comparator, and auxiliary paths to improve the loop's response speed and recovery time under low quiescent current, achieving smaller overshoot / undershoot.

[0019] The technical solutions provided by the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figure 2 This is a schematic block diagram of a fully integrated low-dropout linear regulator system according to the present invention. Figure 2 As can be seen, the LDO of this invention mainly includes a main error amplifier EA1, an adaptive bias circuit, a buffer, and a main power transistor M. P1 Auxiliary error amplifier EA2, secondary power transistor M P2 Resistive feedback network (first feedback resistor) R F1 Second feedback resistor R F2 ) and auxiliary paths, and also a compensation network (first capacitor C) is provided. M Second capacitor C F ).

[0021] The non-inverting input of the main error amplifier is connected to the output of the resistive feedback network, the inverting input is connected to an external reference voltage, and the output is connected to the input of a buffer. The output of the buffer is connected to the gate of the main power transistor. The source of the main power transistor is connected to an external power supply voltage. The main error amplifier provides loop gain to clamp the feedback voltage to the external reference voltage. The buffer pushes the poles of the gate of the main power transistor and the output of the main error amplifier to the target frequency range and drives the main power transistor. The main power transistor provides output current through its drain across the entire load range according to the loop gain.

[0022] The input terminal of the bias circuit is connected to the output terminal of the main error amplifier and the external power supply; the bias circuit is used to sample the current of the main power transistor to realize the adaptive bias of the buffer through the first bias voltage output terminal, and to realize the adaptive bias of the main error amplifier through the second bias voltage output terminal.

[0023] The input terminal of the auxiliary error amplifier is connected to the first bias voltage output terminal of the bias circuit, and the output terminal of the auxiliary error amplifier is connected to the gate of the secondary power transistor. The source of the secondary power transistor is connected to the external power supply voltage. The auxiliary error amplifier is used to turn on and drive the secondary power transistor when the first bias voltage is greater than the target threshold. The secondary power transistor is used to provide output current through its drain. The first bias voltage increases with the increase of the load current.

[0024] The input terminal of the resistor feedback network is connected to the drain of the main power transistor; the resistor feedback network is used to divide the output voltage of the low dropout linear regulator and feed it back to the non-inverting input terminal of the error amplifier.

[0025] The input terminal of the auxiliary path is connected to the internal node voltage of the main error amplifier, and the output terminal of the auxiliary path is connected to the gate of the main power transistor. The auxiliary path is used to form a feedforward path to generate zeros for loop stability compensation.

[0026] Figure 3 This is a schematic diagram of a fully integrated low-dropout linear regulator according to the present invention. Figure 3 As can be seen, in one or more embodiments of the present invention, an adaptively biased low-power main error amplifier serves as the first gain stage of the LDO, and the main error amplifier is connected to the main power transistor M via a buffer. P1 For driving, an auxiliary error amplifier serves as the second gain stage of the LDO, and the auxiliary error amplifier powers the secondary power transistor M. P2 Driven. In the LDO of this invention, M P2 It will adaptively turn on and off according to the magnitude of the load current.

[0027] Under light load, the second gain stage operates in the deep linear region, at which point M... P2 Turn off when the load current is less than the set threshold current I. ON At this time, the LDO has a two-stage structure consisting of a main path and an auxiliary path. Furthermore, to further improve the efficiency and transient performance of the LDO under no-load conditions, the power transistor M... P1 A buffer is inserted between the first gain stage and the power transistor M to reduce its load. P1 The size of the buffer also provides the main power transistor M. P1 and the eighteenth MOSFET M 18 The adaptive bias voltage of the body bias improves the system bandwidth and transient response of the LDO. When the load current is greater than I... ON In this case, the LDO of the present invention will transform into a three-stage structure. The increased loop gain of the LDO lowers the frequency of the primary pole, and as the load current of the LDO increases, the frequency of the secondary pole increases, thereby enhancing the stability of the LDO.

[0028] Specifically, in one or more embodiments of the present invention, the main error amplifier includes: a symmetrical operational amplifier, a cross-coupled structure, and a bias MOSFET; the symmetrical operational amplifier is used to provide gain; the cross-coupled structure is used to allocate more current to the output stage of the symmetrical operational amplifier in transient conditions to improve the slew rate; and the bias MOSFET is used to connect a bias voltage.

[0029] The symmetrical operational amplifier includes a first MOSFET, a second MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET.

[0030] An external power supply is connected to the source of the first MOSFET and the source of the second MOSFET, providing a fixed tail current flowing into the branches of the first MOSFET and the second MOSFET.

[0031] The gate of the first MOSFET is connected to the external reference voltage as the negative input terminal, and the drain of the first MOSFET is connected to the gate and drain of the ninth MOSFET. The gate of the second MOSFET is connected to the output terminal of the resistor feedback network as the positive input terminal, and the drain of the second MOSFET is connected to the gate and drain of the tenth MOSFET. The cross-coupling structure and the bias MOSFET are connected between the positive input terminal and the negative input terminal.

[0032] The first MOSFET and the second MOSFET distribute the tail current source current according to the difference in their gate voltages; the second MOSFET converts the feedback voltage division change into a current change.

[0033] The gate of the ninth MOSFET is connected to the gate of the eleventh MOSFET, and the source of the ninth MOSFET is grounded; the ninth MOSFET forms a current mirror structure to convert the branch current of the first MOSFET into voltage.

[0034] The gate of the tenth MOSFET is connected to the gate of the twelfth MOSFET, and the source of the tenth MOSFET is grounded; the tenth MOSFET forms a current mirror structure to convert the branch current of the second MOSFET into voltage.

[0035] The drain of the eleventh MOSFET is connected to the gate and drain of the thirteenth MOSFET, and the source of the eleventh MOSFET is grounded; the eleventh MOSFET mirrors the current of the branch of the ninth MOSFET.

[0036] The drain of the twelfth MOSFET is connected to the drain of the fourteenth MOSFET and the input of the buffer, and the source of the twelfth MOSFET is grounded; the twelfth MOSFET mirrors the current of the branch of the tenth MOSFET.

[0037] The gate of the thirteenth MOSFET is connected to the gate of the fourteenth MOSFET, and the source of the thirteenth MOSFET is connected to an external power supply. The thirteenth MOSFET forms a current mirror structure to convert the current of the eleventh MOSFET branch into a voltage. The source of the fourteenth MOSFET is connected to the operating power supply. The fourteenth MOSFET mirrors the current of the thirteenth MOSFET branch.

[0038] Furthermore, in one or more embodiments of the present invention, the cross-coupling structure includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor.

[0039] The gate of the third MOSFET is connected to an external reference voltage. The drain of the third MOSFET is connected to the gate and drain of the seventh MOSFET and the gate of the sixth MOSFET. The source of the third MOSFET is connected to the source of the fourth MOSFET. The third MOSFET and the fourth MOSFET distribute the tail current source current according to the difference in their gate voltages.

[0040] The gate of the fourth MOSFET is connected to the output of the resistor feedback network, and the drain of the fourth MOSFET is connected to the gate and drain of the eighth MOSFET and the gate of the fifth MOSFET; the fourth MOSFET converts the feedback voltage division change into a current change.

[0041] The source of the seventh MOSFET is grounded; the seventh MOSFET forms a current mirror structure to convert the current in the third MOSFET branch into voltage; the source of the eighth MOSFET is grounded; the eighth MOSFET forms a current mirror structure to convert the current in the fourth MOSFET branch into voltage.

[0042] The drain of the fifth MOSFET is connected to the connection line between the drains of the first and ninth MOSFETs, and the source of the fifth MOSFET is grounded; the fifth MOSFET mirrors the current of the branch of the eighth MOSFET.

[0043] The drain of the sixth MOSFET is connected to the connection line between the drains of the second and tenth MOSFETs, and the source of the sixth MOSFET is grounded; the sixth MOSFET mirrors the current of the branch of the seventh MOSFET.

[0044] The bias MOSFETs include a twenty-fourth MOSFET and a twenty-fifth MOSFET. The drain of the twenty-fourth MOSFET is connected to the source of the first MOSFET and the source of the second MOSFET. The gate of the twenty-fourth MOSFET is connected to the second bias voltage output terminal of the bias circuit. The source of the twenty-fourth MOSFET is connected to an external power supply. The drain of the twenty-fifth MOSFET is connected to the source of the third MOSFET and the source of the fourth MOSFET. The gate of the twenty-fifth MOSFET is connected to the second bias voltage output terminal of the bias circuit. The source of the twenty-fifth MOSFET is connected to an external power supply.

[0045] The overall circuit diagram of the main error amplifier EA1 is as follows: Figure 4 As shown, it includes M1~M 14 and bias MOSFET M 24 and M 25 This is used to provide loop gain, and the architecture adaptively switches according to the load current. Low-frequency gain can be improved by properly allocating current without affecting the slew rate. This error amplifier has four input transistor pairs, M1~M4, where M3 and M4 are adaptive auxiliary transconductance input pairs; M5~M8 are auxiliary branches. M4 converts the input voltage into current. I d , I d The current flowing through diode M8 is converted into voltage, and this converted voltage is received by M6 to generate a transconductance-enhancing current in M2. M1 and M2 are the main transconductance stages, converting the input differential voltage into differential current. The current in M2 is M... 10 The sum of M6 and M7, due to the inflow of auxiliary branch current, leads to M... 10 The reduced current ultimately reduces the current mirrored to the output stage, thereby increasing the output impedance and reducing quiescent power consumption. To further reduce the quiescent current of the error amplifier, the four input transistor pairs are divided into two groups, each biased by a different current source. The main circuit uses both a constant current source and an adaptive current source to provide current, while the auxiliary branch is biased by a sampled adaptive current source. When the circuit is unloaded, M... 24 and M 25 When the LDO is almost shut down, the adaptive auxiliary branch is closed; when the LDO is connected to the load, the adaptive auxiliary circuit starts working by connecting to the adaptive current source, and the adaptive auxiliary circuit enters the working mode.

[0046] In one or more embodiments of the present invention, the bias circuit includes: an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, and a twenty-third MOS transistor.

[0047] The gate of the eighteenth MOSFET is connected to the output of the main error amplifier. The drain of the eighteenth MOSFET is connected to the gate and drain of the nineteenth MOSFET. The source of the eighteenth MOSFET is connected to an external power supply. The body of the eighteenth MOSFET is connected to the drain of the sixteenth MOSFET. The eighteenth MOSFET is used to sample the current of the main power transistor.

[0048] The source of the nineteenth MOSFET is grounded; the nineteenth MOSFET forms a current mirror structure to convert the sampling current of the eighteenth MOSFET into the first bias voltage; the input of the auxiliary error amplifier is connected to the first bias voltage output of the bias circuit.

[0049] The gate of the twentieth MOSFET is connected to the gate of the nineteenth MOSFET, and the drain of the twentieth MOSFET is connected to the gate and drain of the twenty-third MOSFET. The source of the twentieth MOSFET is grounded. The current of the twentieth MOSFET mirrors that of the nineteenth MOSFET to provide bias current for the twenty-third MOSFET.

[0050] The gate of the 23rd MOSFET is connected to the gate of the 24th MOSFET and the gate of the 25th MOSFET. The 24th MOSFET mirrors the current of the 23rd MOSFET branch, and the 25th MOSFET mirrors the current of the 23rd MOSFET branch. The source of the 23rd MOSFET is connected to an external power supply voltage. The 23rd MOSFET provides a second bias voltage to the tail current source of the main error amplifier through its gate.

[0051] Corresponding to Figure 3 In the adaptive bias circuit, M is included. 18 M 19 M 20 and M 23 M 18 This is a sampling MOSFET used to sample the power transistor M. P1 The current, then through the current mirror M 20 The sampled current is injected into the main error amplifier to achieve adaptive bias.

[0052] In one or more embodiments of the present invention, the buffer includes: a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, and a first resistor.

[0053] The gate of the fifteenth MOSFET is connected to the output of the main error amplifier, the drain of the fifteenth MOSFET is connected to the drain of the twenty-first MOSFET, the source of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the body of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET. The fifteenth MOSFET is used to form a source follower structure to reduce the output impedance.

[0054] The gate of the sixteenth MOSFET is connected to the connection line between the source of the fifteenth MOSFET and the drain of the sixteenth MOSFET, and the source of the sixteenth MOSFET is connected to an external power supply; the sixteenth MOSFET and the fifteenth MOSFET are used to form a negative feedback loop to reduce the output impedance.

[0055] The gate and drain of the seventeenth MOSFET are connected to the gate of the main power transistor and the drain of the twenty-second MOSFET, respectively. The source of the seventeenth MOSFET is connected to the connection line between the source of the fifteenth MOSFET and the drain of the sixteenth MOSFET. The body of the seventeenth MOSFET is connected to the drain of the sixteenth MOSFET. The seventeenth MOSFET and the fifteenth MOSFET are used to realize the rail-to-rail output swing.

[0056] The gate of the 21st MOSFET is connected to the first bias voltage output terminal, and the source of the 21st MOSFET is grounded; the 21st MOSFET provides bias current to the 15th MOSFET; the gate of the 22nd MOSFET is connected to the first bias voltage output terminal, and the source of the 22nd MOSFET is grounded; the 22nd MOSFET provides bias current to the 17th MOSFET.

[0057] The first end of the first resistor is connected to an external power supply, and the second end of the first resistor is connected to the drain of the sixteenth MOSFET.

[0058] Corresponding to Figure 3 In the buffer, M is contained 15 M 16 M 17 M 21 M 22 R1 and R1 are used to isolate EA1 from the power transistor and push the gate pole of the main power transistor out of band. M 21 Provides the buffer's bias current, which can replicate M 18 The sampling current enables adaptive biasing; M 15 and M 17 These are the input and output tubes, which work together to achieve rail-to-rail input and output swing of the buffer.

[0059] In one or more embodiments of the present invention, the auxiliary error amplifier includes: a twenty-eighth MOS transistor, a twenty-ninth MOS transistor, and a thirtieth MOS transistor.

[0060] The gate of the 28th MOSFET is connected to the output terminal of the first bias voltage, the drain of the 28th MOSFET is connected to the gate of the secondary power transistor, and the source of the 28th MOSFET is grounded; the current of the main power transistor is sampled by the 28th MOSFET mirror bias circuit.

[0061] The current inflow terminal of the bias current source is connected to the gate and drain of the 29th MOSFET, and the current outflow terminal of the bias current source is grounded; providing a fixed bias current for the 29th MOSFET.

[0062] The gate and drain of the 29th MOSFET are connected to the gate of the 30th MOSFET, and the source of the 29th MOSFET is connected to an external power supply; the 29th MOSFET forms a current mirror structure to convert the bias current into voltage.

[0063] The drain of the 30th MOSFET is connected to the gate of the secondary power transistor, and the source of the 30th MOSFET is connected to an external power supply. The current of the 30th MOSFET mirrored by the 29th MOSFET is compared with the current mirrored by the 28th MOSFET to adjust the on / off state of the secondary power transistor.

[0064] Corresponding to Figure 3In the middle, the auxiliary error amplifier EA2 contains M 28 M 29 and M 30 Used to drive the secondary power transistor and to turn the power transistor M on and off under different load currents. P2 M 28 Copy M 18 Current and M 30 Comparison, when M 28 When the current is small, EA2 outputs a high level, M P1 Off, or M P1 Open.

[0065] For a resistive feedback network, in one or more embodiments of the present invention, it includes: a first feedback resistor and a second feedback resistor. A first terminal of the first feedback resistor is connected to the non-inverting input terminal of the main error amplifier, and a second terminal of the first feedback resistor is grounded. A first terminal of the second feedback resistor is connected to the output terminal of the low-dropout error amplifier, and a second terminal of the second feedback resistor is connected to the first terminal of the first feedback resistor. Corresponding to... Figure 3 In the middle, the resistive feedback network includes a first feedback resistor. R F1 Second feedback resistor R F2 .

[0066] In one or more embodiments of the present invention, the auxiliary path includes a 26th MOS transistor and a 27th MOS transistor. The gate of the 26th MOS transistor is connected to the gate of the 13th MOS transistor, the drain of the 26th MOS transistor is connected to the drain of the 27th MOS transistor, and the source of the 26th MOS transistor is connected to an external power supply. The gate of the 27th MOS transistor is connected to the gate of the 10th MOS transistor, and the source of the 26th MOS transistor is grounded. Therefore, the first input terminal of the auxiliary path is connected to the junction voltage V in the main error amplifier. FP The second input terminal of the auxiliary path is connected to the node voltage V in the main error amplifier. FN The node voltage V FP The junction voltage V is the difference between the external power supply voltage and the gate-source voltage of the thirteenth MOSFET. FN This is the sum of the ground voltage and the gate-source voltage of the tenth MOSFET. The twenty-sixth and twenty-seventh MOSFETs are used to form a feedforward auxiliary path to generate zeros, improving loop stability. (Corresponding to...) Figure 3 In this context, the auxiliary pathway includes M 26 and M 27 It is connected in parallel with the buffer to generate a zero point for loop compensation under light load.

[0067] Furthermore, in one or more embodiments of the present invention, the low-dropout linear regulator may further include a compensation network, the compensation network comprising: a first capacitor and a second capacitor; a first terminal of the first capacitor is connected to the output terminal of the low-dropout linear regulator, and a second terminal of the first capacitor is connected to the output terminal of the main error amplifier. A first terminal of the second capacitor is connected to the output terminal of the low-dropout linear regulator, and a second terminal of the second capacitor is connected to the output terminal of the resistive feedback network; the first and second capacitors are used to perform loop stability compensation for the low-dropout linear regulator. (Corresponding to...) Figure 3 In the compensation network, the first capacitor C is included. M Second capacitor C F .

[0068] Compared to traditional Miller compensation schemes, this invention employs a combination of feedforward zero-point compensation and Miller compensation, significantly reducing the size of the compensation capacitor and increasing system bandwidth. Compared to traditional LDO architectures and compensation schemes, the LDO designed in this invention has a larger bandwidth and stronger transient charge / discharge capability. During transient switching of the load current, the LDO's output voltage exhibits lower overshoot / undershoot voltage and faster recovery time.

[0069] For applications in optical communication systems, this invention designs a low-power, fast-response fully integrated LDO, including a low-power main error amplifier EA1, a high-slew rate buffer, a main power transistor, an auxiliary path, a secondary power transistor, and a driving circuit EA2 for the secondary power transistor. The main error amplifier EA1 provides loop gain; the buffer drives the main power transistor and improves loop stability; the main power transistor provides output current under full load; the secondary power transistor provides output current under medium and heavy load; the secondary power transistor driving circuit EA2 drives the secondary power transistor; and the auxiliary path and compensation loop provide stability compensation for the LDO loop. This invention achieves a 1.5V output voltage at 1.8V. This LDO exhibits lower undershoot, faster recovery time, better transient characteristics, and smaller chip area overhead. The beneficial effects are shown in Table 1.

[0070] Table 1 Indicator Achievement Figure 5 This is a schematic diagram illustrating the phase margin under light and heavy load conditions according to the present invention. Figure 5 The horizontal axis represents the frequency from low frequency to 1GHz, and the vertical axis represents the loop gain and phase margin, respectively. The solid line is the Bode plot curve when the load current is 100mA and the phase margin is 95°; the dashed line is the Bode plot curve when the load current is 100μA and the phase margin is 61°. It can be seen that the low dropout linear regulator of the present invention can maintain stability under both heavy and light load conditions.

[0071] Figure 6 This is a schematic diagram of the simulation results of a linear adjustment rate in this invention. Figure 6 The horizontal axis represents the power supply voltage variation between 1.7V and 2V, and the vertical axis represents the output voltage variation of the low dropout linear regulator between 1.499929V and 1.499986V. The calculated linear regulation is 0.188mV / V. The small linear regulation indicates that it is not sensitive to the power supply voltage and can effectively suppress power supply voltage fluctuations.

[0072] Figure 7 This is a schematic diagram of the simulation results of a load regulation rate according to the present invention. Figure 7 The horizontal axis represents the load current variation between 100μA and 100mA, and the vertical axis represents the output voltage variation of the low dropout linear regulator between 1.49955V and 1.49995V. The calculated load regulation is 0.004 mV / mA. The small load regulation indicates a strong ability to regulate the load current and maintain stable output voltage over a wide load current range.

[0073] Figure 8 This is a schematic diagram of the simulation results of a load current jump in this invention. Figure 8 The horizontal axis represents time, and the vertical axis represents the output voltage change of the low dropout linear regulator. When the load current jumps from 100μA to 100mA with a 100ns transition edge, the undershoot voltage of the low dropout linear regulator is 276mV, and the settling time is 113ns. When the load current jumps from 100mA to 100μA with a 100ns transition edge, the overshoot voltage of the low dropout linear regulator is 186mV, and the settling time is 398ns. The shorter settling time can better resist load current fluctuations and can be applied to application scenarios with high recovery time requirements.

[0074] It should also be noted that the terms "comprising," "including," or any other variations thereof in this invention are intended to cover non-exclusive inclusion, that is, in addition to the elements listed in this invention, other elements not expressly listed may also be included.

[0075] The various embodiments in this invention are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. Each embodiment focuses on describing the differences from other embodiments.

[0076] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A fully integrated low-dropout linear regulator, characterized in that, include: Main error amplifier, bias circuit, buffer, main power transistor, auxiliary error amplifier, secondary power transistor, resistor feedback network and auxiliary path; The non-inverting input of the main error amplifier is connected to the output of the resistive feedback network, the inverting input is connected to an external reference voltage, and the output is connected to the input of a buffer. The output of the buffer is connected to the gate of the main power transistor. The source of the main power transistor is connected to an external power supply voltage. The main error amplifier provides loop gain to clamp the feedback voltage to the external reference voltage. The buffer pushes the poles of the main power transistor's gate and the main error amplifier's output high to the target frequency range and drives the main power transistor. The main power transistor provides output current through its drain across the entire load range according to the loop gain. The input terminal of the bias circuit is connected to the output terminal of the main error amplifier and the external power supply; the bias circuit is used to sample the current of the main power transistor to realize the adaptive bias of the buffer through the first bias voltage output terminal, and to realize the adaptive bias of the main error amplifier through the second bias voltage output terminal. The input terminal of the auxiliary error amplifier is connected to the first bias voltage output terminal of the bias circuit, and the output terminal of the auxiliary error amplifier is connected to the gate of the secondary power transistor. The source of the secondary power transistor is connected to the external power supply voltage. The auxiliary error amplifier is used to turn on and drive the secondary power transistor when the first bias voltage is greater than the target threshold. The secondary power transistor is used to provide output current through its drain. The first bias voltage increases with the increase of the load current. The input terminal of the resistor feedback network is connected to the drain of the main power transistor; the resistor feedback network is used to divide the output voltage of the low dropout linear regulator and feed it back to the non-inverting input terminal of the error amplifier; The input terminal of the auxiliary path is connected to the internal node voltage of the main error amplifier, and the output terminal of the auxiliary path is connected to the gate of the main power transistor. The auxiliary path is used to form a feedforward path to generate zeros for loop stability compensation.

2. The fully integrated low-dropout linear regulator as described in claim 1, characterized in that, The main error amplifier includes: a symmetrical operational amplifier, a cross-coupling structure, and a bias MOSFET; the symmetrical operational amplifier is used to provide gain; the cross-coupling structure is used to allocate more current to the output stage of the symmetrical operational amplifier in transient conditions to improve the slew rate; the bias MOSFET is used to connect the bias voltage; The symmetrical operational amplifier includes a first MOSFET, a second MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET; An external power supply is connected to the source of the first MOSFET and the source of the second MOSFET to provide a fixed tail current flowing into the branches of the first MOSFET and the second MOSFET. The gate of the first MOSFET is connected to the external reference voltage as the negative input terminal, and the drain of the first MOSFET is connected to the gate and drain of the ninth MOSFET; the gate of the second MOSFET is connected to the output terminal of the resistor feedback network as the positive input terminal, and the drain of the second MOSFET is connected to the gate and drain of the tenth MOSFET; the cross-coupling structure and the bias MOSFET are connected between the positive input terminal and the negative input terminal. The first MOSFET and the second MOSFET distribute the current of the tail current source according to the difference in their gate voltages; the second MOSFET converts the feedback voltage division change into a current change. The gate of the ninth MOSFET is connected to the gate of the eleventh MOSFET, and the source of the ninth MOSFET is grounded; the ninth MOSFET forms a current mirror structure to convert the branch current of the first MOSFET into voltage. The gate of the tenth MOSFET is connected to the gate of the twelfth MOSFET, and the source of the tenth MOSFET is grounded; the tenth MOSFET forms a current mirror structure to convert the branch current of the second MOSFET into voltage. The drain of the eleventh MOSFET is connected to the gate and drain of the thirteenth MOSFET, and the source of the eleventh MOSFET is grounded; the eleventh MOSFET mirrors the current of the branch of the ninth MOSFET. The drain of the twelfth MOSFET is connected to the drain of the fourteenth MOSFET and the input terminal of the buffer, and the source of the twelfth MOSFET is grounded; the twelfth MOSFET mirrors the current of the branch of the tenth MOSFET. The gate of the thirteenth MOSFET is connected to the gate of the fourteenth MOSFET, and the source of the thirteenth MOSFET is connected to an external power supply. The thirteenth MOSFET forms a current mirror structure to convert the current of the eleventh MOSFET branch into a voltage. The source of the fourteenth MOSFET is connected to the operating power supply. The fourteenth MOSFET mirrors the current of the thirteenth MOSFET branch.

3. The fully integrated low-dropout linear regulator as described in claim 2, characterized in that, The cross-coupling structure includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; The gate of the third MOSFET is connected to an external reference voltage. The drain of the third MOSFET is connected to the gate and drain of the seventh MOSFET and the gate of the sixth MOSFET. The source of the third MOSFET is connected to the source of the fourth MOSFET. The third MOSFET and the fourth MOSFET distribute the tail current source current according to the difference in their gate voltages. The gate of the fourth MOSFET is connected to the output of the resistor feedback network, and the drain of the fourth MOSFET is connected to the gate and drain of the eighth MOSFET and the gate of the fifth MOSFET; the fourth MOSFET converts the feedback voltage division change into a current change. The source of the seventh MOSFET is grounded; the seventh MOSFET forms a current mirror structure to convert the current in the third MOSFET branch into voltage; the source of the eighth MOSFET is grounded; the eighth MOSFET forms a current mirror structure to convert the current in the fourth MOSFET branch into voltage; The drain of the fifth MOSFET is connected to the connection line between the drains of the first and ninth MOSFETs, and the source of the fifth MOSFET is grounded; the fifth MOSFET mirrors the current of the branch of the eighth MOSFET. The drain of the sixth MOSFET is connected to the connection line between the drains of the second and tenth MOSFETs, and the source of the sixth MOSFET is grounded; the sixth MOSFET mirrors the current of the branch of the seventh MOSFET. The bias MOSFETs include the twenty-fourth MOSFET and the twenty-fifth MOSFET; The drain of the 24th MOSFET is connected to the source of the first MOSFET and the source of the second MOSFET. The gate of the 24th MOSFET is connected to the second bias voltage output terminal of the bias circuit. The source of the 24th MOSFET is connected to an external power supply. The drain of the 25th MOSFET is connected to the source of the third MOSFET and the source of the fourth MOSFET. The gate of the 25th MOSFET is connected to the second bias voltage output terminal of the bias circuit. The source of the 25th MOSFET is connected to an external power supply.

4. The fully integrated low-dropout linear regulator as described in claim 3, characterized in that, The bias circuit includes: the eighteenth MOSFET, the nineteenth MOSFET, the twentieth MOSFET, and the twenty-third MOSFET; The gate of the eighteenth MOSFET is connected to the output of the main error amplifier. The drain of the eighteenth MOSFET is connected to the gate and drain of the nineteenth MOSFET. The source of the eighteenth MOSFET is connected to an external power supply. The body of the eighteenth MOSFET is connected to the drain of the sixteenth MOSFET. The eighteenth MOSFET is used to sample the current of the main power transistor. The source of the nineteenth MOSFET is grounded; the nineteenth MOSFET forms a current mirror structure to convert the sampling current of the eighteenth MOSFET into the first bias voltage; the input of the auxiliary error amplifier is connected to the first bias voltage output of the bias circuit. The gate of the twentieth MOSFET is connected to the gate of the nineteenth MOSFET, the drain of the twentieth MOSFET is connected to the gate and drain of the twenty-third MOSFET, and the source of the twentieth MOSFET is grounded; the current of the twentieth MOSFET mirrors that of the nineteenth MOSFET to provide bias current for the twenty-third MOSFET. The gate of the 23rd MOSFET is connected to the gate of the 24th MOSFET and the gate of the 25th MOSFET. The 24th MOSFET mirrors the current of the 23rd MOSFET branch, and the 25th MOSFET mirrors the current of the 23rd MOSFET branch. The source of the 23rd MOSFET is connected to an external power supply voltage. The 23rd MOSFET provides a second bias voltage to the tail current source of the main error amplifier through its gate.

5. The fully integrated low-dropout linear regulator as described in claim 1, characterized in that, The buffer includes: a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a twenty-first MOSFET, a twenty-second MOSFET, and a first resistor; The gate of the fifteenth MOSFET is connected to the output of the main error amplifier, the drain of the fifteenth MOSFET is connected to the drain of the twenty-first MOSFET, the source of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the body of the fifteenth MOSFET is connected to the drain of the sixteenth MOSFET. The fifteenth MOSFET is used to form a source follower structure to reduce the output impedance. The gate of the sixteenth MOSFET is connected to the connection line between the source of the fifteenth MOSFET and the drain of the sixteenth MOSFET, and the source of the sixteenth MOSFET is connected to an external power supply; the sixteenth MOSFET and the fifteenth MOSFET are used to form a negative feedback loop to reduce the output impedance. The gate and drain of the seventeenth MOSFET are connected to the gate of the main power transistor and the drain of the twenty-second MOSFET, respectively. The source of the seventeenth MOSFET is connected to the connection line between the source of the fifteenth MOSFET and the drain of the sixteenth MOSFET. The body of the seventeenth MOSFET is connected to the drain of the sixteenth MOSFET. The seventeenth MOSFET and the fifteenth MOSFET are used to realize the rail-to-rail output swing. The gate of the 21st MOSFET is connected to the output terminal of the first bias voltage, and the source of the 21st MOSFET is grounded; the 21st MOSFET provides bias current for the 15th MOSFET. The gate of the 22nd MOSFET is connected to the first bias voltage output terminal, and the source of the 22nd MOSFET is grounded; the 22nd MOSFET provides bias current for the 17th MOSFET. The first end of the first resistor is connected to an external power supply, and the second end of the first resistor is connected to the drain of the sixteenth MOSFET.

6. The fully integrated low-dropout linear regulator as described in claim 1, characterized in that, The auxiliary error amplifier includes: the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, and the thirtieth MOS transistor; The gate of the 28th MOSFET is connected to the output terminal of the first bias voltage, the drain of the 28th MOSFET is connected to the gate of the secondary power transistor, and the source of the 28th MOSFET is grounded; the current of the main power transistor is sampled by the 28th MOSFET mirror bias circuit. The current inflow terminal of the bias current source is connected to the gate and drain of the 29th MOSFET, and the current outflow terminal of the bias current source is grounded; providing a fixed bias current for the 29th MOSFET. The gate and drain of the 29th MOSFET are connected to the gate of the 30th MOSFET, and the source of the 29th MOSFET is connected to an external power supply; the 29th MOSFET forms a current mirror structure to convert the bias current into voltage. The drain of the 30th MOSFET is connected to the gate of the secondary power transistor, and the source of the 30th MOSFET is connected to an external power supply. The current of the 30th MOSFET mirrored by the 29th MOSFET is compared with the current mirrored by the 28th MOSFET to adjust the on / off state of the secondary power transistor.

7. The fully integrated low-dropout linear regulator as described in claim 1, characterized in that, The resistor feedback network includes: a first feedback resistor and a second feedback resistor; The first terminal of the first feedback resistor is connected to the non-inverting input terminal of the main error amplifier, and the second terminal of the first feedback resistor is grounded. The first end of the second feedback resistor is connected to the output of the low dropout error amplifier, and the second end of the second feedback resistor is connected to the first end of the first feedback resistor.

8. The fully integrated low-dropout linear regulator as described in claim 2, characterized in that, The auxiliary path includes: the twenty-sixth MOS transistor and the twenty-seventh MOS transistor; The gate of the 26th MOSFET is connected to the gate of the 13th MOSFET, the drain of the 26th MOSFET is connected to the drain of the 27th MOSFET, and the source of the 26th MOSFET is connected to an external power supply. The gate of the 27th MOSFET is connected to the gate of the 10th MOSFET, and the source of the 26th MOSFET is grounded. The 26th and 27th MOSFETs are used to form a feedforward auxiliary path to generate a zero point and improve loop stability.

9. The fully integrated low-dropout linear regulator as described in claim 1, characterized in that, It also includes a compensation network, which includes a first capacitor and a second capacitor; the first terminal of the first capacitor is connected to the output terminal of the low dropout linear regulator, and the second terminal of the first capacitor is connected to the output terminal of the main error amplifier. The first terminal of the second capacitor is connected to the output terminal of the low-dropout linear regulator, and the second terminal of the second capacitor is connected to the output terminal of the resistive feedback network; the first and second capacitors are used to perform loop stability compensation for the low-dropout linear regulator.

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