Adaptive capacitance compensation FVF type low dropout linear voltage regulator based on multiple feedback loops

Abstract

This invention discloses an adaptive capacitor-compensated FVF-type low-dropout linear regulator based on multiple feedback loops, belonging to the field of integrated circuit technology. The invention includes an output power transistor, a first feedback loop, and a second feedback loop. The input terminal of the first feedback loop is coupled to the output node, and the output terminal is coupled to the control terminal of the output power transistor, used to respond to changes in load current. The input terminal of the second feedback loop is coupled to the output node, and the output terminal is coupled to the first feedback loop. It includes an impedance element, which, together with the load capacitance at the output node, forms a zero-point generation network to generate zeros whose frequency varies with the load capacitance, thus compensating for the poles of the first feedback loop. This invention achieves loop stability without requiring large-value Miller compensation capacitors by introducing adaptive zeros associated with the load capacitance, significantly reducing chip area and improving loop bandwidth and transient response performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops. Background Technology

[0002] Low dropout linear regulators (LDOs) are widely used in portable electronic devices, wireless communication systems, and power management chips due to their simple structure, low output ripple, and low electromagnetic interference. With the continuous evolution of integrated circuit technology and the increasing complexity of application scenarios, higher requirements are being placed on the transient response speed, stability, and chip area of ​​LDOs.

[0003] The flip-flop (FVF) voltage follower architecture is widely used in LDO implementations due to its compact topology and fast dynamic response. A typical FVF LDO structure suitable for higher voltage applications is shown below. Figure 1 As shown, this FVF-type LDO includes transistors M0, M1, and M2, as well as an error amplifier unit EA. The FVF local feedback loop is formed by transistors M0, M1, and M2. Transistor M0, as a folded cascode device, weakens the direct coupling between the gate potential of M1 and the drain potential of M2, thereby achieving level shifting. Transistor M1, as the output stage power device, is responsible for supplying drive current to the load. To meet the drive capability requirements under high load current conditions, this MOS transistor typically has a large size, inevitably introducing a large parasitic capacitance. The error amplifier unit EA detects and amplifies the deviation signal between the output voltage and the reference voltage, and adjusts the output node voltage through the feedback path formed by transistor M2 to achieve voltage regulation control.

[0004] When the external load capacitance is large, the stability compensation design of FVF type LDOs is often quite complex. A common implementation is to set the gate node of the internal power transistor M1 as the dominant pole and use a Miller compensation strategy. However, under this compensation method, the required compensation capacitor C1 often needs to reach a large value. This not only significantly increases the chip layout area overhead, but also significantly compresses the loop bandwidth, thereby weakening the dynamic response performance of the LDO under transient load changes.

[0005] To improve stability, the error amplifier is separated from the internal loop of the FVF, so that the error amplifier loop is unaffected by the output load. For example... Figure 2As shown, the ratio of IB2 to the current flowing through M2, ID2 / IB2, is the same as the width-to-length ratio of M4 and M2 to ensure that their gate-source voltages VGS2 and VGS4 are the same. The error amplifier A1 controls the source voltage of M4 to the target voltage VREF through a negative feedback loop. Since the gate voltages of M2 and M4 are the same, ignoring the channel length modulation effect, their source voltages should also be the same, thus ensuring that the output of the FVF LDO is the target voltage value VREF. Although this scheme isolates the error amplifier loop, the stability compensation problem of the internal loop of the FVF still exists. The internal loop of the FVF still faces the compensation contradiction between the gate parasitic capacitance pole of the power transistor M1 and the output load capacitance pole, and still needs to rely on a large Miller compensation capacitor C1 to maintain stability. Therefore, the technical problem of large compensation capacitor area and limited loop bandwidth has not been fundamentally solved.

[0006] In summary, how to reduce the area of ​​the compensation capacitor, increase the loop bandwidth, and optimize the transient response performance while ensuring the stability of the FVF type LDO is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The present invention aims to provide an adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops, in order to solve the technical problems of existing FVF type LDOs that require the use of large-value Miller compensation capacitors to ensure stability, resulting in large chip area, narrow loop bandwidth and poor transient response performance.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] An adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops includes:

[0010] The output power transistor, whose source or drain is connected to the output node, is used to provide output current to the load;

[0011] The first feedback loop has its input end coupled to the output node and its output end coupled to the control end of the output power transistor, which is used to respond to changes in load current and adjust the conduction state of the output power transistor.

[0012] The second feedback loop has its input coupled to the output node and its output coupled to the first feedback loop. The second feedback loop includes an impedance element, which together with the load capacitance at the output node forms a zero-point generation network. The zero-point generation network is configured to generate zeros, the frequency of which varies with the load capacitance to compensate for the poles of the first feedback loop.

[0013] The first feedback loop and the second feedback loop share a common gate transistor, and the source or drain of the common gate transistor is coupled to the signal paths of the first feedback loop and the second feedback loop, respectively.

[0014] Furthermore, the impedance element is a first MOS transistor operating in the linear region, and the on-resistance of the first MOS transistor and the load capacitance together determine the frequency of the zero point.

[0015] Furthermore, the on-resistance of the first MOS transistor is dynamically adjusted in response to changes in the current flowing through the second feedback loop.

[0016] Furthermore, the first feedback loop includes: the output power transistor;

[0017] The first transistor has its gate coupled to the output of the error amplifier, its source coupled to the output node, and its drain coupled to the source of the common-gate transistor.

[0018] The second transistor has its gate coupled to a common-source, common-gate bias voltage source, its source coupled to the drain of the first transistor, and its drain coupled to the control terminal of the output power transistor.

[0019] Furthermore, the second feedback loop includes: the common-gate transistor;

[0020] The third transistor has its gate coupled to the output of the error amplifier, its source coupled to the output node, and its drain coupled to the source of the common-gate transistor.

[0021] The fourth transistor has its gate coupled to a common-source, common-gate bias voltage source, its source coupled to the first terminal of the impedance element, and its drain coupled to the drain of the common-gate transistor.

[0022] The second end of the impedance element is coupled to the output node.

[0023] Furthermore, the present invention also includes a compensation capacitor, the first end of which is connected to the control terminal of the output power transistor, and the second end of which is connected to the output node. The capacitance value of the compensation capacitor is less than one-tenth of the capacitance value of the load capacitor.

[0024] Furthermore, the capacitance value of the compensation capacitor is less than 5pF.

[0025] Furthermore, the present invention also includes an error amplifier, wherein the non-inverting input terminal of the error amplifier is coupled to a reference voltage, the inverting input terminal is coupled to the output node, and the output terminal is coupled to the first feedback loop or the second feedback loop, for amplifying the deviation between the output voltage and the reference voltage.

[0026] Furthermore, the output power transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the output node, and its gate connected to the output terminal of the first feedback loop.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) By introducing an adaptive zero-point compensation mechanism associated with the load capacitance, the load capacitance itself participates in loop frequency shaping, which greatly reduces the large Miller compensation capacitance required in the traditional scheme. Experimental data show that, under the same power consumption conditions, the compensation capacitance of the present invention is only one-tenth of that of the traditional scheme, which significantly reduces chip area overhead.

[0029] (2) The zero point of the present invention can adaptively follow the change of load capacitance. When the load capacitance increases, the zero point frequency decreases accordingly, effectively compensating for the secondary poles introduced by the load capacitance. Simulation results show that the present invention can maintain a phase margin of more than 45 degrees in a wide load capacitance range of 1nF to 1μF, and can even reach a phase margin of nearly 90 degrees with a 1μF capacitor load, demonstrating excellent stability.

[0030] (3) By reusing the original FVF structure to construct multiple feedback loops, the generation of additional poles is minimized while introducing an adaptive compensation mechanism. The use of linear region MOSFETs as compensation resistors reduces the on-resistance of the compensation resistors under high current conditions, further improving the loop establishment speed. At the same time, by reusing the common source and common gate of the FVF structure, multiple loop compensation is achieved without significantly increasing the number of devices and circuit complexity, maintaining the inherent advantage of the compact FVF LDO structure. Attached Figure Description

[0031] Figure 1 This is a circuit diagram of a typical FVF type low dropout linear regulator in the prior art.

[0032] Figure 2 This is a circuit diagram of an FVF-type low-dropout linear regulator that separates the error amplifier from the FVF loop in the prior art.

[0033] Figure 3 This is a circuit diagram of the adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to the present invention.

[0034] Figure 4 This is a schematic diagram comparing the Bode plots of an embodiment of the present invention with those of a conventional FVF type LDO under the same load conditions.

[0035] Figure 5 This is a schematic diagram comparing the loop bandwidth and phase margin of an embodiment of the present invention with those of a traditional FVF type LDO under different load capacitance conditions. Detailed Implementation

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0037] like Figure 3 As shown, this embodiment provides an adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops, including an output power transistor M1, a first feedback loop, and a second feedback loop.

[0038] The output power transistor M1 is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the output node, and its gate connected to the output terminal of the first feedback loop. Output power transistor M1 is used to provide output current to the load. To meet the drive capability requirements under high load current conditions, M1 typically has a large size.

[0039] The first feedback loop consists of a common-gate transistor M0, an output power transistor M1, and a third transistor M2. The gate of the common-gate transistor M0 is connected to a bias voltage, and its source is connected to the drain of the third transistor M2 and the source of the fifth transistor M4. Its drain is connected to the gate of the output power transistor M1 and the drain of the sixth transistor M6. The gate of the third transistor M2 is connected to a bias current source, its source is connected to the output node, and its drain is connected to the source of the common-gate transistor M0. This first feedback loop responds to rapid changes in load current: when the external load current increases, the output node voltage is pulled low, causing a decrease in the source voltage of the third transistor M2 and a reduction in its drain current. This results in more current flowing from the source to the drain of the common-gate transistor M0, thus lowering the gate voltage of the output power transistor M1 and increasing its drain current to compensate for the output current. When the external load current decreases, the opposite process occurs.

[0040] The second feedback loop consists of a common-gate transistor M0, a fourth transistor M3, a fifth transistor M4, a sixth transistor, and a second transistor M5. Specifically, the gate of the fourth transistor M3 is connected to the second bias current source, its source is connected to the output node, and its drain is connected to the source of the common-gate transistor M0. The gate of the fifth transistor M4 is connected to the second bias current source, its source is connected to the drain of the second transistor M5, and its drain is connected to the drain of the common-gate transistor M0. The gate of the sixth transistor is connected to the second bias current source, its source is connected to the drain of the second transistor M5, and its drain is connected to the drain of the common-gate transistor M0. It should be noted that in the circuit structure of this embodiment, the fifth transistor M4 and the sixth transistor M6 can be combined into a single transistor, or they can be set separately according to specific design requirements.

[0041] The second transistor M5 is an NMOS transistor operating in the linear region. Its gate is connected to a bias voltage, its source is connected to the output node, and its drain is connected to the source of the fifth transistor M4 and the source of the sixth transistor M6. The second transistor M5, together with the load capacitance at the output node, forms a zero-generating network to produce a zero associated with the load capacitance CL. The frequency expression of this zero is:

[0042] f_zero≈1 / (2π×(R_M5+R_par)×CL),

[0043] Where R_M5 is the on-resistance of the second transistor M5, and R_par is the parasitic resistance in the second feedback loop.

[0044] When the load capacitance increases, the secondary pole frequency of the first feedback loop decreases, and the zero frequency generated by the second feedback loop also decreases accordingly, thus compensating for the secondary pole and ensuring the stability of the entire system. Since the second transistor M5 operates in the linear region, its on-resistance R_M5 changes with the current flowing through it. When the load current increases, the current flowing through the second feedback loop increases accordingly, causing R_M5 to decrease. This helps to further optimize the loop setup speed under high current conditions.

[0045] In this embodiment, the common-gate transistor M0 is multiplexed by both the first and second feedback loops, which avoids introducing additional signal paths and poles and helps maintain the stability of the loops.

[0046] To further optimize loop characteristics, this embodiment also includes a very small compensation capacitor C1, with its first terminal connected to the gate of the output power transistor M1 and its second terminal connected to the output node. The capacitance value of the compensation capacitor C1 is much smaller than the load capacitance; for example, when the load capacitance is 1nF, the compensation capacitor C1 can be set to 4pF. In most cases, since the second feedback loop already provides sufficient zero-point compensation, the compensation capacitor C1 can even be omitted.

[0047] This embodiment also includes an error amplifier EA, whose non-inverting input is connected to the reference voltage, its inverting input is connected to the output node, and its output is connected to the sources of the third transistor M2 and the fifth transistor M4 (or coupled to the feedback loop in other ways). The error amplifier EA is used to detect and amplify the deviation between the output voltage and the reference voltage, and to achieve precise voltage regulation control of the output voltage through the feedback path.

[0048] To verify the technical effect of the present invention, a comparison is made between a conventional FVF type LDO and a multi-loop compensated FVF type LDO of this embodiment. Under the same power consumption (3μA) conditions, the compensation capacitor C1 of the conventional FVF type LDO is 40pF, while the compensation capacitor C1 of this embodiment is 4pF, and the output power transistor current ratio K=5.

[0049] like Figure 4 As shown, when the load capacitance is 1nF, the Bode plot of the FVF loop in this embodiment shows that its phase margin is significantly better than that of the traditional scheme, indicating that this embodiment has better stability.

[0050] like Figure 5 As shown, when the output load capacitance changes from 1fF to 1μF, the stability of a traditional FVF-type LDO decreases with increasing load capacitance, and its phase margin is less than 30 degrees when the load capacitance approaches 1nF. In contrast, the FVF-type LDO of this embodiment maintains excellent stability across the entire load capacitance range, with a phase margin approaching 90 degrees at a 1μF load. Furthermore, the loop bandwidth of this embodiment can be maintained at a minimum of over 200kHz and does not decrease significantly with increasing load capacitance; whereas the bandwidth of a traditional FVF-type LDO decreases significantly under large loads because the secondary pole enters the gain-bandwidth product due to excessively large load capacitance.

[0051] The above experimental results show that the present invention effectively maintains loop bandwidth and transient response performance while significantly reducing the area of ​​the compensation capacitor, and achieves stable driving capability for large load capacitors.

[0052] Example 2

[0053] This embodiment modifies the connection method of the error amplifier based on Embodiment 1. Specifically, the output terminal of the error amplifier EA is connected to the gate of transistor M0 or other suitable node to further optimize the stability of the error amplifier loop. This configuration has similar technical effects to Embodiment 1 and can achieve the purpose of this invention.

[0054] Example 3

[0055] This embodiment replaces the implementation of the impedance element—the second transistor M5. Besides using a MOS transistor M5 operating in the linear region, the impedance element can also be a variable resistor, an active resistor, or other controllable impedance devices. As long as it can form a zero-point generation network together with the load capacitance, and the frequency of the zero point can be adaptively adjusted according to changes in the load capacitance, the technical effect of this invention can be achieved.

[0056] Example 4

[0057] This embodiment replaces the type of output power transistor M1. Although the above embodiment uses a PMOS transistor as the output power transistor, those skilled in the art should understand that using an NMOS transistor as the output power transistor and adjusting the circuit connections accordingly can also achieve the technical solution of this invention. This constitutes an equivalent substitution of the technical solution of this invention.

[0058] The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops provided by this invention can be widely used in various integrated circuit products that require high-performance power management, especially in applications such as portable electronic devices, wireless communication terminals, IoT nodes, and wearable devices, which have high requirements for chip area and transient response, and has significant industrial practical value.

[0059] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-dropout linear regulator based on an adaptive capacitor-compensated FVF circuit with multiple feedback loops, characterized in that, include: The output power transistor, whose source or drain is connected to the output node, is used to provide output current to the load; The first feedback loop has its input end coupled to the output node and its output end coupled to the control end of the output power transistor, which is used to respond to changes in load current and adjust the conduction state of the output power transistor. The second feedback loop has its input coupled to the output node and its output coupled to the first feedback loop. The second feedback loop includes an impedance element, which together with the load capacitance at the output node forms a zero-point generation network. The zero-point generation network is configured to generate zeros, the frequency of which varies with the load capacitance to compensate for the poles of the first feedback loop. The first feedback loop and the second feedback loop share a common gate transistor, and the source or drain of the common gate transistor is coupled to the signal paths of the first feedback loop and the second feedback loop, respectively.

2. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 1, characterized in that, The impedance element is a first MOS transistor operating in the linear region, and the on-resistance of the first MOS transistor and the load capacitance together determine the frequency of the zero point.

3. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 2, characterized in that, The on-resistance of the first MOS transistor is dynamically adjusted in response to changes in the current flowing through the second feedback loop.

4. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 3, characterized in that, It also includes an error amplifier, wherein the non-inverting input of the error amplifier is coupled to a reference voltage, the inverting input is coupled to the output node, and the output is coupled to the first feedback loop or the second feedback loop, for amplifying the deviation between the output voltage and the reference voltage.

5. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 4, characterized in that, The first feedback loop includes: The output power transistor; The first transistor has its gate coupled to the output of the error amplifier, its source coupled to the output node, and its drain coupled to the source of the common-gate transistor. The second transistor has its gate coupled to a common-source, common-gate bias voltage source, its source coupled to the drain of the first transistor, and its drain coupled to the control terminal of the output power transistor.

6. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 5, characterized in that, The second feedback loop includes: The common-gate transistor; The third transistor has its gate coupled to the output of the error amplifier, its source coupled to the output node, and its drain coupled to the source of the common-gate transistor. The fourth transistor has its gate coupled to a common-source, common-gate bias voltage source, its source coupled to the first terminal of the impedance element, and its drain coupled to the drain of the common-gate transistor. The second end of the impedance element is coupled to the output node.

7. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to any one of claims 1 to 6, characterized in that, It also includes a compensation capacitor, the first end of which is connected to the control terminal of the output power transistor, and the second end of which is connected to the output node. The capacitance value of the compensation capacitor is less than one-tenth of the capacitance value of the load capacitor.

8. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 7, characterized in that, The capacitance value of the compensation capacitor is less than 5pF.

9. The adaptive capacitor-compensated FVF type low dropout linear regulator based on multiple feedback loops according to claim 7, characterized in that, The output power transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the output node, and its gate connected to the output terminal of the first feedback loop.

Images