Storage chip power consumption optimization method and storage medium

Abstract

The invention discloses a storage chip power consumption optimization method and a storage medium, and the method comprises the steps: carrying out the independent unit division of a storage chip, obtaining a plurality of hardware modules, and enabling each hardware module to be provided with an independent clock control unit and a power supply unit; performing power consumption adjustment on the hardware module according to the idle time of each hardware module in different application scenes; wherein for any one application scene, the idle time of each hardware module is acquired to determine the level of the low-power-consumption mode to be entered by the hardware module; the low power consumption modes at least comprise a first-stage low power consumption mode, a second-stage low power consumption mode, a third-stage low power consumption mode and And according to the level of the low-power-consumption mode to be entered by the hardware module, the power consumption of the hardware module is adjusted through the clock control unit and the power supply unit. Different low-power-consumption modes are accurately matched for different application scenes, so that the power consumption is reduced to the greatest extent; and through precise control of different hardware modules, the overall performance of the storage device is not affected while low power consumption is ensured.

Description

Technical Field

[0001] This invention relates to the field of low-power chip design, specifically to a method for optimizing the power consumption of a memory chip and a memory medium. Background Technology

[0002] With the widespread application of eMMC memory chips in terminal products such as TVs, set-top boxes, tablets, and mobile phones, the requirements for the performance and reliability of eMMC memory chips are becoming increasingly stringent. The most important aspect is ensuring the stable and reliable storage of data in eMMC. As an embedded storage component, it is required to have low power consumption characteristics to extend the standby time of terminal products.

[0003] However, the existing eMMC low-power management mode cannot meet the needs of different application scenarios. This mode cannot achieve rapid entry and exit from low-power mode, nor can it achieve precise collaborative control between different functional modules, or deep integration of the main control hardware and the running software. As a result, the contradiction between the switching speed of eMMC in low-power mode and its fast response performance becomes increasingly prominent.

[0004] This invention defines different levels of low-power modes based on the actual application scenarios of eMMC storage devices, and achieves rapid response by combining the cooperation of eMMC controller and firmware, thereby reasonably entering different levels of low-power modes. Summary of the Invention

[0005] The main technical problem solved by this invention is how to accurately match different low-power modes according to different application scenarios, minimize power consumption, and achieve precise control of different hardware modules, so as to ensure low power consumption without affecting the overall performance of the storage device.

[0006] According to the first aspect, one embodiment provides a method for optimizing the power consumption of a memory chip, comprising:

[0007] The memory chip is divided into independent units to obtain multiple hardware modules, each of which has an independent clock control unit and power supply unit.

[0008] The power consumption of each hardware module is adjusted according to its idle time in different application scenarios. Specifically, for any application scenario: the idle time of each hardware module is obtained; the level of low-power mode to be entered by the hardware module is determined based on the idle time of each hardware module in the current application scenario; the low-power mode includes at least a level 1 low-power mode, a level 2 low-power mode, a level 3 low-power mode, and a level 4 low-power mode; the power consumption of the hardware module is adjusted according to the level of low-power mode to be entered by the hardware module through the clock control unit and the power supply unit of the hardware module.

[0009] In some embodiments, the clock control unit of each hardware module is used to control the clock switch of the hardware module; the power supply unit of each hardware module is used to control the power switch of the hardware module, and the power supply includes at least a core power supply and an interface power supply.

[0010] In some embodiments, determining the level of low-power mode that a hardware module should enter based on the idle time corresponding to each hardware module in the current application scenario includes:

[0011] Based on the usage status of different hardware modules in the current application scenario, identify the unused hardware modules in the current application scenario;

[0012] The low-power mode level to be entered by each unused hardware module is determined based on the time threshold range of the idle time corresponding to that hardware module.

[0013] Specifically, when the idle time corresponding to the hardware module is within the first time threshold range, the hardware module enters the first-level low-power mode; when the idle time corresponding to the hardware module is within the second time threshold range, the hardware module enters the second-level low-power mode; when the idle time corresponding to the hardware module is within the third time threshold range, the hardware module enters the third-level low-power mode; and when the idle time corresponding to the hardware module is within the fourth time threshold range, the hardware module enters the fourth-level low-power mode.

[0014] In some embodiments, the step of adjusting the power consumption of the hardware module according to the level of the low-power mode that the hardware module needs to enter, through the clock control unit and power supply unit of the hardware module, includes:

[0015] When a hardware module needs to enter different levels of low-power mode, the control operations performed by the clock control unit and power supply unit corresponding to that hardware module will be different.

[0016] When the hardware module enters the first-level low-power mode, the clock control unit controls the clock of the hardware module to be turned on, and the power supply unit controls the interface power and core power of the hardware module to be turned on.

[0017] When the hardware module enters the second-level low-power mode, the clock control unit controls the clock of the hardware module to be turned on, the power supply unit controls the interface power of the hardware module to be turned on, and the core power to be turned off.

[0018] When the hardware module enters the third-level low-power mode, the clock control unit controls the clock of the hardware module to be off, and the power supply unit controls the interface power and core power of the hardware module to be on.

[0019] When the hardware module enters the fourth-level low-power mode, the clock control unit controls the clock of the hardware module to be off, the power supply unit controls the interface power of the hardware module to be on, and the core power to be off.

[0020] In some embodiments, the independent clock control unit corresponding to each hardware module is provided by a clock management function, which is used to configure clock switch types that support different hardware modules; the independent power supply unit corresponding to each hardware module is provided by a power management function, which is used to configure power switch types that support different hardware modules.

[0021] In some embodiments, the method further includes: obtaining the theoretical power consumption of the actual power consumption of each hardware module in the current application scenario, and obtaining the actual total power consumption and theoretical total power consumption of the current application scenario; and determining whether the clock control unit and power supply unit of each hardware module are working properly based on the actual total power consumption and theoretical total power consumption of the current application scenario.

[0022] In some embodiments, determining whether the clock control unit and power supply unit of each hardware module are working properly based on the actual total power consumption and theoretical total power consumption of the current application scenario includes: if the theoretical total power consumption of the current application scenario is greater than the actual total power consumption of the current application scenario, then the clock control unit and power supply unit of each hardware module are considered to be working properly, and the idle time of each hardware module under the current application scenario is continued to be obtained; otherwise, the clock control unit and power supply unit of each hardware module are considered not working properly, and the power management function is initialized with firmware.

[0023] In some embodiments, the method further includes: for any idle hardware module in the current application scenario: real-time monitoring to see if there is an operation that interrupts the idle state of the hardware module; if not, then continue to obtain the idle time of the hardware module in the current application scenario; if so, then re-determine the application scenario to obtain a new application scenario, and recalculate the actual total power consumption under the obtained new application scenario.

[0024] In some embodiments, the application scenarios include at least one or more of the following: system restart application scenario, register configuration application scenario, data reading application scenario, data writing application scenario, data erasing application scenario, idle application scenario, and firmware FTL operation application scenario.

[0025] According to a second aspect, one embodiment provides a storage medium storing a computer program that can be executed by a processor to implement the above-described storage chip power consumption optimization method.

[0026] According to the above embodiment, a method for optimizing the power consumption of a memory chip and a memory medium, firstly, different hardware modules are numbered, and the association between different application scenarios and all hardware modules is established. This allows for the direct selection of key nodes and unused hardware modules required for the current application scenario, and the initial reduction of total power consumption by putting these unused hardware modules into low-power mode. Then, the level of the low-power mode to be entered by each unused hardware module is adjusted based on its idle time. The longer the idle time of a hardware module, the higher the level of the low-power mode it needs to enter, allowing for the shutdown of more clocks and power supplies, resulting in lower overall power consumption and greater energy savings, thus further reducing total power consumption. By precisely matching different low-power modes according to different application scenarios, unused hardware modules in the corresponding application scenarios automatically enter different levels of low-power mode to minimize power consumption and achieve precise control of different hardware modules. This ensures low power consumption without affecting the overall performance of the memory device. Furthermore, by adding multi-level independently controlled clock and power circuits within the memory, combined with software algorithm scheduling, a new low-power mode is achieved. Attached Figure Description

[0027] Figure 1 This is a flowchart of a method for optimizing the power consumption of a memory chip.

[0028] Figure 2 This is a table showing the calculation of the power consumption of each hardware module;

[0029] Figure 3 It is a low-power, finely designed overall architecture for the internal storage devices;

[0030] Figure 4 This is a table showing the correspondence between different application scenarios and their key nodes;

[0031] Figure 5 This is a flowchart for adjusting the power consumption of hardware modules. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0033] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0034] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0035] eMMC memory chips consist of an ARM CPU as the controller and NAND Flash memory. The ARM CPU runs the controller software, commonly known as firmware. The main functions of the firmware are to manage bad blocks, perform garbage collection (GC), and provide early warnings for the NAND Flash, thereby improving performance and lifespan and ensuring reliable use of the NAND Flash. Enabling eMMC to have different levels of low-power modes for different application scenarios is a design challenge that each eMMC controller and firmware developer needs to evaluate and design.

[0036] The key to this invention lies in adding multi-level independently controlled clock and power circuits within the memory, coupled with software algorithm scheduling to achieve a novel low-power mode. By segmenting application scenarios, the hardware modules (i.e., key nodes) required in different scenarios are identified. The Task Scheduling (TST) function controls the idle time range of unused hardware modules within these scenarios to enter different levels of low-power modes, thus refining the hardware and software control process. Under normal circumstances (i.e., during normal operation without low-power modes), all hardware modules are in operation. By precisely matching different low-power modes according to different application scenarios, unused hardware modules can enter different levels of low-power modes, achieving precise control of different hardware modules, minimizing power consumption, and ensuring low power consumption without affecting the overall performance of the storage device.

[0037] The low-power design of the storage device in this embodiment of the invention mainly includes three parts: (1) refined design of hardware modules, that is, dividing the storage device into independent units to obtain multiple hardware modules, and providing an independent clock control unit for each hardware module through the clock management function; and providing an independent power supply unit for each hardware module through the power management function; (2) pre-processing division for actual application scenarios to facilitate power consumption control according to different application scenario modes; (3) in different application scenarios, determining the hardware modules that need to be controlled in the current application scenario based on the usage of different hardware modules in the current application scenario, so as to enable these hardware modules to enter different levels of low-power mode according to the idle time of the unused hardware modules in the application scenario, thereby realizing precise control of different hardware modules; and the longer the idle time, the higher the level of the low-power mode entered, thereby making the overall power consumption of the corresponding hardware module lower and thus saving more power.

[0038] Please refer to Figure 1 Some embodiments provide a method for optimizing the power consumption of a memory chip, which includes the following steps:

[0039] Step S100: Divide the memory chip into independent units to obtain multiple hardware modules. Each hardware module has an independent clock control unit and power supply unit.

[0040] This embodiment performs fine classification based on the hardware logic design of the memory, that is, the memory chip (memory device) is divided into independent units to obtain multiple hardware modules. At this time, each hardware module is an independent unit, and the obtained hardware modules are numbered. Among them, the same hardware module serves as a key node in different application scenarios to realize different functions.

[0041] For example, suppose we have 20 hardware modules, which can be independently divided into logical units such as RISCV (Central Processing Unit), CMDProcess (Command Processing Flow), HW Configuration (Storage Hardware Related Configuration), eMMC Configuration (Protocol Related Configuration), ..., OSC (System Reference Clock), and System Power, and their numbers can be set to H1~H20 in sequence.

[0042] In this embodiment, the hardware modules and their power consumption calculation tables are as follows: Figure 2 As shown, each hardware module is coded to identify key nodes in different application scenarios in a timely manner. The diagram includes the barcode, name, activity time Ts, actual power P, and actual power consumption W of each hardware module after fine division. For example, the first hardware module represents the central processing unit RISCCV, which is numbered H1, has an actual power of P1, and its activity time (excluding idle time) recorded by TST is T1. Then, the actual power consumption of this hardware module is W1 = P1 × T1.

[0043] In addition, the clock control unit of each hardware module is used to control the clock switch of the hardware module, and the power supply unit of each hardware module is used to control the power switch of the hardware module. The power supply in this embodiment includes at least the core power supply VCC and the interface power supply VCCQ.

[0044] Each hardware module has an independent clock control unit provided by a clock management function, which is used to configure the clock switch type that supports different hardware modules; each hardware module has an independent power supply unit provided by a power management function, which is used to configure the power switch type that supports different hardware modules.

[0045] In this embodiment, the overall architecture of the storage device features a low-power, finely designed internal architecture as follows: Figure 3As shown in the diagram, the OSC (System Base Clock) provides the clock source for the storage controller; the System Power module provides power to all hardware modules of the entire storage device; the Clock Management function provides an independent clock control unit for each hardware module; the Power Management function provides an independent power supply unit for each hardware module; RISC represents the Central Processing Unit; RAM represents Random Access Memory; ROM represents Read-Only Memory; the eMMC Interface is the protocol interface for data transmission and command interaction between the embedded multimedia card (eMMC) and the host, and can accept host commands; the Command Execution Flow (CMD Process) is the processing unit that parses the instructions issued by the host and classifies them into different application scenarios; the TST (Task Schedule Timer) is the clock monitoring unit that controls the scheduling of different hardware modules for operation or idle time; HW Configuration represents the storage hardware-related configuration; eMMC Configuration represents the protocol-related configuration; Table Buffer, Read Buffer, Write Buffer, GC Buffer, LDPC Buffer, and ACC are also mentioned. Buffer (acceleration / accumulation buffer) and CMDQ Buffer (command queue buffer) are different buffers in firmware that provide data temporary storage and interaction support for different FTL (flash translation layer) algorithms; NAND Array represents the physical storage device of NAND Flash.

[0046] exist Figure 3The process begins with powering on the eMMC storage chips and initializing the system reference clock (OSC). It then continuously checks if the Clock Management function is enabled. If enabled, the eMMC firmware initializes the Clock Management function during the startup phase to configure clock switch types for different hardware modules. Next, it checks the Power Management function. If enabled, the eMMC firmware initializes the Power Management function to configure power switch types for different hardware modules. Then, the eMMC firmware initializes the TST (Task Schedule Timer) function. This allows all hardware modules to have the same idle time threshold for different low-power modes, or different hardware modules can have their own idle time thresholds set. This ensures that each hardware module enters the corresponding low-power mode after its idle time exceeds its threshold. Subsequently, different application modes are configured according to different application scenarios, and the clock and power states of each hardware module are configured based on the TST monitoring and scheduling status.

[0047] Step S110: Adjust the power consumption of the hardware module according to the idle time of each hardware module in different application scenarios; wherein, obtain the idle time of each hardware module in any application scenario; determine the level of low power mode to be entered by the hardware module according to the idle time corresponding to each hardware module in the current application scenario, and then adjust the power consumption of the hardware module.

[0048] This embodiment abstracts specific and typical scenario types from various complex application types, including at least: system restart application scenario, register configuration application scenario, data read application scenario, data write application scenario, data erase application scenario, idle application scenario, and firmware FTL operation application scenario. Furthermore, it identifies the hardware modules used in each application scenario, i.e., the key nodes corresponding to that application scenario. The correspondence table of different application scenarios and their key nodes is as follows: Figure 4 As shown, taking the data reading application scenario as an example, the hardware modules (i.e., key nodes) used in this application scenario are H20, H19, H18, H17, H6, H1, H2, H3, H9, H16, and H4. The hardware modules not used in this application scenario, including H5, H7, H8, H10, H11, H12, H13, H14, and H15, will enter the corresponding level of low-power mode according to their idle time. As a result, the actual total power consumption generated by different levels of low-power mode is much lower than the theoretical total power consumption generated during normal operation without setting a low-power mode.

[0049] In this embodiment, the level of low-power mode to be entered by each hardware module is determined based on the idle time corresponding to that hardware module in different application scenarios. The process of adjusting the low-power mode of the hardware module through the clock control unit and power supply unit of that hardware module is as follows: Figure 5 As shown, it includes the following steps:

[0050] Step S111: For any application scenario: obtain the idle time of each hardware module.

[0051] Upon entering an application scenario, the usage status of each hardware module in that scenario is monitored in real time to pre-determine which hardware module will be adjusted to low-power mode. Based on its idle time, the low-power level that the hardware module will request is predicted, thereby achieving a rapid response to low-power mode switching. The actual total power consumption of the application scenario is calculated based on the activity time and actual power consumption of each hardware module. Subsequently, this is compared with the theoretical total power consumption of the application scenario to determine whether the entire system is operating normally based on the set low-power mode control method.

[0052] Step S112: Determine the level of low-power mode that the hardware module should enter based on the idle time of each hardware module in the current application scenario.

[0053] The low-power modes in this embodiment include a level 1 low-power mode, a level 2 low-power mode, a level 3 low-power mode, and a level 4 low-power mode.

[0054] Based on the usage status of different hardware modules in the current application scenario, the unused hardware modules in the current application scenario are identified. The low-power mode level to be entered by each unused hardware module is determined based on the time threshold range of its idle time. Specifically, when the idle time of a hardware module is within the first time threshold range, the hardware module enters a level 1 low-power mode; when the idle time is within the second time threshold range, the hardware module enters a level 2 low-power mode; when the idle time is within the third time threshold range, the hardware module enters a level 3 low-power mode; and when the idle time is within the fourth time threshold range, the hardware module enters a level 4 low-power mode.

[0055] For example, suppose that in the current application scenario, the current idle time of a certain hardware module is t, and the corresponding first time threshold is t1, the second time threshold is t2, the third time threshold is t3, and the fourth time threshold is t4, where t4 > t3 > t2 > t1. Then, when the idle time of the hardware module reaches the first time threshold t1 but does not reach the second time threshold t2 (i.e., t1 ≤ t < t2), corresponding to the first time threshold range, the hardware module automatically enters (or maintains) the first low-power mode; when the idle time of the hardware module reaches the second time threshold t2 but does not reach the third time threshold, the hardware module automatically enters (or maintains) the first low-power mode. When the idle time of the hardware module reaches the third time threshold t3, that is, t2≤t<t3, corresponding to the second time threshold range, the hardware module automatically enters (or maintains) the second-level low-power mode. When the idle time of the hardware module reaches the third time threshold t3, but does not reach the fourth time threshold t4, that is, t3≤t<t4, corresponding to the third time threshold range, the hardware module automatically enters (or maintains) the third-level low-power mode. When the idle time of the hardware module reaches or exceeds the fourth time threshold t4, that is, t≥t4, corresponding to the fourth time threshold range, the hardware module automatically enters (or maintains) the fourth-level low-power mode.

[0056] During this process, it is necessary to monitor in real time whether there is any operation that interrupts the idle state of the hardware module. If not, the idle time of the hardware module in the current application scenario is obtained, and the idle time threshold range of the hardware module is determined based on the idle time of the hardware module. If it exists, it means that the application scenario has changed, and the application scenario needs to be re-determined to obtain a new application scenario. In the new application scenario, the actual total power consumption in the new application scenario is recalculated based on the actual power consumption of each hardware module, so as to compare with the actual total power consumption and monitor whether the low power control process is working properly.

[0057] It should be noted that when the current application scenario is interrupted and a new application scenario is entered, only the idle time of the hardware module whose idle state was interrupted is recalculated, while the idle time of the hardware module whose idle state was not interrupted is not recalculated, and its corresponding low power mode level does not need to be adjusted.

[0058] For example, refer to Figure 4Assuming the current application scenario is a read data application scenario, and it is interrupted to enter a write data application scenario, the key node difference between these two application scenarios is that the key node 9 in the read data application scenario is H9, while the key node 9 in the write data application scenario is H10. The other key nodes are the same. That is to say, in the read data application scenario, if the idle state of hardware module H10 is interrupted, after re-judging the application scenario, the new application scenario is the write data application scenario. At this time, H9 becomes idle, and other hardware modules that were not interrupted remain idle. That is, the unused hardware modules in the write data application scenario (including H5, H7, H8, H11, H12, H13, H14, and H15) are still in an idle state. Therefore, there is no need to adjust the idle time (or low power mode level) of these hardware modules that are still unused in the write data application scenario. Instead, the idle time continues to accumulate on the original basis.

[0059] Step S113: Based on the level of the low-power mode that the hardware module needs to enter, the power consumption of the hardware module is adjusted through the clock control unit and the power supply unit of the hardware module.

[0060] The power consumption of a hardware module mainly comes from two categories: dynamic power consumption and static power consumption. Dynamic power consumption is generated by the switching action of the circuit and is positively correlated with the clock frequency and voltage. It is the main power consumption when the hardware module is working. Static power consumption is generated by leakage current and also exists when the hardware module is powered on but not working.

[0061] The core power supply VCC powers the core logic of the hardware module, while the interface power supply VCCQ powers the input / output interfaces of the hardware module to ensure communication between the hardware and the host. The clock signal is crucial for the switching action of the drive circuit. As long as the clock is running, even if the hardware module is not actually working, the internal logic circuit will still idle with the clock tick, generating dynamic power consumption. Therefore, when the hardware module is idle, turning off its dedicated clock can significantly reduce the dynamic power consumption of the hardware module. Compared to directly cutting off the power, turning off the clock results in a faster wake-up speed and better rapid response.

[0062] In this embodiment, when a hardware module needs to enter a different level of low-power mode, the control operations performed by the clock control unit and the power supply unit corresponding to that hardware module are different.

[0063] When the hardware module enters Level 1 low-power mode, its clock control unit keeps the clock on and its power supply unit keeps all power supplies on, including the core power supply VCC and the interface power supply VCCQ. When the hardware module enters Level 2 low-power mode, its clock control unit keeps the clock on and its power supply unit keeps the interface power supply VCCQ on, while the core power supply VCC is off. When the hardware module enters Level 3 low-power mode, its clock control unit keeps the clock off and its power supply unit keeps all power supplies on, including the core power supply VCC and the interface power supply VCCQ. When the hardware module enters Level 4 low-power mode, its clock control unit keeps the clock off and its power supply unit keeps the interface power supply VCCQ on, while the core power supply VCC is off.

[0064] During this process, the actual power consumption and theoretical power consumption of each hardware module in the current application scenario are acquired in real time, resulting in the actual total power consumption and theoretical total power consumption of the current application scenario. Without fine-grained partitioning of hardware modules and adjustment of clock and power management functions, all hardware modules remain on in different application scenarios, even those not actually in use. In this case, the theoretical total power consumption is the sum of the product of the power (theoretical power) of each hardware module and its total operating time, i.e., the sum of the theoretical power consumption of each hardware module. However, with fine-grained partitioning of hardware modules and adjustment of clock and power management functions, hardware modules not used in each application scenario are put into different levels of low-power mode based on their usage in that application scenario. In this case, the actual total power consumption is the sum of the product of the actual power of each hardware module in that application scenario and its actual operating time (activity time), i.e., the sum of the actual power consumption of each hardware module.

[0065] Then, based on the actual total power consumption and the theoretical total power consumption of the current application scenario, it is determined whether the clock control unit and power supply unit of each hardware module are working properly. If the theoretical total power consumption of the current application scenario is greater than the actual total power consumption, the clock control unit and power supply unit of each hardware module are considered to be working properly, and the idle time of each hardware module in the current application scenario continues to be acquired to adjust the power consumption of each hardware module in the current application scenario; otherwise, the clock control unit and power supply unit of each hardware module are considered not working properly. At this time, it is necessary to check whether there are any abnormalities or program problems during the execution process, which may have caused the low power mode adjustment to fail to take effect, and the power management function is initialized with firmware.

[0066] This embodiment first numbers the different hardware modules and establishes the association between different application scenarios and all hardware modules. Based on the current application scenario, it directly filters out the key nodes to be used and the unused hardware modules for that scenario, and initially reduces total power consumption by putting these unused hardware modules into low-power mode. Then, it further adjusts the level of low-power mode to be entered by each unused hardware module based on its idle time. The longer the idle time of a hardware module, the higher the level of low-power mode it enters, the more clocks and power supplies can be turned off, and the lower the overall power consumption of the hardware module, thus further reducing total power consumption. By precisely matching different low-power modes according to different application scenarios, unused hardware modules in the corresponding application scenarios automatically enter different levels of low-power mode to minimize power consumption and achieve precise control of different hardware modules. While ensuring low power consumption, it does not affect the overall performance of the storage device. A new low-power mode is achieved by adding multi-level independently controlled clock and power circuits inside the memory, combined with software algorithm scheduling.

[0067] The present invention also discloses a storage medium storing a computer program, which can be executed by a processor to implement the above-described method for optimizing the power consumption of a storage chip.

[0068] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0069] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A method for optimizing the power consumption of a memory chip, characterized in that, include: The memory chip is divided into independent units to obtain multiple hardware modules, each of which has an independent clock control unit and power supply unit. The power consumption of each hardware module is adjusted according to its idle time in different application scenarios. Specifically, for any application scenario: the idle time of each hardware module is obtained; the level of low-power mode to be entered by the hardware module is determined based on the idle time of each hardware module in the current application scenario; the low-power mode includes at least a level 1 low-power mode, a level 2 low-power mode, a level 3 low-power mode, and a level 4 low-power mode; the power consumption of the hardware module is adjusted according to the level of low-power mode to be entered by the hardware module through the clock control unit and the power supply unit of the hardware module.

2. The method as described in claim 1, characterized in that, The clock control unit of each hardware module is used to control the clock switch of the hardware module; the power supply unit of each hardware module is used to control the power switch of the hardware module, and the power supply includes at least the core power supply and the interface power supply.

3. The method as described in claim 2, characterized in that, The step of determining the level of low-power mode that a hardware module should enter based on the idle time corresponding to each hardware module in the current application scenario includes: Based on the usage status of different hardware modules in the current application scenario, identify the unused hardware modules in the current application scenario; The low-power mode level to be entered by each unused hardware module is determined based on the time threshold range of the idle time corresponding to that hardware module. Specifically, when the idle time corresponding to the hardware module is within the first time threshold range, the hardware module enters the first-level low-power mode; when the idle time corresponding to the hardware module is within the second time threshold range, the hardware module enters the second-level low-power mode; when the idle time corresponding to the hardware module is within the third time threshold range, the hardware module enters the third-level low-power mode; and when the idle time corresponding to the hardware module is within the fourth time threshold range, the hardware module enters the fourth-level low-power mode.

4. The method as described in claim 3, characterized in that, The step of adjusting the power consumption of the hardware module according to the level of the low-power mode it needs to enter, through the clock control unit and power supply unit of the hardware module, includes: When a hardware module needs to enter different levels of low-power mode, the control operations performed by the clock control unit and power supply unit corresponding to that hardware module will be different. When the hardware module enters the first-level low-power mode, the clock control unit controls the clock of the hardware module to be turned on, and the power supply unit controls the interface power and core power of the hardware module to be turned on. When the hardware module enters the second-level low-power mode, the clock control unit controls the clock of the hardware module to be turned on, the power supply unit controls the interface power of the hardware module to be turned on, and the core power to be turned off. When the hardware module enters the third-level low-power mode, the clock control unit controls the clock of the hardware module to be off, and the power supply unit controls the interface power and core power of the hardware module to be on. When the hardware module enters the fourth-level low-power mode, the clock control unit controls the clock of the hardware module to be off, the power supply unit controls the interface power of the hardware module to be on, and the core power to be off.

5. The method as described in claim 1, characterized in that, The independent clock control unit corresponding to each hardware module is provided by the clock management function, which is used to configure the clock switch type that supports different hardware modules; the independent power supply unit corresponding to each hardware module is provided by the power management function, which is used to configure the power switch type that supports different hardware modules.

6. The method as described in claim 5, characterized in that, Also includes: Obtain the actual power consumption and theoretical power consumption of each hardware module in the current application scenario, and get the actual total power consumption and theoretical total power consumption of the current application scenario; Based on the actual total power consumption and theoretical total power consumption of the current application scenario, determine whether the clock control unit and power supply unit of each hardware module are working properly.

7. The method as described in claim 6, characterized in that, The step of determining whether the clock control unit and power supply unit of each hardware module are working properly based on the actual total power consumption and theoretical total power consumption of the current application scenario includes: If the theoretical total power consumption of the current application scenario is greater than the actual total power consumption of the current application scenario, then the clock control unit and power supply unit of each hardware module are considered to be working normally, and the idle time of each hardware module under the current application scenario will continue to be acquired; otherwise, the clock control unit and power supply unit of each hardware module are considered not to be working normally, and the power management function will be initialized with firmware.

8. The method as described in claim 1, characterized in that, Also includes: For any idle hardware module in the current application scenario: monitor in real time whether there is an operation that interrupts the idle state of the hardware module; if not, continue to obtain the idle time of the hardware module in the current application scenario; if it exists, re-determine the application scenario to obtain a new application scenario, and recalculate the actual total power consumption under the obtained new application scenario.

9. The method as described in claim 1, characterized in that, The application scenarios include at least one or more of the following: system restart application scenario, register configuration application scenario, data reading application scenario, data writing application scenario, data erasing application scenario, idle application scenario, and firmware FTL operation application scenario.

10. A storage medium, characterized in that, The storage medium stores a computer program that can be executed by a processor to implement the method as described in any one of claims 1-9.

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