An AI algorithm acceleration system and method for real-time junction temperature prediction of IGBTs
By employing the Zynq7000 series FPGA SoC architecture and dedicated neural network processor in the IGBT system, combined with mixed-precision computing and multi-level cache design, the problems of high accuracy, low latency and energy efficiency in IGBT junction temperature prediction are solved, and efficient junction temperature monitoring at the edge is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- STATE GRID FUJIAN ELECTRIC POWER CO LTD
- Filing Date
- 2026-02-03
- Publication Date
- 2026-05-26
AI Technical Summary
Existing technologies lack a solution for online prediction of IGBT junction temperature that can achieve high accuracy, low latency, and high energy efficiency at the edge of large-scale power systems, and also suffer from high computational load, high communication costs, and data privacy issues.
It adopts a SoC architecture based on Zynq7000 series FPGA, integrating a dual-core ARM Cortex-A9 processor and a dedicated neural network processor NPU. It combines mixed-precision vector inner product units and three-dimensional matrix inner product operation units to design a multi-level cache system, realize hardware and software co-optimization, and filter effective operations through the approximate prior vector inner product method (AVIP) to reduce computation latency and memory access.
It achieves high-precision, low-latency, and low-energy-consumption IGBT junction temperature prediction at the edge, with an average prediction error of less than 3°C, adapting to the needs of large-scale distributed deployment and avoiding high communication costs and data privacy leakage risks.
Smart Images
Figure CN122086703A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor device condition monitoring and edge computing technology, and in particular to an artificial intelligence algorithm acceleration system and method for real-time junction temperature prediction of IGBTs. Background Technology
[0002] Insulated-gate bipolar transistors (IGBTs) are core power switching devices in modern power electronic systems, and their reliability and lifespan directly affect the operational safety of the entire system (smart grid). Among the many factors affecting IGBT reliability, the junction temperature (TJ) is one of the most critical parameters. Excessively high or drastic fluctuations in junction temperature can accelerate device aging and even lead to immediate failure. Therefore, achieving accurate, real-time online monitoring of IGBT chip junction temperature is crucial for system status monitoring, fault prediction, and health management.
[0003] Artificial intelligence algorithms have become a highly effective method in the field of IGBT junction temperature estimation; however, they still face a series of challenges and difficulties. First, AI methods are computationally intensive and complex, placing high demands on the computing power of the hardware in power systems, leading to increased costs due to hardware upgrades. Second, junction temperature calculation requires sufficiently low latency to ensure the system can take timely and necessary protective measures to address IGBT temperature changes. Finally, considering that power systems typically require large-scale distributed deployment, and that system operating status and other information are sensitive, the computing hardware must be remote and edge-based to maintain data privacy, while simultaneously ensuring sufficient reliability to adapt to complex operating environments.
[0004] Current technologies lack an online IGBT junction temperature prediction solution that can achieve a balance between high accuracy, low latency, and high energy efficiency at the edge of large-scale power systems. Therefore, there is an urgent need for a system and method that integrates dedicated hardware acceleration capabilities and can directly perform complex AI algorithm inference at the device level to overcome the above-mentioned shortcomings and promote the application of artificial intelligence technology in the condition monitoring of industrial power equipment. Summary of the Invention
[0005] In view of this, the purpose of this invention is to provide an artificial intelligence algorithm acceleration system and method for real-time IGBT junction temperature prediction. Through the collaborative optimization design of algorithms and hardware, it solves the problems of high latency, high communication cost and data privacy in cloud computing solutions. At the same time, it breaks through the bottlenecks of existing edge computing platforms in terms of computing power, energy efficiency and accuracy, and finally realizes a dedicated solution for high-precision, low-latency and high-energy-efficiency online prediction of IGBT junction temperature at the edge of industrial sites.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: an artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs, comprising a parameter acquisition module, an artificial intelligence algorithm acceleration module, and a host computer; The parameter acquisition module is used to acquire the saturated on-state collector-emitter voltage V during IGBT operation. CE（Sat） Collector current I C and substrate temperature T C The collected analog signals are converted into digital signals and then transmitted to the artificial intelligence algorithm acceleration module. The artificial intelligence algorithm acceleration module is based on a Zynq7000 series FPGA to build a SoC architecture, integrating a dual-core ARM Cortex-A9 processor and a dedicated neural network processor (NPU). The ARM Cortex-A9 processor is used for system initialization, data scheduling, and communication with the host computer. The dedicated neural network processor (NPU) includes a mixed-precision vector inner product unit (Hybrid-VPU), a three-dimensional matrix inner product operation unit (MMU), and a multi-level cache and control unit, which are used for hardware acceleration of the core operations of vector inner product and matrix inner product in the junction temperature prediction algorithm. The host computer is used to receive the junction temperature prediction results and original acquisition parameters transmitted by the artificial intelligence algorithm acceleration module, and realize real-time data display, historical data storage, junction temperature anomaly alarm and model parameter calibration.
[0007] In a preferred embodiment, the parameter acquisition module includes: Voltage acquisition unit: Employs an indirect acquisition scheme, inferring V by acquiring the associated voltage V1. CE（Sat） The circuit is compatible with scenarios where the IGBT is under low voltage in the on-state and under high voltage on the bus in the off-state. Current acquisition unit: A Rogowski coil is used in the IGBT bus circuit for non-destructive measurement. C The output voltage signal is converted into a digital quantity by the ADC; Temperature acquisition unit: A thermocouple is tightly secured to the IGBT metal substrate with screws to measure temperature (T). C Cold junction compensation and digital processing are achieved through the MAX31856 chip; Communication unit: It adopts an optical fiber communication interface and uses 8b / 10b encoding to achieve isolated data transmission with the artificial intelligence algorithm acceleration module, supporting synchronous parameter acquisition at a switching frequency of up to 50kHz.
[0008] In a preferred embodiment, the mixed-precision vector inner product unit (Hybrid-VPU) includes N mixed-precision floating-point multipliers (Hybrid-FPUs) and one N-input 16-bit pipelined adder tree. The mixed-precision floating-point multipliers (Hybrid-FPUs) reuse the DSP48EIP core and support three precision operations: hfp16-int8, hfp16-hfp16, and int8-int8. At the same time, one set of hfp16 vector inner products or two sets of int8 vector inner products can be executed. The adder tree adopts a log2N-stage pipeline design. When N=16, the number of pipeline stages is 4, and the output data bit width is 32 bits.
[0009] In a preferred embodiment, the three-dimensional matrix inner product operation unit (MMU) adopts an N×NPE array architecture, where N≥4; each PE unit is an int8 precision vector inner product unit, containing N fixed-point multipliers and one addition tree; PEs in the same row share a row of input from matrix A, and PEs in the same column share a column of input from matrix B. PE[i,j] performs the inner product operation of A[i,:] and B[:,j], and N operations can be performed in parallel in one clock cycle. 3 Multiplication and associative addition operations are supported; matrix block tiling optimization is supported, and the storage configurations of "large Z small Z", "large N small N", and "large N small Z" are adapted to large matrix operations.
[0010] In a preferred embodiment, the multi-level cache and control unit of the dedicated neural network processor (NPU) includes a dedicated cache for matrix inner product and a unified cache (Unified-Buffer). The dedicated cache for matrix inner product includes Buffer-A, Buffer-B, and Buffer-C. Buffer-A, Buffer-B, and Buffer-C store the input matrices A and B and the output matrix C, respectively, while the Unified-Buffer stores vector operation data. The CPU and the dedicated neural network processor (NPU) alternately access different cache partitions to achieve parallel execution of data transmission and computation, thereby reducing memory access latency.
[0011] This invention also provides an artificial intelligence algorithm acceleration method for real-time junction temperature prediction of IGBTs, implemented based on the aforementioned artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs, comprising the following steps: Step 1: System initialization. The ARM processor reads the pre-stored BP neural network model weights and configuration parameters, loads them into DDR3 memory, and completes the initialization of the dedicated neural network processor NPU, sensor driver, and communication interface. Step 2: Real-time parameter acquisition; the parameter acquisition module synchronously acquires the V of the IGBT. CE（Sat） I C and T C，After analog-to-digital conversion and isolated transmission, the data is sent to the artificial intelligence algorithm acceleration module. Step 3: Data preprocessing. The ARM processor normalizes the raw parameters, removes outlier data, and packages them into a 3D input vector. Step 4: Approximate Prior Vector Inner Product (AVIP) Operation. The dedicated Neural Processing Unit (NPU) divides the weight vector into K continuous sub-regions, selects a subset of effective parameters to perform low-precision inner product operation, and filters out effective operations. Step 5: Hardware-accelerated inference of BP neural network, which completes the calculation of each layer based on the mixed precision architecture of the dedicated neural network processor NPU and outputs the intermediate results of junction temperature prediction; Step 6: Post-processing of results. Perform inverse normalization and smoothing on the intermediate results to obtain the actual junction temperature value. Step 7: Data transmission and storage, upload the junction temperature value and original parameters to the host computer; Step 8: Repeat steps 2 to 7 to achieve continuous real-time monitoring; Step 9: Anomaly Alarm. When the host computer detects that the junction temperature exceeds the threshold or that the parameters are abnormal, it triggers an alarm and sends a protection signal.
[0012] In a preferred embodiment, the specific implementation of the Approximate Prior Vector Inner Product (AVIP) method in step 4 includes: Step 41: Analyze the pre-trained BP neural network model offline, and divide the weight vectors of each layer with a length of N into K continuous sub-regions of equal length, where K = 2, 4 or 8; Step 42: Calculate the sum of the absolute values of the elements within each sub-region, and select the sub-region with the largest sum of absolute values as the effective parameter subset; Step 43: Perform a low-precision inner product operation on the input vector and the effective parameter subset, while scaling the bias value proportionally by K, b→b / K; Step 44: Determine the sign of the inner product result. If it is not positive, ignore the operation; if it is positive, retain it and perform the subsequent complete high-precision inner product operation.
[0013] In a preferred embodiment, the specific implementation of the hardware-accelerated inference of the BP neural network in step 5 includes: Step 51: Input layer to first hidden layer: Using the hfp16-hfp16 mode of Hybrid-VPU, the vector inner product API (npu_vip) is called, and the operation of 3 inputs → 16 outputs is completed in 16 iterations; Step 52: Intermediate hidden layer, 3 layers in total: Using the MMU's int8 precision mode, combined with the effective operation columns filtered by AVIP, the matrix inner product API (npu_mm) is called to complete the 16×16 matrix inner product through block operation; Step 53: Output layer: Using the hfp16-hfp16 mode of Hybrid-VPU, the vector accumulation API (npu_vipa) is called to split the 16 inputs into 4 sub-vectors of length 4, and accumulate them in batches to obtain a single junction temperature prediction value; Step 54: After each layer operation, the ReLU activation function is executed to suppress negative values and reduce invalid computation propagation.
[0014] In a preferred embodiment, the normalization range of the data preprocessing in step 3 is 0~1, using the linear normalization formula: x_norm=(x-x_min) / (x_max-x_min); where V CE（Sat） The normalized range corresponds to the actual voltage 0~1V, I C Corresponding to 20~200A, T C The corresponding temperature range is 25~150℃; outlier data is removed using the 3σ criterion, which removes data points that fall outside the range of [x_mean-3σ, x_mean+3σ].
[0015] In a preferred embodiment, the post-processing of the results in step 6 employs a moving average filter with a window size of 5, and the formula is as follows: The inverse normalization formula is: ,in , This ensures that the output junction temperature value matches the actual physical range.
[0016] Compared with the prior art, the present invention has the following beneficial effects: 1) It achieves real-time computing at the edge, solving the inherent problem of cloud dependence. Through the edge computing architecture of NPU, AI algorithm inference can be completed directly in the industrial field without relying on remote cloud servers, avoiding high communication costs and data privacy leakage risks, and adapting to the deployment needs of large-scale distributed power systems.
[0017] 2) Achieving ultra-low computational latency while ensuring high prediction accuracy: The hybrid precision computation strategy adopted in this invention uses high-precision computation on critical paths that ensure the overall prediction accuracy of the model, while using low-precision computation on non-critical or prediction paths to improve speed. This strategy, combined with dedicated hardware acceleration, enables the system to complete a single complete junction temperature prediction in less than 1 millisecond, while keeping the average prediction error within 3°C, perfectly balancing the dual requirements of speed and accuracy for industrial applications.
[0018] 3) Through hardware and software co-design, the "memory wall" problem is effectively alleviated: This invention maximizes data reuse within the chip by designing a multi-level on-chip cache and combining it with a "ping-pong" data flow mechanism, significantly reducing the number of communications and bandwidth requirements with off-chip memory (such as DDR). This design enables computing units to continuously receive data and maintain high utilization, thereby solving the "memory wall" bottleneck that restricts computing performance and energy efficiency. Attached Figure Description
[0019] Figure 1 This is the system overall architecture of a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the overall SoC architecture of a preferred embodiment of the present invention; Figure 3 This is a top-level architecture diagram of the NPU according to a preferred embodiment of the present invention. Detailed Implementation
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0022] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0023] refer to Figure 1-3 The specific implementation of this patent relates to an artificial intelligence algorithm acceleration system and method for real-time junction temperature prediction of IGBTs.
[0024] First, select the saturated on-state collector-emitter voltage (V). CE ), collector current (I C ) and substrate temperature (T) C ) as a characterization of IGBT junction temperature (T) J Key characteristic parameters of IGBTs. A power cycling accelerated aging test platform was designed, applying different currents to unpackaged IGBT modules while controlling heat dissipation conditions, and simultaneously measuring and acquiring VL online. CE -I C -T C -T J Data (where T)J (Calibrated using an infrared thermal imager) to create a degenerate dataset for neural network training.
[0025] Secondly, based on this dataset, a four-hidden-layer BP neural network junction temperature prediction model is constructed and trained. To address the computational power and latency challenges of deploying the algorithm at the edge, an Approximate Prior Vector Inner Product (AVIP) method is proposed. By pre-computing with low precision during the model inference stage to filter effective computations, the amount of high-precision computation and memory access is significantly reduced.
[0026] Subsequently, a dedicated neural network processor (NPU) was designed and integrated into the Zynq7000 SoC architecture. This NPU includes a mixed-precision vector inner product unit (Hybrid-VPU) and a three-dimensional matrix inner product unit (MMU). Through multi-level caching and a "ping-pong" data flow mechanism, the hardware accelerates the AVIP-optimized BP neural network core operations, forming a hardware-software co-operated real-time junction temperature prediction system.
[0027] Finally, a verification system was built, comprising a parameter acquisition module, an AI algorithm acceleration module, and a host computer. During IGBT operation, this system utilizes real-time acquired electrical parameters and employs a prediction model deployed on the NPU for online, low-latency accelerated calculations. This enables high-precision, millisecond-level real-time prediction of the IGBT chip junction temperature, providing crucial data for power system health monitoring and proactive thermal management.
[0028] The system hardware implementation includes: Voltage acquisition unit: Indirect acquisition scheme is adopted. After the IGBT is fully turned on and enters steady state, its saturation on-state voltage drop V CE(Sat) It cannot directly withstand high bus voltage. This unit acquires voltage from V through a precision resistor voltage divider network. CE(Sat) The associated voltage signal V1 is then processed by the formula. The real V is obtained by reverse engineering. CE(Sat) The acquired analog voltage signal is converted from analog to digital by a high-precision, high-speed ADC (such as AD4682, 16-bit resolution).
[0029] Current acquisition unit: A Rogowski coil is used to mount on the IGBT bus for non-destructive measurement. The differential signal output from the Rogowski coil is conditioned by an integrator to output a voltage signal. This voltage value is proportional to the rate of change of the collector current IC, and is then converted into a digital quantity by an ADC. This scheme avoids introducing parasitic parameters into the power circuit, ensuring the dynamic response performance of the system.
[0030] Temperature acquisition unit: A K-type thermocouple is mounted tightly against the metal substrate of the IGBT module using fastening screws, and thermal paste is applied to the contact surface to reduce thermal resistance. The weak millivolt-level signal output by the thermocouple is processed by a dedicated thermocouple signal conditioning chip, MAX31856. This chip integrates cold junction compensation, analog-to-digital conversion, and a digital interface, and transmits the compensated substrate temperature T via SPI communication. C Output numeric values.
[0031] Communication Unit: An optical fiber communication interface is used to achieve electrical isolation from the artificial intelligence algorithm acceleration module. All acquired digital signals are encoded in 8b / 10b on the FPGA side and then converted into optical signals by a photoelectric conversion module for transmission. This effectively avoids interference from power ground noise on sensitive measurement circuits and supports multi-parameter synchronous acquisition at a switching frequency of up to 50kHz.
[0032] Hardware acceleration system implementation methods include: The artificial intelligence algorithm acceleration module is the core of the system, and it is built on the Xilinx Zynq-7000 series SoC FPGA (specifically model XC7Z020-CLG484). Figure 2 As shown in the SoC overall architecture diagram, this module adopts a co-design architecture of PS (processor system) + PL (programmable logic): PS side: The dual-core ARM Cortex-A9 processor runs the Linux operating system and is responsible for global system control, including: reading the pre-trained BP neural network weight file from the SD card to the off-chip DDR3 memory; scheduling the DMA controller to move data between DDR3 and NPU cache; interacting with the host computer via UART; and calling the NPU driver to initiate accelerated computing commands.
[0033] PL side: A dedicated neural network processor (NPU) and peripheral interface IP were custom-developed. For example... Figure 3 As shown in the (NPU top-level architecture diagram), the NPU includes: Hybrid-VPU: This unit consists of 16 mixed-precision floating-point multipliers (Hybrid-FPU) and a 16-input adder tree with a 4-stage pipeline. The Hybrid-FPU core is implemented using the FPGA's DSP48E1Slice. Through an internal data selector, it can be configured to support three operation modes: hfp16×hfp16, hfp16×int8 (computes 2 groups at a time), and int8×int8 (computes 4 groups at a time), achieving a dynamic balance between computational precision and hardware resources. The adder tree is designed separately for hfp16 and int16 types, and the final output is a 32-bit fixed-point (int32) number.
[0034] 3D Matrix Inner Product Unit (MMU): This unit employs a 4×4 PE (Processing Unit) array architecture. Each PE is an independent int8 precision vector inner product unit, containing four int8 multipliers and a small adder tree. PEs in the same row share a row of the input matrix A, and PEs in the same column share a column of the weight matrix B. PE[i,j] is responsible for calculating the inner product of the i-th row of matrix A and the j-th column of matrix B. This architecture can perform 4×4×4=64 multiplication operations in parallel within one clock cycle, making it computationally intensive.
[0035] The multi-level cache subsystem includes Buffer-A, Buffer-B, and Buffer-C (implemented using BlockRAM, 36KB capacity) specifically for the MMU, and a Unified-Buffer (64KB) shared by the Hybrid-VPU and CPU. All caches are divided into two physically independent memory blocks (Part a and Part b), managed strictly according to the "ping-pong" principle. When the CPU or DMA writes data to be computed into one memory block (e.g., Part a), the NPU can simultaneously read data from the other memory block (Part b) and perform computation, and vice versa. This mechanism completely hides data transfer latency, ensuring a continuous data supply to the computing units and is key to overcoming the "memory wall" bottleneck.
[0036] Control Unit: Contains an instruction issuer, register file, and state machine. The ARM processor configures control registers and issues high-level instructions (such as npu_vip() for vector inner product and npu_mm() for matrix inner product) via the AXI4-Lite bus. The control unit decodes these instructions into micro-operations, precisely controlling the timing coordination between data paths, computing units, and caches.
[0037] This invention is achieved through the following technical solution: an artificial intelligence algorithm acceleration system and method for real-time junction temperature prediction of IGBTs, specifically implemented according to the following steps: Step 1: Select the saturation on-state collector-emitter voltage (V CE ), collector current (I C ) and substrate temperature (T) C ) as a characterization of IGBT chip junction temperature (T) J The core input features of ).
[0038] Step 2: Design and build a power cycling accelerated aging test platform to obtain degradation data of IGBTs under different operating conditions.
[0039] Step 3: On the experimental platform, using an unpackaged IGBT module, simultaneously measure and acquire multiple sets of V data online. CE -I C -TC -T J The data constitutes the training dataset for the neural network, where the junction temperature T J Calibration is performed using an infrared thermal imager.
[0040] Step 4: Based on the collected dataset, construct a BP neural network model with four hidden layers to learn from electrical parameters (V). CE , I C , T C ) to junction temperature (T) J The complex mapping relationship of ).
[0041] Step 5: Propose the Approximate Prior Vector Inner Product (AVIP) method. In the model inference stage, through low-precision pre-computation and sign discrimination, select and perform only the necessary full high-precision operations to reduce the amount of computation and memory access.
[0042] Step 6: Based on the Zynq7000 series FPGA, design a SoC architecture that integrates a dedicated neural network processor (NPU) as the core computing platform for algorithm acceleration.
[0043] Step 7: Design a hybrid precision vector inner product unit (Hybrid-VPU) in the NPU to support mixed precision calculations of half-precision floating-point numbers and fixed-point numbers, so as to balance computing power and accuracy.
[0044] Step 8: Design a three-dimensional matrix inner product operation unit (MMU) in the NPU, and adopt a processing unit (PE) array architecture to achieve high parallelism of matrix operations.
[0045] Step 9: Equip the NPU with a multi-level caching system, including a matrix-specific cache and a unified cache, to improve data access efficiency.
[0046] Step 10: Adopt the "ping-pong operation" data flow strategy to enable data transfer and calculation processes to be executed in parallel, effectively hiding memory access latency and overcoming the "memory wall" bottleneck.
[0047] Step 11: Integrate the parameter acquisition module, AI algorithm acceleration module and host computer to build a complete verification system.
[0048] Step 12: Deploy the trained and AVIP-optimized BP neural network model to the NPU of the AI algorithm acceleration module.
[0049] Step 13: When the IGBT is working normally, the system collects electrical parameters in real time and calls the NPU to perform hardware-accelerated inference to achieve online prediction of junction temperature.
[0050] Step 14: Perform post-processing such as inverse normalization and moving average filtering on the prediction results output by the NPU to obtain the final junction temperature value.
[0051] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.
Claims
1. An artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs, characterized in that, It includes a parameter acquisition module, an artificial intelligence algorithm acceleration module, and a host computer; The parameter acquisition module is used to acquire the saturated on-state collector-emitter voltage V during IGBT operation. CE（Sat） Collector current I C and substrate temperature T C The collected analog signals are converted into digital signals and then transmitted to the artificial intelligence algorithm acceleration module. The artificial intelligence algorithm acceleration module is based on a Zynq7000 series FPGA to build a SoC architecture, integrating a dual-core ARM Cortex-A9 processor and a dedicated neural network processor (NPU). The ARM Cortex-A9 processor is used for system initialization, data scheduling, and communication with the host computer. The dedicated neural network processor (NPU) includes a mixed-precision vector inner product unit (Hybrid-VPU), a three-dimensional matrix inner product operation unit (MMU), and a multi-level cache and control unit, which are used for hardware acceleration of the core operations of vector inner product and matrix inner product in the junction temperature prediction algorithm. The host computer is used to receive the junction temperature prediction results and original acquisition parameters transmitted by the artificial intelligence algorithm acceleration module, and realize real-time data display, historical data storage, junction temperature anomaly alarm and model parameter calibration.
2. The artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs according to claim 1, characterized in that, The parameter acquisition module includes: Voltage acquisition unit: Employs an indirect acquisition scheme, inferring V by acquiring the associated voltage V1. CE（Sat） The circuit is compatible with scenarios where the IGBT is under low voltage in the on-state and under high voltage on the bus in the off-state. Current acquisition unit: A Rogowski coil is used in the IGBT bus circuit for non-destructive measurement. C The output voltage signal is converted into a digital quantity by the ADC; Temperature acquisition unit: A thermocouple is tightly secured to the IGBT metal substrate with screws to measure temperature (T). C Cold junction compensation and digital processing are achieved through the MAX31856 chip; Communication unit: It adopts an optical fiber communication interface and uses 8b / 10b encoding to achieve isolated data transmission with the artificial intelligence algorithm acceleration module, supporting synchronous parameter acquisition at a switching frequency of up to 50kHz.
3. The artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs according to claim 1, characterized in that, The Hybrid-VPU (Hybrid-Precision Vector Inner Product Unit) comprises N Hybrid-FPUs (Hybrid-Precision Floating-Point Multipliers) and one N-input 16-bit pipelined adder tree. The Hybrid-FPUs reuse the DSP48EIP core and support three precision operations: hfp16-int8, hfp16-hfp16, and int8-int8. Simultaneously, one hfp16 vector inner product or two int8 vector inner products can be executed. The adder tree employs a log2N-stage pipeline design; when N=16, the pipeline stages are 4, and the output data width is 32 bits.
4. The artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs according to claim 1, characterized in that, The three-dimensional matrix inner product operation unit (MMU) adopts an N×NPE array architecture, where N≥4. Each PE unit is an int8 precision vector inner product unit, containing N fixed-point multipliers and one addition tree. PEs in the same row share a row of input from matrix A, and PEs in the same column share a column of input from matrix B. PE[i,j] performs the inner product operation between A[i,:] and B[:,j]. N operations can be performed in parallel in one clock cycle. 3 Multiplication and associative addition operations are supported; matrix block tiling optimization is supported, and the storage configurations of "large Z small Z", "large N small N", and "large N small Z" are adapted for large matrix operations.
5. The artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs according to claim 1, characterized in that, The multi-level cache and control unit of the dedicated neural network processor (NPU) includes a dedicated cache for matrix inner product and a unified cache (Unified-Buffer). The dedicated cache for matrix inner product includes Buffer-A, Buffer-B, and Buffer-C. Buffer-A, Buffer-B, and Buffer-C store the input matrices A and B and the output matrix C, respectively, while the Unified-Buffer stores vector operation data. The CPU and the dedicated neural network processor (NPU) alternately access different cache partitions to achieve parallel execution of data transmission and computation, thereby reducing memory access latency.
6. A method for accelerating an artificial intelligence algorithm for real-time junction temperature prediction of IGBTs, implemented based on the artificial intelligence algorithm acceleration system for real-time junction temperature prediction of IGBTs as described in any one of claims 1-5, characterized in that, Includes the following steps: Step 1: System initialization. The ARM processor reads the pre-stored BP neural network model weights and configuration parameters, loads them into DDR3 memory, and completes the initialization of the dedicated neural network processor NPU, sensor driver, and communication interface. Step 2: Real-time parameter acquisition; the parameter acquisition module synchronously acquires the V of the IGBT. CE（Sat） I C and T C， After analog-to-digital conversion and isolated transmission, the data is sent to the artificial intelligence algorithm acceleration module. Step 3: Data preprocessing. The ARM processor normalizes the raw parameters, removes outlier data, and packages them into a 3D input vector. Step 4: Approximate Prior Vector Inner Product (AVIP) Operation. The dedicated Neural Processing Unit (NPU) divides the weight vector into K continuous sub-regions, selects a subset of effective parameters to perform low-precision inner product operation, and filters out effective operations. Step 5: Hardware-accelerated inference of BP neural network, which completes the calculation of each layer based on the mixed precision architecture of the dedicated neural network processor NPU and outputs the intermediate results of junction temperature prediction; Step 6: Post-processing of results. Perform inverse normalization and smoothing on the intermediate results to obtain the actual junction temperature value. Step 7: Data transmission and storage, upload the junction temperature value and original parameters to the host computer; Step 8: Repeat steps 2 to 7 to achieve continuous real-time monitoring; Step 9: Anomaly Alarm. When the host computer detects that the junction temperature exceeds the threshold or that the parameters are abnormal, it triggers an alarm and sends a protection signal.
7. The artificial intelligence algorithm acceleration method for real-time junction temperature prediction of IGBTs according to claim 6, characterized in that, The specific implementation of the Approximate Prior Vector Inner Product (AVIP) method described in step 4 includes: Step 41: Analyze the pre-trained BP neural network model offline, and divide the weight vectors of each layer with a length of N into K continuous sub-regions of equal length, where K = 2, 4 or 8; Step 42: Calculate the sum of the absolute values of the elements within each sub-region, and select the sub-region with the largest sum of absolute values as the effective parameter subset; Step 43: Perform a low-precision inner product operation on the input vector and the effective parameter subset, while scaling the bias value proportionally by K, b→b / K; Step 44: Determine the sign of the inner product result. If it is not positive, ignore the operation; if it is positive, retain it and perform the subsequent complete high-precision inner product operation.
8. The artificial intelligence algorithm acceleration method for real-time junction temperature prediction of IGBTs according to claim 6, characterized in that, The specific implementation of hardware-accelerated inference of the BP neural network in step 5 includes: Step 51: Input layer to first hidden layer: Using the hfp16-hfp16 mode of Hybrid-VPU, the vector inner product API is called, and the operation of 3 inputs → 16 outputs is completed in 16 iterations; Step 52: Intermediate hidden layer, 3 layers in total: Using the MMU's int8 precision mode, combined with the effective operation columns filtered by AVIP, the matrix inner product API is called to complete the 16×16 matrix inner product through block operation; Step 53: Output layer: Using the hfp16-hfp16 mode of Hybrid-VPU, the vector accumulation API is called to split the 16 inputs into 4 sub-vectors of length 4, and accumulate them in batches to obtain a 1 junction temperature prediction value. Step 54: After each layer operation, the ReLU activation function is executed to suppress negative values and reduce invalid computation propagation.
9. The artificial intelligence algorithm acceleration method for real-time junction temperature prediction of IGBTs according to claim 6, characterized in that, The normalization range for the data preprocessing described in step 3 is 0~1, and the linear normalization formula is: x_norm=(x-x_min) / (x_max-x_min); Among them, V CE（Sat） The normalized range corresponds to the actual voltage 0~1V, I C Corresponding to 20~200A, T C The corresponding temperature range is 25~150℃; outlier data is removed using the 3σ criterion, which removes data points that fall outside the range of [x_mean-3σ, x_mean+3σ].
10. The artificial intelligence algorithm acceleration method for real-time junction temperature prediction of IGBTs according to claim 6, characterized in that, The post-processing of the results described in step 6 uses a moving average filter with a window size of 5, and the formula is as follows: The inverse normalization formula is: ,in , This ensures that the output junction temperature value matches the actual physical range.