High-performance network devices with multi-protocol convergence

Abstract

This invention discloses a high-performance network device with multi-protocol fusion, comprising an application layer, a network fusion layer, a data link layer, and a physical layer connected in sequence. The application layer is configured to perform high-speed data interaction with the network fusion layer via the AXI-Stream protocol. The network fusion layer is configured to identify and parse the input data packets, converting data frames from Interlaken, Aurora, Ethernet, and FC protocols into a unified AXI-Stream format and providing error detection flags to the upper layer. The data link layer is configured to generate, encapsulate, and encode frame structures according to the frame format requirements of different network protocols based on the standardized data stream output by the network fusion layer. The physical layer includes a high-speed SerDes module for implementing serial-to-parallel conversion. The high-performance network device with multi-protocol fusion provided by this invention significantly improves system parallelism, transmission bandwidth, and reliability, while reducing CPU processing burden and transmission latency by implementing multi-protocol fusion and a unified interface at the hardware level.

Description

Technical Field

[0001] This invention belongs to the field of network communication technology, and specifically relates to a high-performance network device that integrates multiple protocols. Background Technology

[0002] With the development of cloud computing, data centers, high-performance computing, distributed storage systems and reconfigurable accelerators, a single platform cannot meet the diverse and high-performance computing needs. Heterogeneous computing across different platforms is increasingly becoming a solution to these computing needs, while also placing higher demands on high-bandwidth and low-latency data communication. Since the communication protocols between different devices are different, it is urgent to develop high-performance network devices that support the integration of multiple communication protocols.

[0003] Research in the field of network multi-protocol fusion has developed rapidly in recent years, but it also has its shortcomings. Some designs for IoT gateways using the Node-Red platform employ software-based multi-protocol fusion, heavily relying on and consuming CPU resources, resulting in poor parallel processing and thus bottlenecking network performance. Others utilize FPGAs to implement conversion processes for various low-speed protocols such as Bluetooth and Wi-Fi, but these cannot meet the demands of high-bandwidth and low-latency networks. Summary of the Invention

[0004] This invention provides a high-performance network device that integrates multiple protocols to solve the technical problem of inaccurate traditional early warning methods mentioned above. Specifically, the technical solution is as follows:

[0005] A high-performance network device integrating multiple protocols includes an application layer, a network convergence layer, a data link layer, and a physical layer connected in sequence. The application layer is configured to perform high-speed data interaction with the network convergence layer via the AXI-Stream protocol. The network convergence layer is configured to identify and parse the input data packets, convert data frames from Interlaken, Aurora, Ethernet, and FC protocols into a unified AXI-Stream format, and provide error detection flags to the upper layer. The data link layer is configured to generate, encapsulate, and encode frame structures according to the frame format requirements of different network protocols based on the standardized data stream output by the network convergence layer. The physical layer includes a high-speed SerDes module for implementing serial-to-parallel conversion.

[0006] Furthermore, when processing the Interlaken protocol, the network fusion layer includes an Interlaken transmitter bus conversion module, a burst format generation module, a burst format parsing module, an Interlaken receiver bus conversion module, an Interlaken frame header alignment module, and a first error detection module;

[0007] The Interlaken transmitter bus conversion module is used to convert AXI-Stream format data to Interlaken LBUS format and perform endianness conversion, and generate BCTL flags according to the burst transmission optimization algorithm;

[0008] The burst format generation module is used to encapsulate data into Interlaken Burst format according to the BurstMax and BurstShort parameters;

[0009] The burst format parsing module is used to parse the received Interlaken Burst format data;

[0010] The Interlaken receiver bus conversion module is used to convert Interlaken LBUS format data into AXI-Stream format; the Interlaken frame header alignment module is used to complete frame header alignment.

[0011] The first error detection module is used to detect CRC errors, excessively long frames, excessively short frames, and abnormal frame end characters, and sets specific error flags.

[0012] Furthermore, when processing the Interlaken protocol, the data link layer includes a meta frame generation module, a first encoding module, a first decoding module, and a meta frame parsing module;

[0013] The Meta frame generation module is used to divide the Interlaken Burst data into 8-byte data blocks, which are then distributed to each channel sequentially and packaged into Meta frame format when there are multiple channels in the physical layer.

[0014] The first encoding module is used to perform specific encoding on the Meta frame to achieve DC balance;

[0015] The first decoding module is used to decode the received Meta frames;

[0016] The Meta frame parsing module is used to parse the decoded Meta frame, extract synchronization word and check word information, and extract valid data based on these flags to obtain Interlaken Burst format data.

[0017] Furthermore, when processing the Aurora protocol, the network convergence layer includes a transmitter bit width conversion module, a transmitter clock domain conversion module, a data block segmentation module, a data block reassembly module, a receiver bit width conversion module, a receiver clock domain conversion module, and a second error detection module;

[0018] The transmitting end bit width conversion module is used to convert application layer AXI-Stream data into AXI-Stream data bit width supported by the Aurora protocol;

[0019] The transmitting end clock domain conversion module is used to convert data from the application layer clock domain to the network convergence layer clock domain;

[0020] The data segmentation module is used to divide the data frame into 8-byte data blocks, and add a Separator data block after the last data block of each frame.

[0021] The Separator data block includes the CRC check data of the current frame and the frame end information;

[0022] The data block reassembly module is used to parse the data block into an AXI-Stream format data frame defined by Aurora based on the relevant information provided by the Separator data block, and at the same time generate CRC check data and compare it with the CRC data in the Separator data block.

[0023] The receiving end bit width conversion module is used to convert the Aurora protocol data frame into the data bit width specified by the upper layer protocol.

[0024] The receiving end clock domain conversion module is used to convert data into the clock domain of the upper layer protocol;

[0025] The second error detection module is used to detect whether the frame length meets the requirements by counting, perform frame verification according to the CRC signal provided by the data reassembly module, detect whether the frame end character is normal, and set a specific error flag.

[0026] Furthermore, when processing the Aurora protocol, the data link layer includes a second encoding module and a second decoding module;

[0027] The second encoding module is used to perform unified encoding on data blocks and Separator blocks;

[0028] The second decoding module is used to decode the data block and the Separator block according to the protocol.

[0029] Furthermore, when processing the Ethernet protocol, the network convergence layer includes a data buffer module, a read / write control module, an Ethernet transmitter bus conversion module, a MAC framing module, an Ethernet frame header alignment module, an Ethernet receiver bus conversion module, a MAC parsing module, and a third error detection module.

[0030] The data buffer module is used to store data transmitted by the upper-layer protocol;

[0031] The read / write control module is used to realize continuous transmission within an Ethernet frame. When it is detected that a complete frame of data is stored in the data buffer module, a data frame is read from the data buffer module and written to the MAC frame module without interruption.

[0032] The Ethernet transmitter bus conversion module is used to convert continuous AXI-Stream format data within a frame into Ethernet LBUS format data;

[0033] The MAC framing module is used to add the corresponding Ethernet frame header and frame trailer to form a MAC frame;

[0034] The Ethernet frame header alignment module is used to complete frame header alignment and obtain Ethernet LBUS format data with frame header alignment;

[0035] The Ethernet receiver bus conversion module is used to convert Ethernet LBUS format data into AXI-Stream format data; the MAC parsing module is used to convert MAC frames into Ethernet LBUS format data, and at the same time recalculate the FCS and compare it with the received FCS to determine the correctness of the data frame transmission.

[0036] The third error detection module is used to perform CRC error detection, frame length detection, and frame end character error detection, and to set specific error flags.

[0037] Furthermore, when processing the Ethernet protocol, the data link layer includes a third encoding module and a third decoding module;

[0038] The third encoding module is used to encode MAC frames;

[0039] The third decoding module is used to decode the received data to obtain the content of the MAC frame.

[0040] Furthermore, when processing the FC protocol, the network convergence layer includes an FC transmitter bus conversion module, an FC receiver bus conversion module, and a fourth error detection module;

[0041] The FC transmitter bus conversion module is used to convert AXI-Stream data into a customized data frame format for the FC protocol.

[0042] The FC receiver bus conversion module is used to convert FC customized data into AXI-Stream format;

[0043] The fourth error detection module is used to perform frame length detection and frame end character detection, cooperate with the FC receiver control module to implement CRC check detection, and set specific error flags.

[0044] Furthermore, when processing the FC protocol, the data link layer includes an FC transmission control module, a fourth encoding module, a fourth decoding module, an FC receiver control module, an FC frame header alignment module, and an FC protocol word validity / primitive detection module;

[0045] The FC transmission control module is responsible for link establishment, CRC check code generation, and credit flow control.

[0046] The fourth encoding module is used to complete data encoding;

[0047] The fourth decoding module is used to complete data decoding;

[0048] The FC receiver control module is used to complete the response mechanism and CRC check detection function, and works in conjunction with the fourth error detection module.

[0049] The FC frame header alignment module is used to complete frame header alignment;

[0050] The FC protocol word validity / primitive detection module is used to determine whether the data conforms to the requirements of the FC protocol. If valid data is detected, the data is passed to the FC frame header alignment module.

[0051] Furthermore, the AXI-Stream format includes TVALID, TREADY, TKEEP, TLAST, and TUSER signals;

[0052] The TVALID indicates whether the current data is valid;

[0053] TREADY is a flag bit from the network fusion layer. If it is 1, it means that data can now be received from the upper layer.

[0054] The TKEEP indicates which positions of the 512 bits of data sent are valid, with each bit corresponding to 32 bits of validity. It is used in conjunction with TLAST to indicate which bits are invalid in the last data frame.

[0055] The TLAST indicates the end-of-frame marker;

[0056] The TUSER includes TUSER[0] frame start flag, TUSER[1] CRC check error flag, TUSER[2] long frame error flag, TUSER[3] short frame flag, TUSER[4] frame end character abnormal flag, and TUSER[7:5] reserved bits;

[0057] The network convergence layer is configured to automatically set the corresponding error flag and report it to the application layer when a corresponding error is detected, so that the application layer can execute error correction or retransmission strategies.

[0058] The high-performance network device with multi-protocol convergence provided by this invention integrates high-performance network protocols such as Interlaken, Aurora, Ethernet, and FC (Fiber Channel) on the hardware device, which is conducive to building a high-bandwidth, low-latency network architecture and provides technical support for high-performance distributed computing and multi-device access. It is suitable for high-speed data interconnection in heterogeneous computing, data centers, high-performance computing, and distributed storage systems.

[0059] The high-performance network device with multi-protocol fusion provided by this invention enables communication using multiple high-performance network protocols and provides a unified data format to the upper layer, laying the foundation for multi-device communication in heterogeneous computing. Simultaneously, the multi-protocol fusion process of this device is implemented in hardware, reducing the CPU processing burden and significantly improving system parallelism. Furthermore, this design provides multiple error detection mechanisms, laying the foundation for error detection and mis-frame retransmission functions in upper-layer protocols.

[0060] The high-performance network device with multi-protocol fusion provided by this invention implements a cross-protocol error detection mechanism (such as CRC error, frame length detection, etc.) at the protocol fusion layer to ensure high communication reliability, which is also a necessary condition for the faulty frame retransmission mechanism.

[0061] The high-performance network device with multi-protocol convergence provided by this invention combines the streaming architecture of Aurora / Interlaken with the frame structure of Ethernet / FC to achieve high network throughput and low overhead. It integrates lightweight network protocols and general-purpose network protocols into a unified network architecture, thereby improving the scalability and versatility of the system. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the Interlaken protocol fusion transmission process of a high-performance network device with multi-protocol fusion according to the present invention;

[0064] Figure 2This is a schematic diagram of the Aurora protocol fusion transmission process of a high-performance network device with multi-protocol fusion according to the present invention;

[0065] Figure 3 This is a schematic diagram of the Ethernet protocol fusion transmission process of a high-performance network device with multi-protocol fusion according to the present invention;

[0066] Figure 4 This is a schematic diagram of the FC protocol fusion transmission process of a high-performance network device with multi-protocol fusion according to the present invention;

[0067] Figure 5 This is a schematic diagram illustrating the process of frame header alignment achieved by the variable sliding window of the present invention. Detailed Implementation

[0068] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0069] This application discloses a high-performance network device with multi-protocol convergence, comprising an application layer, a network convergence layer, a data link layer, and a physical layer connected in sequence.

[0070] The application layer is configured to interact with the network convergence layer at high speed via the AXI-Stream protocol. Located at the top of the entire system protocol stack, the application layer is primarily responsible for the interaction between upper-layer business logic and data transmission interfaces. This layer communicates with lower layers at high speed using a customized AXI-Stream (Advanced eXtensible Interface Stream) protocol.

[0071] AXI-Stream, a widely adopted standard bus interface protocol in embedded and FPGA systems, features high bandwidth, low latency, and excellent streaming data characteristics, making it suitable for scenarios such as hardware / software co-design and real-time data transmission. In this design, data interaction between the application layer and lower layers uniformly adopts the AXI-Stream format to standardize the data channel and improve system compatibility and scalability. The AXI-Stream data format is shown in the table below. This design facilitates seamless integration with subsequent upper-layer application modules (such as distributed computing, data compression, or security encryption modules).

[0072] Specifically, the AXI-Stream data format is shown in the table below, including TVALID, TREADY, TKEEP, TLAST, and TUSER signals. This design facilitates seamless integration with subsequent higher-layer application modules (such as distributed computing, data compression, or security encryption modules).

[0073] Table 1 Application Layer Custom AXI-Stream Protocol Format

[0074] Signal Bit width Data source describe TDATA 512 main equipment Data Stream TVALID 1 main equipment valid signal for data stream TREADY 1 From the equipment The device can receive data flags. TKEEP 16 main equipment Data stream validity flag, each bit indicates whether the 32 bits of data are valid. TUSER 8 main equipment Custom data format TUSER[0]: Start of frame flag TUSER[1]: CRC check error TUSER[2]: Oversized frame error TUSER[3]: Oversized frame flag TUSER[4]: End of frame exception flag TUSER[7:5]: Reserved bits TLAST 1 main equipment End of frame marker

[0075] TVALID indicates whether the current data is valid. TREADY is a flag bit from the network convergence layer; a value of 1 indicates that data transmitted from the upper layer can now be received. TKEEP indicates which bits of the transmitted 512 bits are valid, with each bit corresponding to 32 bits of validity. It is used in conjunction with TLAST to indicate which bits are invalid in the last frame of data. In the multi-protocol converged high-performance network device of this application, each bit of TKEEP corresponds to 32 bits of validity. TLAST indicates the end-of-frame flag. TUSER includes TUSER[0] start frame flag, TUSER[1] CRC check error flag, TUSER[2] over-length frame error flag, indicating that the frame length exceeds the space limit reserved in the buffer and the requirements of the corresponding protocol, indicating that an error has occurred during transmission, TUSER[3] over-short frame flag, indicating that if the length of the frame is shorter than the minimum frame length specified by the protocol, its transmission cannot be supported, or data loss has occurred during transmission, TUSER[4] end frame character abnormal flag, indicating that an error was detected in the previous processing and the current frame has an error, TUSER[7:5] are reserved bits for subsequent function expansion.

[0076] The network convergence layer is configured to automatically set the corresponding error flag and report it to the application layer when a corresponding error is detected, so that the application layer can execute error correction or retransmission strategies.

[0077] The network convergence layer is configured to identify and parse the incoming data packets, convert data frames from Interlaken, Aurora, Ethernet and FC protocols into a unified AXI-Stream format, and provide error detection flags to the upper layers.

[0078] Specifically, the network convergence layer is one of the core layers of the system protocol framework, mainly responsible for the parsing, conversion, and unified management of various network protocols. This layer identifies and parses the input data packets, converting data frames from different networks (including Interlaken, Aurora, Ethernet, and FC protocols) into the device's uniformly customized AXI-Stream format.

[0079] Meanwhile, the network convergence layer undertakes the functions of integrity and reliability detection of data transmission, including CRC check, frame structure validity detection, and data length verification. When an error is detected (such as CRC error, abnormal frame end marker, data length mismatch, etc.), the system automatically sets the error flag and reports it to the upper-layer protocol module so that the upper-layer protocol can take timely error correction or retransmission strategies. On this basis, the system can realize secure and reliable communication across multiple protocols.

[0080] Furthermore, the high-performance network device integrating multiple protocols in this application supports upper-layer applications using cut-through mode, which can effectively reduce transmission latency. This function requires differentiated processing at the network protocol layer according to different protocol requirements, as detailed in the subsequent analysis.

[0081] The data link layer is configured to generate, encapsulate, and encode frame structures according to the standardized data stream output by the network convergence layer, following the frame format requirements of different network protocols. In terms of encoding, the data link layer can leverage the characteristics of the target physical interface to achieve efficient frame transmission, ensuring robustness and anti-interference capabilities of data transmission over the physical medium.

[0082] The physical layer includes a high-speed SerDes module for serial-to-parallel conversion. Located at the bottom of the protocol stack, the physical layer is responsible for the final transmission and reception of electrical / optical signals. This layer primarily consists of high-speed SerDes (Serializer / Deserializer) modules, implementing parallel-to-serial and serial-to-parallel conversion operations, thereby supporting high-speed link communication up to hundreds of Gbps. The physical layer employs differential signal transmission and clock data recovery techniques to reduce jitter and signal interference, achieving stable and reliable data transmission. Ultimately, data output from the physical layer can be directly transmitted between chips, boards, or across nodes, providing a high-bandwidth, low-latency hardware foundation for upper-layer protocols.

[0083] Interlaken is a high-bandwidth, scalable inter-chip communication protocol designed to replace traditional parallel protocols such as SPI4.2. At the data link layer, Interlaken combines the advantages of parallel data packet transmission, while at the physical layer it uses a high-speed serial port design instead of source clock synchronization, increasing data transmission rates. It provides a lightweight, efficient, reliable, and high-bandwidth data packet transmission method, making it commonly used for high-speed data packet transmission between chips and a crucial interconnect technology for building high-performance network systems.

[0084] like Figure 1As shown, when processing the Interlaken protocol, the network convergence layer includes an Interlaken transmitter bus conversion module, a burst format generation module, a burst format parsing module, an Interlaken receiver bus conversion module, an Interlaken frame header alignment module, and a first error detection module. The Interlaken transmitter bus conversion module converts AXI-Stream format data to Interlaken LBUS format and performs endianness conversion, generating BCTL flags according to the burst transmission optimization algorithm. The burst format generation module encapsulates data into Interlaken Burst format according to the BurstMax and BurstShort parameters. The burst format parsing module parses the received Interlaken Burst format data. The Interlaken receiver bus conversion module converts Interlaken LBUS format data to AXI-Stream format. The Interlaken frame header alignment module performs frame header alignment. The first error detection module detects CRC errors, excessively long frames, excessively short frames, and abnormal frame end-of-frame markers, and sets specific error flags.

[0085] The data link layer includes a Meta frame generation module, a first encoding module, a first decoding module, and a Meta frame parsing module. The Meta frame generation module divides Interlaken Burst data into 8-byte blocks, which are then distributed sequentially to each channel when there are multiple channels in the physical layer and packaged into Meta frame format. The first encoding module performs specific encoding on the Meta frames to achieve DC balance. The first decoding module decodes the received Meta frames. The Meta frame parsing module parses the decoded Meta frames, extracts synchronization and checksum information, and extracts valid data based on these flags to obtain Interlaken Burst format data.

[0086] Specifically, the upper-layer protocol first encapsulates the data packets into data frames in a custom AXI-Stream (abbreviated as AXIS in the diagram) format.

[0087] After the network convergence layer receives the data, the Interlaken transmitter bus conversion module first parses the AXI-Stream format data and converts it into Interlaken LBUS format data frames. Interlaken LBUS data is divided into four segments, each containing 128 bits of data and corresponding control signals such as ENABLE, SOP, EOP, and EMPTY. ENABLE indicates that the data in the current segment is valid, SOP is the start of frame flag, and EMPTY indicates whether there are any invalid bits in the current segment's data; it is used in conjunction with the EOP frame end signal. The Interlaken transmitter bus conversion module converts the AXI-Stream flags TVALID, TLAST, and TUSER into the Interlaken LBUS bus flags ENABLE, SOP, EOP, and EMPTY. Furthermore, AXI-Stream and LBUS have different endianness formats; AXI-Stream uses big-endian, while LBUS divides the 512-bit data into four segments, with each segment using little-endian internally, requiring endianness conversion. In addition, Interlaken LBUS also includes a BCTL flag related to burst generation. According to the burst transmission optimization algorithm, if the effective data length of the last burst is detected to be less than BurstShort (minimum burst length), then BCTL is inserted into the data of the penultimate burst. BurstMin (the truncation length of the optimization algorithm) data is taken from the penultimate burst and left for transmission in the last burst. This ensures that IDLE control words are not inserted into the Interlaken Burst generated by the data, thereby increasing the proportion of effective data. This completes the bus conversion process.

[0088] Interlaken LBUS data enters the burst format generation module, which encapsulates the data into a specified burst format according to the Interlaken protocol. This involves inserting the data to be transmitted between multiple control words according to the given BurstMax (maximum burst length) and BurstShort (minimum burst length). Simultaneously, special processing is performed during the generation of the last two Interlaken Bursts, in conjunction with the BCTL signal of the Interlaken LBUS bus. The control word contains information related to frame start, end, and channel flow control.

[0089] Next, the data enters the data link layer, where the Meta frame generation module converts the generated Interlaken Burst into Meta frames. If multiple channels in the physical layer are transmitting data simultaneously, the Interlaken Burst data is divided into 8-byte blocks and distributed sequentially to each channel. Each channel then packages the data into a physical layer Meta frame format. The encoding module performs specific encoding on the Meta frames to be transmitted, which is beneficial for DC balance during transmission and clock recovery at the receiving end. Afterward, the data is handed over to the physical layer's high-speed SerDes for cross-chip transmission.

[0090] After the data is transmitted to the receiving end, the physical layer receives the data, recovers the clock information, samples the data using the clock, and completes the serial-to-parallel conversion. The data link layer's decoding module decodes the data to obtain a Meta frame. The Meta frame parsing module parses the Meta frame, extracts information such as synchronization words and check words, and extracts valid data based on these flags to obtain Interlaken Burst format data.

[0091] At the network fusion layer, the burst parsing module extracts the flag bits of the Burst Control Word, including SOP, EOP, EMPTY, CRC24, Flow Control, etc., converts this information into Interlaken LBUS flag bits, obtains valid data, and fills the data fields of the Interlaken LBUS. At this point, the Interlaken LBUS data in the same frame may simultaneously contain the EOP of the previous frame and the SOP of the next frame. The close proximity of two frames is not conducive to subsequent detection and storage; therefore, frame header alignment is required first, placing the frame header of each frame in the least significant bit of the 512-bit data to facilitate subsequent processing. This invention uses a variable sliding window reading method, with the reading window size determined by the LBUS flag bits. First, the data of the four segments of the received LBUS is written to the buffer. If valid data exists in the four segments, all data from the four segments is written to the buffer, with four segments as the unit of writing. Figure 5This describes a four-read process. In the first read, Segment 0 is the SOP (Start of Production), and the remaining three segments are valid data. Therefore, the first sliding window size is 4, and valid data from four segments is read. In the second read, the first two segments are detected as valid data, the third segment as a valid EOP (End of Production) signal, and the fourth as the SOP signal for the next frame. To place the SOP signal for the next frame in the least significant bit of the 512-bit buffer, the SOP signal of the last segment is not read this time; only the EOP and preceding information are read. Data less than 512 bits and the corresponding flag bits are padded with 0s. The window size for this read is 3, and valid data from three segments is obtained. In the third read, the first four data in the buffer include one SOP and three valid data. Therefore, the window size is 4, and four valid data are read, achieving the goal of placing the SOP in the least significant bit. During the fourth read, the first four data points consist of one valid data point, one valid EOP (Extended Opening) data point, and two invalid data points, without including SOP (Segment Opening) information. Therefore, four Segment data points are read directly, with invalid data padded with 0s. The read window size is 4, and two valid data points are obtained. In the next read, the SOP will be at the beginning of the buffer, so it can be placed in the least significant bit of the data. The subsequent data alignment process will then proceed as described above.

[0092] After obtaining the aligned data, bus conversion and error detection are performed synchronously. The processing of the Interlaken receiver bus conversion module is the reverse process of the transmitter bus conversion, converting the Interlaken LBUS data after frame header alignment into AXI-Stream format data. The error detection process is performed synchronously with the bus conversion to reduce system latency. The error detection module performs various error detection and reporting. When the Interlaken protocol is transmitted at the data link layer, it includes CRC24 check based on burst transmission and CRC32 check based on Meta frame. The range of CRC32 check is the Meta frame check of the channel, and the range of CRC24 is the check of the current burst. Based on the above two checks, it is possible to check whether CRC error occurs during frame transmission. If there is an error, Tuser[1] is pulled high at the end of the frame. At the same time, during the bus conversion process, the flag bit is used to count the valid data. If it exceeds or does not meet the protocol requirements, Tuser[2] and Tuser[3] are pulled high accordingly. When an EOP is received, the frame end symbol is checked to see if it matches the corresponding end symbol of the protocol to determine the correctness of the data. If it is not a normal frame end symbol, Tuser[4] is pulled high. At this point, the receiver obtains unified AXI-Stream data and provides the data to the upper layer protocol, realizing the entire process of Interlaken protocol fusion.

[0093] The Aurora protocol is a lightweight, scalable link-layer protocol for point-to-point serial link transmission. It sits between the physical layer and upper-layer protocols, providing a transparent interface to the physical layer, enabling user-defined or standard protocols to communicate directly using high-speed transceivers. Aurora achieves low-latency, high-bandwidth data transmission with minimal logic resources, supports multi-channel parallel expansion and flexible configuration, and is widely used in high-speed inter-chip interconnects, inter-board communication, and reconfigurable systems. This application's multi-protocol fusion high-performance network device integrates Aurora to provide a channel for point-to-point short-distance data transmission.

[0094] like Figure 2 As shown, when processing the Aurora protocol, the network convergence layer includes a transmitter bit-width conversion module, a transmitter clock domain conversion module, a data segmentation module, a data block reassembly module, a receiver bit-width conversion module, a receiver clock domain conversion module, and a second error detection module. The transmitter bit-width conversion module converts application-layer AXI-Stream data into the AXI-Stream data bit width supported by the Aurora protocol. The transmitter clock domain conversion module converts data from the application-layer clock domain to the network convergence layer clock domain. The data segmentation module divides the data frame into 8-byte blocks and adds a Separator data block after the last data block of each frame. The Separator data block includes the CRC checksum of the current frame and frame end information. The data block reassembly module parses the data block into an AXI-Stream format data frame defined by Aurora based on the information provided by the Separator data block, and generates CRC checksum data to compare with the CRC data in the Separator data block. The receiver bit-width conversion module converts Aurora protocol data frames into the data bit width specified by the upper-layer protocol. The receiver clock domain conversion module converts data into the clock domain of the upper-layer protocol. The second error detection module checks whether the frame length meets the requirements by counting, performs frame verification based on the CRC signal provided by the data reassembly module, checks whether the frame end symbol is normal, and sets specific error flags.

[0095] Furthermore, the data link layer includes a second encoding module and a second decoding module. The second encoding module is used to uniformly encode data blocks and separator blocks. The second decoding module is used to decode data blocks and separator blocks according to the protocol specifications.

[0096] Specifically, the upper-layer protocol encapsulates the data into specific AXI-Stream data before transmitting it to the network convergence layer. The network convergence layer's sender-side bit-width conversion module and sender-side clock domain conversion module work synchronously to reduce system latency. The bit-width conversion module converts the application-layer AXI-Stream data to the AXI-Stream data bit width supported by the Aurora protocol, while the clock domain conversion module converts the data from the application-layer clock domain to the network convergence layer clock domain. The data packet enters the data segmentation module, where the data frame is divided into 8-byte blocks. A separator block is added after the last data block of each frame. The separator block includes the CRC checksum of the current frame and frame end information. The data blocks and separator blocks reach the data link layer, where they are uniformly encoded by the encoding module. Finally, the high-speed SerDes at the physical layer completes the signal transmission between chips.

[0097] After receiving data at the high-speed Serded physical layer, the receiving end performs serial-to-parallel conversion and uploads the data to the data link layer. The decoding module at the data link layer decodes the data blocks and separator blocks according to the protocol specifications. The decoded data continues into the network convergence layer. The data block reassembly module parses the database into AXI-Stream format data frames defined by Aurora based on the information provided by the separator block, and simultaneously generates CRC check data. This CRC data is compared with the CRC data in the separator block to verify the correctness of the data transmission; this signal can be used to report CRC errors. The receiving end clock domain conversion and receiving end bit width conversion modules convert the Aurora protocol data frames into the data bit width and clock domain specified by the upper-layer protocol. Simultaneously, the error detection module counts to check if the frame length meets the requirements, performs frame verification based on the CRC signal provided by the data reassembly module, checks if the frame end symbol is normal, sets specific error flags to 0 or 1, and provides the customized AXI-Stream format data to the upper-layer application.

[0098] Ethernet is currently the most widely used standardized network communication protocol, conforming to the IEEE 802.3 standard, and is widely used in LANs (Local Area Networks), data center interconnects, and high-performance computing platforms. This application's multi-protocol converged high-performance network device supports Ethernet MAC and PHY layer protocols, and converges data frames above the MAC layer, improving the scalability of the converged network and facilitating the access of general-purpose network devices.

[0099] like Figure 3 As shown, when processing the Ethernet protocol, the network convergence layer includes a data buffer module, a read / write control module, an Ethernet transmitter bus conversion module, a MAC framing module, an Ethernet frame header alignment module, an Ethernet receiver bus conversion module, a MAC parsing module, and a third error detection module. The data buffer module stores data transmitted by upper-layer protocols. Application layer networks support cut-through mode, forwarding data to the network convergence layer even before a frame is fully received. However, Ethernet frame transmission cannot be interrupted, thus requiring a read / write control module. This module ensures continuous transmission within the Ethernet frame, guaranteeing its continuity. When a complete frame is detected in the data buffer module, a data frame is read from the buffer and continuously written to the MAC framing module. The Ethernet transmitter bus conversion module converts continuous AXI-Stream format data within the frame into Ethernet LBUS format data. The MAC framing module adds the appropriate Ethernet frame header and trailer to form a MAC frame. The Ethernet frame header alignment module aligns the frame header to obtain header-aligned Ethernet LBUS format data. The Ethernet receiver bus conversion module converts Ethernet LBUS format data to AXI-Stream format data. The MAC parsing module converts MAC frames to Ethernet LBUS format data, recalculates the FCS, compares it with the received FCS, and verifies the correctness of the data frame transmission. The third error detection module performs CRC error detection, frame length detection, and frame end-of-frame error detection, and sets specific error flags.

[0100] When processing Ethernet protocols, the data link layer includes a third encoding module and a third decoding module. The third encoding module is used to encode MAC frames. The third decoding module is used to decode the received data to obtain the content of the MAC frame.

[0101] Specifically, the upper-layer protocol packages data into AXI-Stream format and delivers it to the network convergence layer. The network convergence layer first writes the data into a data buffer module for storage, and the read / write control module reads the frames. Since Ethernet transmits data in frames, it requires uninterrupted transmission from the preamble to the FCS (Frame Check Sequence). The high-performance network device of this application, which integrates multiple protocols, supports cut-through mode in its upper-layer protocol, allowing frames to be transmitted even before complete reception. Therefore, a read / write control module needs to be added to the Ethernet protocol convergence. When at least one complete frame is detected in the buffer, the read / write control module reads a data frame from the data buffer module and writes it uninterruptedly to the MAC framing module; otherwise, the current frame will be recorded as an error frame, affecting the data transmission process. Next, the Ethernet transmitter bus conversion module converts the continuous AXI-Stream format data within the frame into Ethernet LBUS format data. The MAC framing module then adds the corresponding Ethernet frame header and trailer to form a MAC frame. After encoding by the data link layer's encoding module, it is delivered to the physical layer's SerDes for transmission.

[0102] After receiving data, the physical layer's high-speed SerDes performs a serial-to-parallel conversion. The data then enters the data link layer's decoding module to obtain the MAC frame content. The MAC parsing module converts the MAC frame into Ethernet LBUS format data, recalculates the FCS (Frame Cross Section), and compares it with the received FCS to verify the correctness of the data frame transmission. At this point, the data may still have a missing least significant bit in the frame header. The data then enters the Ethernet header alignment module to perform header alignment, resulting in header-aligned Ethernet LBUS format data. The error detection module performs CRC error detection, frame length detection, and frame end-of-frame error detection. Simultaneously, the Ethernet receiver bus conversion module converts the Ethernet LBUS format data into AXI-Stream format data, which is finally delivered to the upper-layer application for processing.

[0103] FC protocol is a high-throughput, low-latency, and high-reliability network technology that is widely used in high-performance storage, database centers, and cluster systems. The multi-protocol integrated high-performance network device of this application integrates the FC network protocol and can achieve high-speed interconnection with external SAN (Storage Area Network) devices, providing an interface for the access of storage devices.

[0104] like Figure 4As shown in the embodiments of this application, when processing the FC protocol, the network convergence layer includes an FC transmitter bus conversion module, an FC receiver bus conversion module, and a fourth error detection module. The FC transmitter bus conversion module is used to convert AXI-Stream data into a customized data frame format for the FC protocol. The FC receiver bus conversion module is used to convert customized FC data into AXI-Stream format. The fourth error detection module is used to perform frame length detection, frame end-of-frame detection, cooperate with the FC receiver control module to implement CRC checksum detection, and set specific error flags.

[0105] When processing the FC protocol, the data link layer includes an FC transmit control module, a fourth encoding module, a fourth decoding module, an FC receiver control module, an FC header alignment module, and an FC protocol word validity / primitive detection module. The FC transmit control module is responsible for link establishment, CRC checksum generation, and credit flow control. The fourth encoding module performs data encoding. The fourth decoding module performs data decoding. The FC receiver control module implements the acknowledgment mechanism and CRC checksum detection, and works in conjunction with the fourth error detection module. The FC header alignment module performs header alignment. The FC protocol word validity / primitive detection module determines whether the data conforms to the FC protocol requirements; if valid data is detected, it is passed to the FC header alignment module.

[0106] Specifically, the upper-layer protocol first encapsulates the data into a customized AXI-Stream format data frame and delivers it to the network convergence layer. The FC transmitter bus conversion module of the network convergence layer first converts the AXI-Stream data into a data frame format customized for the FC protocol. The FC transmission control module of the data link layer is responsible for link establishment, CRC checksum generation, credit flow control, etc., and then the encoding module completes the data encoding. Finally, it is handed over to the high-speed SerDes of the physical layer for transmission.

[0107] Upon receiving data, the physical layer completes the serial-to-parallel conversion, and the data enters the data link layer. The decoding module of the data link layer decodes the data, which then enters the FC protocol word validity / primitive detection module. This module determines whether the data conforms to the requirements of the FC protocol. If valid data is detected, it is passed to the FC frame header alignment module for frame header alignment, similar in principle to Interlaken's frame header alignment, which will not be elaborated further. The data then enters the FC receiver control module to complete functions such as acknowledgment mechanisms and CRC checksum detection, resulting in a customized FC protocol data frame. Next, bus conversion and error detection are performed synchronously. The FC receiver bus conversion module converts the customized FC data to AXI-Stream format, while the error detection module performs frame length detection and frame end-of-frame detection. Finally, the AXI-Stream data is delivered to the upper-layer application, completing the FC protocol integration process.

[0108] In summary, this application's multi-protocol converged high-performance network device integrates Interlaken and Aurora protocol communication mechanisms, achieving high throughput and low latency inter-chip data transmission while maintaining a lightweight design. Furthermore, the system constructs a unified converged channel for Ethernet and FC networks, balancing the interconnection needs of general-purpose networks with the transmission characteristics of high-performance dedicated networks, thereby significantly improving the device's network adaptability and scalability. Moreover, the design based on the multi-protocol converged framework and error detection mechanism enables the device to achieve efficient and reliable communication between multiple devices in complex heterogeneous computing environments.

[0109] In summary, the high-performance multi-protocol converged network device of this application constructs a unified multi-protocol converged communication architecture by realizing multi-protocol coexistence and data frame fusion at the hardware level. This architecture not only improves the system's interconnection bandwidth and transmission reliability, but also supports flexible access to various network devices and storage systems, possessing excellent scalability and compatibility, and providing an efficient and universal communication foundation for future heterogeneous computing platforms and high-performance data centers.

[0110] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A multi-protocol integrated high performance network device, characterized by, The application layer is configured to perform high-speed data interaction with the network fusion layer through AXI-Stream protocol; the network fusion layer is configured to perform protocol identification and analysis on the input data packet, convert data frames from Interlaken, Aurora, Ethernet and FC protocols into unified AXI-Stream format, and provide error detection flag to the upper layer; The data link layer is configured to generate, encapsulate and encode frame structure according to the standardized data stream output by the network fusion layer according to the frame format requirements of different network protocols; and the physical layer comprises a high-speed SerDes module for realizing serial-parallel conversion.

2. The multi-protocol integrated high-performance network device according to claim 1, characterized in that, when processing Interlaken protocol, the network fusion layer comprises an Interlaken sending end bus conversion module, a burst format generation module, a burst format analysis module, an Interlaken receiving end bus conversion module, an Interlaken frame header alignment module and a first error detection module; the Interlaken sending end bus conversion module is used for converting AXI-Stream format data into Interlaken LBUS format and performing size-end conversion, and generating BCTL flag according to burst transmission optimization algorithm; the burst format generation module is used for encapsulating data into Interlaken Burst format according to BurstMax and BurstShort parameters; the burst format analysis module is used for analyzing received Interlaken Burst format data; the Interlaken receiving end bus conversion module is used for converting Interlaken LBUS format data into AXI-Stream format; and the Interlaken frame header alignment module is used for completing frame header alignment; the first error detection module is used for detecting CRC error, overlong frame, over-short frame and frame end symbol exception, and setting specific error flag.

3. The multi-protocol integrated high-performance network device according to claim 1 or 2, characterized in that, when processing Interlaken protocol, the data link layer comprises a Meta frame generation module, a first encoding module, a first decoding module and a Meta frame analysis module; the Meta frame generation module is used for dividing Interlaken Burst data into 8-byte data blocks, and when there are multiple channels in the physical layer, the data blocks are sequentially distributed to each channel and packaged into Meta frame format; the first encoding module is used for encoding Meta frame to realize direct current balance; the first decoding module is used for decoding received Meta frame; and the Meta frame analysis module is used for analyzing received Meta frame. The Meta frame analysis module is configured to analyze the decoded Meta frame, extract the synchronization word and check word information, and extract valid data to obtain Interlaken Burst format data according to the flags.

4. The multi-protocol converged high-performance network device of claim 1, wherein, when processing the Aurora protocol, the network convergence layer comprises a sending end bit width conversion module, a sending end clock domain conversion module, a data block module, a data block recombination module, a receiving end bit width conversion module, a receiving end clock domain conversion module, and a second error detection module; the sending end bit width conversion module is configured to convert AXI-Stream data of an application layer into AXI-Stream data bit width supported by the Aurora protocol; the sending end clock domain conversion module is configured to convert data from a clock domain of the application layer into a clock domain of the network convergence layer; the data block module is configured to cut a data frame into data blocks of 8 bytes in size, and add a Separator data block after the last data block of each frame, the Separator data block comprises CRC check data and frame end information of a current frame; the data block recombination module is configured to parse data blocks into AXI-Stream format data frames defined by the Aurora according to related information provided by the Separator data block, and generate CRC check data and compare the CRC check data with the CRC data in the Separator data block; the receiving end bit width conversion module is configured to convert data frames of the Aurora protocol into data bit width specified by an upper layer protocol; the receiving end clock domain conversion module is configured to convert data into a clock domain of the upper layer protocol; the second error detection module is configured to detect whether a frame length meets a requirement by counting, perform frame check according to a CRC signal provided by the data recombination module, detect whether a frame end symbol is normal, and set a specific error flag position.

5. The multi-protocol converged high-performance network device of claim 1 or 4, wherein, when processing the Aurora protocol, the data link layer comprises a second encoding module and a second decoding module; the second encoding module is configured to uniformly encode data blocks and Separator blocks; the second decoding module is configured to complete decoding of the data blocks and the Separator blocks according to a protocol.

6. The multi-protocol converged high-performance network device of claim 1, wherein, when processing the Ethernet protocol, the network convergence layer comprises a data buffer module, a read-write control module, an Ethernet sending end bus conversion module, a MAC framing module, an Ethernet frame header alignment module, an Ethernet receiving end bus conversion module, a MAC analysis module, and a third error detection module; the data buffer module is configured to store data transmitted by an upper layer protocol; The read-write control module is used to realize internal continuous transmission of Ethernet frames, and when it is detected that a complete frame of data is stored in the data buffer module, a frame of data is read from the data buffer module and written into the MAC framing module without interruption. The Ethernet sending-end bus conversion module is used to convert the data in the form of internal continuous AXI-Stream into data in the form of Ethernet LBUS. The MAC framing module is used to add corresponding Ethernet frame headers and frame tails to form MAC frames. The Ethernet frame header alignment module is used to complete frame header alignment to obtain Ethernet LBUS format data with aligned frame headers. The Ethernet receiving-end bus conversion module is used to convert Ethernet LBUS format data into AXI-Stream format data; and the MAC analysis module is used to convert MAC frames into Ethernet LBUS format data, while recalculating FCS and comparing it with the received FCS to give the correctness of data frame transmission. The third error detection module is used to complete CRC error detection, frame length detection, and frame end symbol error detection, and set specific error flag positions.

7. The multi-protocol integrated high-performance network device according to claim 1 or 6, characterized in that, when processing the Ethernet protocol, the data link layer comprises a third encoding module and a third decoding module; the third encoding module is used to encode MAC frames; the third decoding module is used to decode received data to obtain the content of MAC frames.

8. The multi-protocol integrated high-performance network device according to claim 1, characterized in that, when processing the FC protocol, the network integration layer comprises an FC sending-end bus conversion module, an FC receiving-end bus conversion module, and a fourth error detection module; the FC sending-end bus conversion module is used to convert AXI-Stream data into FC protocol customized data frame format; the FC receiving-end bus conversion module is used to convert FC customized data into AXI-Stream format; the fourth error detection module is used to complete frame length detection, frame end symbol detection, and CRC check detection in cooperation with the FC receiving-end control module, and set specific error flag positions.

9. The multi-protocol integrated high-performance network device according to claim 1 or 8, characterized in that, when processing the FC protocol, the data link layer comprises an FC sending control module, a fourth encoding module, a fourth decoding module, an FC receiving-end control module, an FC frame header alignment module, and an FC protocol word validity / primitive detection module; the FC sending control module is used to be responsible for link establishment, CRC check code generation, and credit flow control; the fourth encoding module is used to complete data encoding; the fourth decoding module is used to complete data decoding; the FC receiving-end control module is used to complete response mechanism and CRC check detection functions, and works in cooperation with the fourth error detection module; the FC frame header alignment module is used to complete frame header alignment. The FC protocol word validity / primitive detection module is used to determine whether the data conforms to the requirements of the FC protocol. If valid data is detected, the data is passed to the FC frame header alignment module.

10. The high-performance network device with multi-protocol fusion according to claim 1, characterized in that, The AXI-Stream format includes TVALID, TREADY, TKEEP, TLAST, and TUSER signals; The TVALID indicates whether the current data is valid; TREADY is a flag bit from the network fusion layer. If it is 1, it means that data can now be received from the upper layer. The TKEEP indicates which positions of the 512 bits of data are valid, with each bit corresponding to 32 bits of validity. It is used in conjunction with TLAST to indicate which bits are invalid in the last data frame. The TLAST indicates the end-of-frame marker; The TUSER includes TUSER[0] frame start flag, TUSER[1] CRC check error flag, TUSER[2] long frame error flag, TUSER[3] short frame flag, TUSER[4] frame end character abnormal flag, and TUSER[7:5] reserved bits; The network convergence layer is configured to automatically set the corresponding error flag and report it to the application layer when a corresponding error is detected, so that the application layer can execute error correction or retransmission strategies.

Images