An ASIC chip with an energy response self-calibration module

By integrating an energy response self-calibration module into the ASIC chip, the problem of inconsistent energy responses among different channels of the ASIC chip was solved, achieving high-precision energy detection and improved material utilization, while simplifying the calibration process.

CN122093687APending Publication Date: 2026-05-26ZHEJIANG PIONEER RUITAI MEDICAL TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-01-26
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

The existing ASIC chips have differences in energy response between pixel channels during the manufacturing process, resulting in inconsistent energy detection accuracy. Furthermore, existing calibration methods cannot distinguish between ASIC and crystal manufacturing process issues, leading to material waste and communication complexity.

Method used

An energy response self-calibration module is integrated into the ASIC chip, including a test pulse generator, a reference voltage control submodule, and a calibration logic control submodule. The self-calibration algorithm solves the polynomial coefficients and adjusts the reference voltage of each pixel channel to achieve a consistent energy response.

Benefits of technology

It achieves consistent discrimination thresholds for the same energy pulse across all channels of the ASIC, improves energy detection accuracy, avoids material waste, simplifies the calibration process, and can identify defective crystals.

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Abstract

This invention discloses an ASIC chip with an energy response self-calibration module, comprising a multi-pixel channel array containing N independent pixel channels. Each pixel channel includes a charge-sensitive amplifier module, a shaping circuit, a pulse energy discrimination module, and a counting module. The pulse energy discrimination module has a built-in comparator. The chip also includes an energy response self-calibration module, comprising a test pulse generator, a reference voltage control submodule, and a calibration logic control submodule. By controlling the pulse height and the magnitude of the reference voltage Vref, the S-curves of each pixel channel corresponding to different test pulse heights are obtained. Based on a preset calibration algorithm, the polynomial coefficients of the reference voltage and the calibrated DAC value for each pixel channel are calculated and stored. This invention enables consistent energy response across all pixel channels of the ASIC, and allows the calibration coefficients to be read after self-calibration to determine the differences between the ASIC channels.
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