An integrated circuit chip signal transmission correction system and method

Abstract

The application provides a kind of integrated circuit chip signal transmission correction system and method, related to the technical field of application-specific integrated circuit chip, by determining the clock phase difference between adjacent transmission channels;The monitoring circuit of each receiving end records the pulse string interference intensity from the active transmission channel, and then constructs the pulse string interference matrix of application-specific integrated circuit chip;When it is identified that more than a preset number of transmission channels in adjacent transmission channels occur reverse jump at the same time, pulse edge suppression is carried out on the transmission channel that occurs reverse jump, and the jitter suppression amount of the pulse edge of the reverse jump transmission channel is obtained;Insert reference pulse in the idle clock cycle of signal transmission stage, and detect the waveform distortion degree of reference pulse;According to the jitter suppression amount and the waveform distortion degree, the timing parameters of the pulse edge of the reverse jump transmission channel are timing calibrated.The application can realize the suppression of multi-channel pulse crosstalk in the application-specific integrated circuit chip, so as to improve the integrity of chip signal transmission.

Description

Technical Field

[0001] This application relates to the field of application-specific integrated circuit (ASIC) chip technology, and more specifically, to an integrated circuit chip signal transmission correction system and method. Background Technology

[0002] Application-specific integrated circuit (ASIC) technology is the cornerstone of modern electronic information systems. Through customized design for specific applications, it achieves a perfect combination of high performance, high energy efficiency, and high integration. It plays a core role in key areas such as data centers, high-speed communications, and artificial intelligence computing. The ability of its massive internal transmission channels to process data in parallel directly determines the throughput and response speed of the entire system. Therefore, ensuring the accuracy and integrity of high-speed signal transmission within ASICs is the fundamental prerequisite for maximizing the performance of ASICs and ensuring the stable and reliable operation of the system.

[0003] However, in existing technologies, application-specific integrated circuit (ASIC) chips integrate a large number of high-density parallel transmission channels. The extremely small physical spacing between channels can easily cause electromagnetic and capacitive coupling, leading to pulse crosstalk problems. Traditional signal correction schemes mostly focus on timing compensation or waveform shaping of a single channel, ignoring the coupling effect of crosstalk between multiple channels. Moreover, most of them rely on external equipment for offline calibration, making it impossible to achieve real-time adjustment during the dynamic operation of the chip. At the same time, existing methods lack quantitative modeling of crosstalk intensity, making it difficult to formulate accurate correction strategies for different operating conditions. This results in increased signal edge jitter and higher bit error rate when the chip is running under high load, severely restricting its application in high-speed transmission scenarios. Therefore, how to suppress multi-channel pulse crosstalk inside ASIC chips and thus improve the integrity of chip signal transmission has become a challenge for the industry. Summary of the Invention

[0004] This application provides an integrated circuit chip signal transmission correction system and method, which can suppress multi-channel pulse crosstalk inside the dedicated integrated circuit chip, thereby improving the integrity of chip signal transmission.

[0005] In a first aspect, this application provides a signal transmission correction method for an integrated circuit chip, the chip signal transmission correction method comprising the following steps: The reference clock signal is received by the receiver of each transmission channel within the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels; During the periodic idle period, each transmission channel sends a transition test signal in sequence, while the other transmission channels remain static. The monitoring circuits at each receiver record the pulse crosstalk intensity from the active transmission channels, and construct the pulse crosstalk matrix of the application-specific integrated circuit chip based on all the pulse crosstalk intensities and all the clock phase differences. During the signal transmission stage, when it is detected that more than a preset number of adjacent transmission channels simultaneously undergo reverse transitions, pulse edge suppression is performed on the transmission channels undergoing reverse transitions according to the pulse crosstalk matrix to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. A reference pulse is inserted during the idle clock cycle of the signal transmission phase, and the waveform distortion of the reference pulse is detected by the receiver of the reverse switching transmission channel. Timing calibration is performed on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

[0006] In this embodiment, determining the clock phase difference between adjacent transmission channels specifically includes: The local sampling clock for each transmission channel is recovered from the received reference clock signal; The phase offset of each transmission channel is obtained by comparing the local sampling clock of each transmission channel with the global reference clock. The clock phase difference between adjacent transmission channels is determined based on the phase offset of each transmission channel.

[0007] In this embodiment, during periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuits at each receiver record the pulse crosstalk intensity from the active transmission channels, specifically including: During periodic idle periods, each transmission channel sends a transition test signal in sequence; When the test sequence controller designates a certain transmission channel as an active channel and sends a transition test signal, it controls the transmitters of all inactive transmission channels to maintain static output. The monitoring circuit at the receiving end of each inactive transmission channel acquires the voltage signal at the input end of the active transmission channel; Extract the peak value of crosstalk spikes generated by the active transmission channel from the voltage signal at the input of the active transmission channel; The pulse crosstalk intensity of the active transmission channel is determined based on the peak value of the crosstalk spikes generated by the active transmission channel and the static reference level. Then, the monitoring circuits of each receiver record the pulse crosstalk intensity from the active transmission channel.

[0008] In this embodiment, constructing the pulse crosstalk matrix of the application-specific integrated circuit (ASIC) chip based on all pulse crosstalk intensities and all clock phase differences specifically includes: The central processing unit acquires the pulse crosstalk intensity recorded in all test rounds, where each round corresponds to the pulse crosstalk of an active transmission channel to all other transmission channels; For each pair of transmission channels, each pair specifically includes a victim transmission channel and an attack transmission channel; Based on the clock phase difference between the victim transmission channel and the attack transmission channel in each pair of transmission channels, the pulse crosstalk intensity recorded on the victim transmission channel and measured from the attack transmission channel is calibrated in the time domain to obtain the crosstalk coupling coefficient corresponding to each pair of transmission channels. The pulse crosstalk matrix of the application-specific integrated circuit chip is constructed based on the crosstalk coupling coefficient corresponding to each pair of transmission channels.

[0009] In this embodiment, pulse edge suppression is performed on the transmission channel experiencing reverse transitions based on the pulse crosstalk matrix. The specific jitter suppression amount for the pulse edge of the reverse transition transmission channel includes: The combination of transmission channels that simultaneously undergo reverse transitions and the corresponding clock phase difference are identified. The basis for determining the reverse transition is that the polarity of the transition edges of adjacent transmission channels is opposite. Based on the identified transmission channel combination number and clock phase difference, the pulse crosstalk matrix is ​​queried to extract the crosstalk coupling coefficient corresponding to the transmission channel with reverse transition; The edge suppression parameters of the reverse transition transmission channel are determined based on the crosstalk coupling coefficient corresponding to the reverse transition transmission channel. The delay of the signal edge of the reverse transition transmission channel is adjusted by using the edge suppression parameter of the reverse transition transmission channel; The jitter suppression amount of the reverse transition transmission channel pulse edge is determined based on the jitter value of the reverse transition transmission channel pulse edge after delay adjustment.

[0010] In this embodiment, detecting the waveform distortion of the reference pulse at the receiving end of the reverse-switching transmission channel specifically includes: The reference pulse is sampled at equal intervals in the time domain by the sampling circuit at the receiving end of the reverse switching channel to obtain the waveform data of the reference pulse; The amplitude deviation rate, edge slope deviation rate, and pulse width deviation rate are extracted from the waveform data of the reference pulse. The waveform distortion of the reference pulse is determined based on the amplitude deviation rate, the edge slope deviation rate, and the pulse width deviation rate.

[0011] In this embodiment, timing calibration of the timing parameters of the reverse transition transmission channel pulse edge based on the jitter suppression amount and the waveform distortion specifically includes: The timing margin of the reverse transition transmission channel pulse edge is determined by the jitter suppression amount and the waveform distortion. The timing margin is used to adjust the transmission delay time of the pulse edge of the reverse transition transmission channel and the sampling window offset of the reverse transition transmission channel receiver. The timing convergence verification results of the adjusted transmission delay time and sampling window offset are obtained by performing timing convergence verification on the pulse edge of the reverse transition transmission channel. The calibration ends when the timing convergence verification result is satisfactory. When the timing convergence verification result is unqualified, the transmission delay time and the adjustment step size of the sampling window offset are adjusted according to the deviation information of the timing convergence verification, and the timing convergence verification is performed again. The above adjustment and verification process is repeated until the verification result is qualified.

[0012] In this embodiment, the pulse crosstalk matrix represents a matrix that reflects the pulse crosstalk coupling relationship between transmission channels within an application-specific integrated circuit chip.

[0013] In this embodiment, the jitter suppression amount represents the quantization value of suppressing pulse crosstalk jitter caused by the reverse transition of the transmission channel due to the reverse transition of the adjacent transmission channel.

[0014] Secondly, this application provides an integrated circuit chip signal transmission correction system for performing an integrated circuit chip signal transmission correction method, the chip signal transmission correction system comprising: The clock signal receiving module is used to receive a reference clock signal through the receiving end of each transmission channel in the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels; The pulse crosstalk analysis module is used to send a transition test signal to each transmission channel in turn during periodic idle periods, while the other transmission channels remain static. The monitoring circuits at each receiving end record the pulse crosstalk intensity from the active transmission channel and construct the pulse crosstalk matrix of the dedicated integrated circuit chip based on all pulse crosstalk intensities and all clock phase differences. The pulse edge suppression module is used to suppress the pulse edges of the transmission channels that have reverse transitions simultaneously when more than a preset number of adjacent transmission channels are detected to be undergoing reverse transitions during the signal transmission stage, based on the pulse crosstalk matrix, to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. The waveform distortion detection module is used to insert a reference pulse during the idle clock cycle of the signal transmission phase and detect the waveform distortion of the reference pulse through the receiving end of the reverse switching transmission channel. The timing calibration module is used to perform timing calibration on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: The reference clock signal is received by the receiver of each transmission channel within the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels. During periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuit of each receiver records the pulse crosstalk intensity from the active transmission channels, and constructs a pulse crosstalk matrix for the dedicated integrated circuit chip based on all pulse crosstalk intensities and all clock phase differences. During the signal transmission phase, when more than a preset number of adjacent transmission channels are detected to simultaneously undergo reverse transitions, pulse edge suppression is performed on the transmission channels undergoing reverse transitions based on the pulse crosstalk matrix to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. A reference pulse is inserted during the idle clock cycle of the signal transmission phase, and the waveform distortion of the reference pulse is detected by the receiver of the reverse transition transmission channel. Timing calibration is performed on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

[0016] Therefore, in this application, timing parameters of the pulse edge of the reverse transition transmission channel can be calibrated based on the jitter suppression amount and the waveform distortion. Firstly, by receiving reference clock signals at each transmission channel receiver and determining the clock phase difference between adjacent channels, the influence of phase relationship on crosstalk coupling effect is accurately captured, breaking the limitations of traditional schemes that ignore phase correlation and focus only on single-channel optimization. Secondly, during periodic idle periods, crosstalk intensity is recorded by sending test signals through a single channel while the remaining channels are static. A pulse crosstalk matrix is ​​constructed based on the clock phase difference, achieving quantitative modeling of crosstalk intensity between multiple channels. This solves the problem of existing technologies lacking crosstalk quantitative analysis and difficulty in formulating precise correction strategies, upgrading the correction action from "blind compensation" to "quantitative driving." Furthermore, during the signal transmission stage, high crosstalk conditions with simultaneous reverse transitions of adjacent multiple channels are specifically identified, based on the crosstalk matrix... The system employs pulse edge suppression to directly address the core scenario of crosstalk caused by multi-channel coupling, effectively reducing signal edge jitter caused by reverse transitions and overcoming the bottleneck of traditional single-channel timing compensation being unable to cope with multi-channel coupling effects. Furthermore, by inserting a reference pulse during idle clock cycles and detecting waveform distortion, real-time distortion monitoring of the ASIC chip during operation is achieved, eliminating the drawbacks of traditional offline calibration relying on external equipment and being disconnected from actual operating conditions, and providing real-time feedback for dynamic adjustment and correction. Finally, timing parameters are calibrated by combining jitter suppression and waveform distortion, forming a closed-loop mechanism of "quantitative modeling - risk suppression - real-time feedback - precise calibration," effectively alleviating the problem of increased signal edge jitter and bit error rate under high load, significantly improving the accuracy and integrity of high-speed signal transmission within the ASIC chip, and helping it to fully realize its extreme performance in high-end scenarios such as data centers and high-speed communications.

[0017] In summary, the technical solution adopted in this application can suppress multi-channel pulse crosstalk within the application-specific integrated circuit chip, thereby improving the integrity of chip signal transmission. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this embodiment of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an exemplary flowchart of a signal transmission correction method for an integrated circuit chip according to the present application; Figure 2 This is a flowchart illustrating the process for determining the jitter suppression amount provided in this application; Figure 3 This is a flowchart illustrating the timing calibration process provided in this application; Figure 4 This is a module structure diagram of an integrated circuit chip signal transmission correction system provided in this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] This application provides an integrated circuit chip signal transmission correction system and method. The core of the system is to receive a reference clock signal at the receiving end of each transmission channel within the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels. During periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuit at each receiving end records the pulse crosstalk intensity from the active transmission channels. Based on all pulse crosstalk intensities and all clock phase differences, a pulse crosstalk matrix for the dedicated integrated circuit chip is constructed. During the signal transmission phase, when more than a preset number of adjacent transmission channels are simultaneously detected to have reverse transitions, pulse edge suppression is performed on the transmission channels experiencing reverse transitions according to the pulse crosstalk matrix, obtaining the jitter suppression amount of the reverse transition transmission channel's pulse edge. A reference pulse is inserted during the idle clock cycle of the signal transmission phase, and the waveform distortion of the reference pulse is detected by the receiving end of the reverse transition transmission channel. Timing calibration is performed on the timing parameters of the reverse transition transmission channel's pulse edge based on the jitter suppression amount and the waveform distortion.

[0022] Example 1: To better understand the above technical solution, the following will provide a detailed description of the technical solution in conjunction with the accompanying drawings and specific implementation methods. (Refer to...) Figure 1 As shown, this figure is an exemplary flowchart of an integrated circuit chip signal transmission correction method according to this embodiment of the present application. The chip signal transmission correction method includes the following steps: In step S1, a reference clock signal is received by the receiver of each transmission channel within the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels.

[0023] In practice, the receiver of each transmission channel within the application-specific integrated circuit (ASIC) chip is switched to clock reception mode, and the reference clock signal distributed evenly by the global clock tree of the ASIC chip is received through the receiver of each transmission channel within the ASIC chip.

[0024] It should be noted that the reference clock signal mentioned in this application refers to the reference clock signal that is distributed to each transmission channel through the global clock tree of the dedicated integrated circuit chip to ensure synchronization from the same source.

[0025] In this embodiment, the clock phase difference between adjacent transmission channels can be determined by the following steps: The local sampling clock for each transmission channel is recovered from the received reference clock signal; The phase offset of each transmission channel is obtained by comparing the local sampling clock of each transmission channel with the global reference clock. The clock phase difference between adjacent transmission channels is determined based on the phase offset of each transmission channel.

[0026] It should be noted that the local sampling clock mentioned in this application refers to the clock signal used for local signal sampling, whose frequency is consistent with the reference clock signal and whose phase is stable; the global reference clock refers to the core reference clock of the application-specific integrated circuit chip clock system; the phase offset refers to the synchronization deviation between the transmission channel clock and the reference clock; and the clock phase difference between adjacent transmission channels refers to the clock synchronization difference between adjacent transmission channels.

[0027] In specific implementation, firstly, a phase-locked loop (PLL) module is used to locally sample and recover the reference clock signal acquired at the receiver of each transmission channel. The output frequency of the voltage-controlled oscillator inside the PLL is adjusted to ensure that the frequency of the output clock is consistent with that of the reference clock signal. At the same time, the phase detector inside the PLL calibrates the phase of the output clock in real time until the phase deviation between the output clock and the reference clock signal stabilizes within a preset range (e.g., ≤1ps). The stabilized PLL output clock is then used as the local sampling clock for the corresponding transmission channel. Secondly, the phase detector performs real-time phase comparison between the local sampling clock of each transmission channel and the global reference clock, synchronously capturing the timing difference between their rising edges. The timing difference is converted into a corresponding phase difference value by the time-to-digital converter inside the chip, and this phase difference value is used as the phase offset of the corresponding transmission channel. Finally, all transmission channels are traversed sequentially according to their physical arrangement. The phase offset between two adjacent transmission channels is taken, and the absolute value of the difference between the phase offset of the previous transmission channel and the phase offset of the next transmission channel is subtracted from the phase offset of the previous transmission channel. This absolute value is used as the clock phase difference between adjacent transmission channels, thus completing the acquisition of the clock phase difference between adjacent transmission channels.

[0028] In step S2, during periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuits at each receiver record the pulse crosstalk intensity from the active transmission channels, and construct the pulse crosstalk matrix of the dedicated integrated circuit chip based on all pulse crosstalk intensities and all clock phase differences.

[0029] In this embodiment, during periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuit at each receiver records the pulse crosstalk intensity from the active transmission channel, which can be achieved through the following steps: During periodic idle periods, each transmission channel sends a transition test signal in sequence; When the test sequence controller designates a certain transmission channel as an active channel and sends a transition test signal, it controls the transmitters of all inactive transmission channels to maintain static output. The monitoring circuit at the receiving end of each inactive transmission channel acquires the voltage signal at the input end of the active transmission channel; Extract the peak value of crosstalk spikes generated by the active transmission channel from the voltage signal at the input of the active transmission channel; The pulse crosstalk intensity of the active transmission channel is determined based on the peak value of the crosstalk spikes generated by the active transmission channel and the static reference level. Then, the monitoring circuits of each receiver record the pulse crosstalk intensity from the active transmission channel.

[0030] It should be noted that, in this application, the periodic idle time period refers to the gap period during which the application-specific integrated circuit chip transmits service data; the transition test signal refers to a standard pulse sequence of alternating high and low levels used to induce crosstalk; the active transmission channel refers to the transmission channel selected by the test sequence controller to send the transition test signal; the inactive transmission channel refers to the transmission channel that is not selected and maintains static output; the crosstalk peak value refers to the maximum voltage fluctuation generated by the signal transition of the active transmission channel; the static reference level refers to the stable output level of the inactive transmission channel when there is no crosstalk; and the pulse crosstalk intensity refers to the degree of fluctuation of the crosstalk peak value relative to the static reference level.

[0031] In specific implementation, firstly, the chip link negotiation module identifies and locks periodic idle periods. The test sequence controller triggers each transmission channel sequentially according to its physical number, causing it to send alternating high and low level transition test signals. The transition frequency of the signals is consistent with the chip's operating frequency, and this alternating high and low level pulse sequence is used as the transition test signal. Secondly, when the test sequence controller designates a transmission channel as an active transmission channel via on-chip bus instructions, it synchronously sends static hold instructions to the transmitters of all other inactive transmission channels, controlling the transmitters of the inactive transmission channels to output a fixed high or low level, and this fixed level is used as the static output. Next, the high-speed voltage monitoring circuit integrated into the receiver of each inactive transmission channel monitors the voltage of the receiver of that inactive transmission channel. The voltage signal is sampled at equal intervals at a high speed, with a sampling rate no less than 10 times the chip's operating frequency. This captures the voltage fluctuations at the receiver of the inactive channel when the active channel signal transitions. The sampled voltage fluctuation signal is used as the voltage signal associated with the input of the active channel. Then, a peak detection algorithm is used to traverse the sampled voltage signals and filter out the maximum voltage value that deviates from the static reference level. This maximum value is used as the peak value of the crosstalk spike generated by the active transmission channel. Finally, the ratio of the peak value of the crosstalk spike to the static reference level is calculated. This ratio is used as the pulse crosstalk intensity of the active transmission channel. The monitoring circuit at the receiver of each inactive transmission channel associates and stores the corresponding active transmission channel number, the peak value of the crosstalk spike, and the pulse crosstalk intensity, thus completing the recording of the pulse crosstalk intensity from the active transmission channel.

[0032] In this embodiment, the pulse crosstalk matrix of the application-specific integrated circuit (ASIC) chip can be constructed based on all pulse crosstalk intensities and all clock phase differences using the following steps: The central processing unit acquires the pulse crosstalk intensity recorded in all test rounds, where each round corresponds to the pulse crosstalk of an active transmission channel to all other transmission channels; For each pair of transmission channels, each pair specifically includes a victim transmission channel and an attack transmission channel; Based on the clock phase difference between the victim transmission channel and the attack transmission channel in each pair of transmission channels, the pulse crosstalk intensity recorded on the victim transmission channel and measured from the attack transmission channel is calibrated in the time domain to obtain the crosstalk coupling coefficient corresponding to each pair of transmission channels. The pulse crosstalk matrix of the application-specific integrated circuit chip is constructed based on the crosstalk coupling coefficient corresponding to each pair of transmission channels.

[0033] It should be noted that, in this application, the victim transmission channel refers to an inactive transmission channel whose recording pulse crosstalk intensity is affected by crosstalk; the attacking transmission channel refers to a transmission channel that generates crosstalk as an active channel; the time-domain calibration refers to the process of correcting the timing deviation in crosstalk intensity measurement caused by clock phase difference; the crosstalk coupling coefficient refers to the quantified value of the crosstalk influence of the attacking transmission channel on the victim transmission channel after time-domain calibration; and the pulse crosstalk matrix refers to a matrix reflecting the pulse crosstalk coupling relationship between transmission channels within an application-specific integrated circuit chip.

[0034] In specific implementation, firstly, the central processing unit (CPU) reads all test round data stored in the on-chip SRAM via the on-chip AXI4 bus, categorizes and organizes it according to the active transmission channel number, and extracts the pulse crosstalk intensity, corresponding transmission channel number, and test timing information of the active transmission channel for all other transmission channels in each round. The categorized crosstalk data is then correlated with the previously acquired phase offset data of each transmission channel to form a complete crosstalk-phase dataset. Secondly, all transmission channels are traversed according to the combination of "attack channel - victim channel," clarifying the role of each pair of transmission channels; that is, when an active transmission channel acts as an attack channel, all other transmission channels are corresponding victim channels. Next, a phase offset compensation algorithm is used for time-domain calibration. For each pair of transmission channels, the algorithm is called... The clock phase difference between adjacent transmission channels is calculated in the early stage. Based on the timing offset corresponding to the clock phase difference, the sampling timing of the crosstalk intensity of the victim transmission channel is adjusted so that the sampling time of the crosstalk peak is aligned with the transition time of the attacking transmission channel, thus eliminating the influence of timing deviation on the crosstalk intensity. The calibrated and stable crosstalk quantization value is used as the crosstalk coupling coefficient corresponding to the pair of transmission channels. Finally, an M×M two-dimensional matrix is ​​constructed (M is the total number of transmission channels). The matrix row index corresponds to the attacking transmission channel number and the column index corresponds to the victim transmission channel number. The crosstalk coupling coefficient of each pair of transmission channels is filled into the corresponding matrix element position. At the same time, the transmission channel number mapping relationship and calibration timestamp of the matrix are marked. The constructed two-dimensional matrix is ​​stored in the on-chip cache and used as the pulse crosstalk matrix of the application-specific integrated circuit chip.

[0035] In step S3, during the signal transmission stage, when it is detected that more than a preset number of adjacent transmission channels simultaneously undergo reverse transitions, pulse edge suppression is performed on the transmission channels undergoing reverse transitions according to the pulse crosstalk matrix to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel.

[0036] It should be noted that the signal transmission phase described in this application refers to the alternation of the core period and periodic idle period for the transmission of service data by the application-specific integrated circuit chip; the reverse transition refers to the opposite polarity of the signal transition edges of adjacent transmission channels (i.e., one transmission channel transitions from low level to high level, and the adjacent transmission channel transitions from high level to low level); the preset number refers to the minimum number of reverse transition channels for the preset trigger pulse edge suppression (which can be configured according to the transmission channel density, for example, 2 or more), and is stored in the on-chip configuration register.

[0037] Preferably, in this embodiment, pulse edge suppression is performed on the transmission channel experiencing reverse transitions based on the pulse crosstalk matrix to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel, with reference to... Figure 2As shown in the figure, this is a schematic flowchart of determining the jitter suppression amount in some embodiments of this application. In this embodiment, the jitter suppression amount can be determined by the following steps: In step S31, the combination of transmission channels that simultaneously undergo reverse transitions and the corresponding clock phase difference are identified. The basis for determining the reverse transition is that the polarity of the transition edges of adjacent transmission channels is opposite. In step S32, the pulse crosstalk matrix is ​​queried based on the identified transmission channel combination number and clock phase difference to extract the crosstalk coupling coefficient corresponding to the transmission channel with reverse transition. In step S33, the edge suppression parameter of the reverse transition transmission channel is determined according to the crosstalk coupling coefficient corresponding to the reverse transition transmission channel. In step S34, the signal edge of the reverse transition transmission channel is delayed and adjusted by the edge suppression parameter of the reverse transition transmission channel; In step S35, the jitter suppression amount of the reverse transition transmission channel pulse edge is determined based on the jitter value of the reverse transition transmission channel pulse edge after delay adjustment.

[0038] It should be noted that the edge suppression parameter mentioned in this application represents a quantization value used to adjust the signal edge delay of the reverse transition channel, which is positively correlated with the crosstalk coupling coefficient; the signal edge delay adjustment represents changing the transmission delay of the rising / falling edge of the signal by adjusting the output driving capability of the transmission channel, thereby offsetting the edge jitter caused by crosstalk; the jitter value represents the degree of deviation between the actual transition time of the signal edge and the ideal transition time; the jitter suppression amount represents the quantization value for suppressing the pulse crosstalk jitter caused by the reverse transition of adjacent transmission channels in the reverse transition transmission channel.

[0039] In specific implementation, firstly, the signal transition polarity and transition time of each transmission channel are collected by the transition edge detection circuit at the transmitting end of each transmission channel. A transition polarity comparison algorithm is used to traverse the transition data of adjacent transmission channels, filtering out adjacent transmission channels with opposite transition edge polarities and transition time deviations less than a preset threshold. The number combination of this type of transmission channel is used as a reverse transition transmission channel combination. Simultaneously, the clock phase difference corresponding to this transmission channel combination, stored previously, is retrieved, and the transmission channel combination number is associated with and stored with the corresponding clock phase difference. Secondly, the central processing unit queries the pulse crosstalk matrix stored in the on-chip cache according to the index mapping relationship of "attack transmission channel number - victim transmission channel number" to obtain the crosstalk coupling coefficient corresponding to the reverse transition transmission channel. Next, the crosstalk coupling coefficient - edge suppression parameter hierarchical mapping table pre-stored in the on-chip configuration register is retrieved. This mapping table is hierarchically classified according to crosstalk coupling... The coefficients are divided into multiple intervals, each corresponding to a fixed edge suppression parameter value. An interval matching algorithm is used to match the extracted crosstalk coupling coefficients to the corresponding intervals, and the value corresponding to that interval is used as the edge suppression parameter for the reverse-jump transmission channel. Then, the determined edge suppression parameter is input to the output drive control module of the reverse-jump transmission channel. This module adjusts the signal output delay by changing the capacitor load level of the drive circuit. For channels with rising edge reverse jumps, the rising edge delay is increased; for channels with falling edge reverse jumps, the falling edge delay is increased. The adjusted signal edge transmission delay is used as the delay adjustment result. Finally, through the jitter detection circuit at the transmission channel receiver, a sliding window jitter detection algorithm is used to collect the pulse edge jitter values ​​before and after delay adjustment, respectively. The difference between the jitter value before and after adjustment is calculated, and this difference is used as the jitter suppression amount for the pulse edge of the reverse-jump transmission channel.

[0040] In step S4, a reference pulse is inserted during the idle clock cycle of the signal transmission phase, and the waveform distortion of the reference pulse is detected by the receiving end of the reverse switching transmission channel.

[0041] It should be noted that the idle clock cycle in the signal transmission stage described in this application refers to a single or multiple consecutive clock cycles during the transmission of service data by the application-specific integrated circuit chip without effective data payload transmission, which is marked in real time by the link status detector; the reference pulse refers to a standard rectangular pulse with preset fixed parameters, the amplitude, pulse width, and rise / fall slope of which are all known calibration values.

[0042] In specific implementation, inserting a reference pulse during the idle clock cycle of the signal transmission phase can be achieved in the following way: First, the valid flag bit of the data stream during the signal transmission phase is monitored in real time by the chip link status detector. When the flag bit is detected to be invalid, the current clock cycle is determined to be an idle clock cycle, and the start and end times of the idle clock cycle and the corresponding transmission channel number are marked synchronously. The marked time period is used as the target time period for inserting the reference pulse. Second, the reference pulse standard parameters pre-stored in the on-chip configuration register are retrieved. These parameters include a pulse frequency consistent with the chip's operating clock frequency, a pulse amplitude matching the channel's rated output amplitude, a standard pulse width with a duty cycle of 50%, and a preset ideal rise / fall slope. The standard rectangular pulse generated according to these parameters is used as the reference pulse. Next, the pulse insertion control module is started. According to the previously marked reverse transition transmission channel number, the reference pulse is accurately inserted into the target idle clock cycle of the corresponding channel. During the insertion process, the edge of the reference pulse is kept synchronously aligned with the clock edge of the idle clock cycle. Finally, the insertion time, channel number, and standard parameter information of the reference pulse are recorded through the synchronization register.

[0043] In this embodiment, the waveform distortion of the reference pulse can be detected by the receiving end of the reverse switching transmission channel using the following steps: The reference pulse is sampled at equal intervals in the time domain by the sampling circuit at the receiving end of the reverse switching channel to obtain the waveform data of the reference pulse; The amplitude deviation rate, edge slope deviation rate, and pulse width deviation rate are extracted from the waveform data of the reference pulse. The waveform distortion of the reference pulse is determined based on the amplitude deviation rate, the edge slope deviation rate, and the pulse width deviation rate.

[0044] It should be noted that the waveform distortion described in this application refers to the degree of waveform distortion of the reference pulse after transmission.

[0045] In specific implementation, firstly, the high-speed analog-to-digital conversion sampling circuit at the receiving end of the reverse-switching transmission channel is activated. The sampling rate of the sampling circuit is set to 20 times the chip's operating frequency, and the sampling interval is precisely controlled by an on-chip timer. The received reference pulse is sampled at equal intervals in the time domain, and the associated dataset of the sampled voltage values ​​and corresponding sampling times is used as the waveform data of the reference pulse. Secondly, the reference pulse standard parameters pre-stored in the on-chip configuration register are retrieved. A feature extraction algorithm is used to traverse the waveform data, selecting the maximum voltage value in the waveform data as the measured amplitude. The difference between the measured amplitude and the standard amplitude is calculated, and the ratio of this ratio to the standard amplitude is used as the amplitude deviation rate. Then, the voltage change intervals at the rising and falling edges of the waveform data are selected, and the calculation is performed. The voltage change per unit time is used as the measured edge slope. The difference between the measured edge slope and the standard edge slope is calculated, and the ratio of the difference to the standard edge slope is used as the edge slope deviation rate. At the same time, the number of sampling points from the rising edge reaching the threshold voltage to the falling edge falling below the threshold voltage of the reference pulse is counted. Combined with the sampling interval, the measured pulse width is calculated. The difference between the measured pulse width and the standard pulse width is calculated, and the ratio of the difference to the standard pulse width is used as the pulse width deviation rate. Finally, a pre-stored deviation rate weight allocation table is retrieved. The weight values ​​of amplitude deviation rate, edge slope deviation rate, and pulse width deviation rate in this table are stored after calibration. A weighted summation algorithm is used to multiply the three deviation rates by their corresponding weight values ​​and then sum them. The summation result is used as the waveform distortion of the reference pulse.

[0046] In step S5, timing parameters of the reverse transition transmission channel pulse edge are calibrated according to the jitter suppression amount and the waveform distortion.

[0047] Preferably, in this embodiment, timing calibration is performed on the timing parameters of the reverse transition transmission channel pulse edge based on the jitter suppression amount and the waveform distortion, with reference to... Figure 3 As shown in the figure, this is a schematic flowchart of timing calibration in some embodiments of this application. Timing calibration in this embodiment can be achieved by the following steps: In step S51, the timing margin of the reverse transition transmission channel pulse edge is determined by the jitter suppression amount and the waveform distortion. In step S52, the transmission delay time of the pulse edge of the reverse transition transmission channel and the sampling window offset of the receiving end of the reverse transition transmission channel are adjusted by the timing margin. In step S53, the timing convergence verification of the adjusted transmission delay time and sampling window offset is performed to obtain the timing convergence verification result of the pulse edge of the reverse transition transmission channel. In step S54, when the timing convergence verification result is qualified, the calibration ends; In step S55, when the timing convergence verification result is unqualified, the adjustment step size of the transmission delay time and sampling window offset is adjusted according to the deviation information of the timing convergence verification, and the timing convergence verification is performed again. The above adjustment and verification process is repeated until the verification result is qualified.

[0048] It should be noted that, in this application, the timing margin refers to the timing adjustment margin that the pulse edge of the reverse transition transmission channel still has after jitter suppression and waveform distortion compensation; the transmission delay time refers to the delay adjustment value of the output pulse edge of the transmitter of the reverse transition transmission channel; the sampling window offset refers to the start time offset adjustment value of the sampling window of the receiver of the reverse transition transmission channel; and the timing convergence check refers to the detection operation that verifies whether the adjusted transmission delay time and the sampling window offset match the channel timing requirements.

[0049] In specific implementation, firstly, the inherent initial jitter value of the reverse transition transmission channel stored on-chip is retrieved. The jitter suppression amount is subtracted from the initial jitter value, and the resulting value is used as the residual jitter value after jitter suppression. Then, the on-chip digital-to-analog converter module and the controllable delay line linkage circuit are activated. The on-chip digital-to-analog converter directly converts the waveform distortion digital parameters into a linear analog control voltage. The parameter value is positively correlated with the output voltage. This voltage directly acts on the controllable delay line composed of CMOS delay units. The output delay of the delay line changes linearly with the control voltage. The actual delay value output by the controllable delay line at this time is used as the timing offset loss value corresponding to the waveform distortion. At the same time, the chip's preset reference timing is retrieved. The half-width value of the window (determined by the chip's operating frequency, for example, 1GHz corresponds to a half-width value of 500ps, which is half of the effective range of the sampling window) is first obtained by subtracting the residual jitter value from the reference timing window half-width value. Then, the timing offset loss value is subtracted from the first intermediate value. The final value is used as the timing margin for the pulse edge of the reverse transition transmission channel (if the final value is negative, the minimum value of 0 is taken, indicating that there is no available timing margin). Next, the obtained timing margin is allocated in a 1:1 ratio to the transmit delay adjustment component and the sampling window offset adjustment component. The transmit delay adjustment component is input to the delay control circuit at the transmitting end of the transmission channel, and the delay unit within the circuit is adjusted. The output delay of the pulse edge is changed, and the adjusted output delay is used as the transmission delay time of the pulse edge of the reverse transition transmission channel. Simultaneously, the sampling window offset adjustment component is input to the sampling window control module of the receiving end. The start time of the sampling window is adjusted through a shift register, and the adjusted start time offset value is used as the sampling window offset of the receiving end of the reverse transition transmission channel. Next, an edge sampling deviation detection algorithm is used to capture the difference between the actual transition time of the adjusted pulse edge and the center time of the sampling window. This difference is compared with a preset qualified threshold (e.g., ≤1ps), and the comparison result is used as the timing convergence verification result of the pulse edge of the reverse transition transmission channel. If the timing convergence verification result shows a difference less than or equal to the preset qualified threshold, the verification result is deemed qualified, and the timing calibration process ends directly. Finally, if the timing convergence verification result shows a difference greater than the preset qualified threshold, the verification result is deemed unqualified. The difference is extracted as the deviation information for timing convergence verification. The original adjustment step size is multiplied by the ratio coefficient of the deviation information to the qualified threshold (e.g., the coefficient is set to 0.8) to obtain a new adjustment step size. The transmission delay time and sampling window offset are finely adjusted again according to the new adjustment step size. The timing convergence verification operation is repeated until the verification result shows a difference less than or equal to the preset qualified threshold, thus completing the timing calibration of the reverse transition transmission channel pulse edge.

[0050] Therefore, in this application, timing parameters of the pulse edge of the reverse transition transmission channel can be calibrated based on the jitter suppression amount and the waveform distortion. Firstly, by receiving reference clock signals at each transmission channel receiver and determining the clock phase difference between adjacent channels, the influence of phase relationship on crosstalk coupling effect is accurately captured, breaking the limitations of traditional schemes that ignore phase correlation and focus only on single-channel optimization. Secondly, during periodic idle periods, crosstalk intensity is recorded by sending test signals through a single channel while the remaining channels are static. A pulse crosstalk matrix is ​​constructed based on the clock phase difference, achieving quantitative modeling of crosstalk intensity between multiple channels. This solves the problem of existing technologies lacking crosstalk quantitative analysis and difficulty in formulating precise correction strategies, upgrading the correction action from "blind compensation" to "quantitative driving." Furthermore, during the signal transmission stage, high crosstalk conditions with simultaneous reverse transitions of adjacent multiple channels are specifically identified, based on the crosstalk matrix... The system employs pulse edge suppression to directly address the core scenario of crosstalk caused by multi-channel coupling, effectively reducing signal edge jitter caused by reverse transitions and overcoming the bottleneck of traditional single-channel timing compensation being unable to cope with multi-channel coupling effects. Furthermore, by inserting a reference pulse during idle clock cycles and detecting waveform distortion, real-time distortion monitoring of the ASIC chip during operation is achieved, eliminating the drawbacks of traditional offline calibration relying on external equipment and being disconnected from actual operating conditions, and providing real-time feedback for dynamic adjustment and correction. Finally, timing parameters are calibrated by combining jitter suppression and waveform distortion, forming a closed-loop mechanism of "quantitative modeling - risk suppression - real-time feedback - precise calibration," effectively alleviating the problem of increased signal edge jitter and bit error rate under high load, significantly improving the accuracy and integrity of high-speed signal transmission within the ASIC chip, and helping it to fully realize its extreme performance in high-end scenarios such as data centers and high-speed communications.

[0051] In summary, the technical solution adopted in this application can suppress multi-channel pulse crosstalk within the application-specific integrated circuit chip, thereby improving the integrity of chip signal transmission.

[0052] Example 2: This application provides an integrated circuit chip signal transmission correction system, referring to... Figure 4 As shown, this figure is a block structure diagram of an integrated circuit chip signal transmission correction system according to this embodiment of the present application. The chip signal transmission correction system includes: The clock signal receiving module 100 is used to receive a reference clock signal through the receiving end of each transmission channel in the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels; The pulse crosstalk analysis module 200 is used to send a transition test signal to each transmission channel in turn during periodic idle periods, while the other transmission channels remain static. The monitoring circuits at each receiving end record the pulse crosstalk intensity from the active transmission channels and construct the pulse crosstalk matrix of the dedicated integrated circuit chip based on all pulse crosstalk intensities and all clock phase differences. The pulse edge suppression module 300 is used to suppress the pulse edge of the transmission channel that has reversed transition simultaneously when more than a preset number of adjacent transmission channels are detected to be undergoing reverse transition during the signal transmission stage, based on the pulse crosstalk matrix, to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. The waveform distortion detection module 400 is used to insert a reference pulse during the idle clock cycle of the signal transmission phase and detect the waveform distortion of the reference pulse through the receiving end of the reverse switching transmission channel. The timing calibration module 500 is used to perform timing calibration on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

[0053] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compactdisc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0055] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

Claims

1. A method for signal transmission correction of an integrated circuit chip, characterized in that, The chip signal transmission correction method includes the following steps: The reference clock signal is received by the receiver of each transmission channel within the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels; During the periodic idle period, each transmission channel sends a transition test signal in sequence, while the other transmission channels remain static. The monitoring circuits at each receiver record the pulse crosstalk intensity from the active transmission channels, and construct the pulse crosstalk matrix of the application-specific integrated circuit chip based on all the pulse crosstalk intensities and all the clock phase differences. During the signal transmission stage, when it is detected that more than a preset number of adjacent transmission channels simultaneously undergo reverse transitions, pulse edge suppression is performed on the transmission channels undergoing reverse transitions according to the pulse crosstalk matrix to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. A reference pulse is inserted during the idle clock cycle of the signal transmission phase, and the waveform distortion of the reference pulse is detected by the receiver of the reverse switching transmission channel. Timing calibration is performed on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

2. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, Determining the clock phase difference between adjacent transmission channels specifically includes: The local sampling clock for each transmission channel is recovered from the received reference clock signal; The phase offset of each transmission channel is obtained by comparing the local sampling clock of each transmission channel with the global reference clock. The clock phase difference between adjacent transmission channels is determined based on the phase offset of each transmission channel.

3. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, During periodic idle periods, each transmission channel sequentially sends a transition test signal, while the remaining transmission channels remain static. The monitoring circuits at each receiver record the pulse crosstalk intensity from the active transmission channels, specifically including: During periodic idle periods, each transmission channel sends a transition test signal in sequence; When the test sequence controller designates a certain transmission channel as an active channel and sends a transition test signal, it controls the transmitters of all inactive transmission channels to maintain static output. The monitoring circuit at the receiving end of each inactive transmission channel acquires the voltage signal at the input end of the active transmission channel; Extract the peak value of crosstalk spikes generated by the active transmission channel from the voltage signal at the input of the active transmission channel; The pulse crosstalk intensity of the active transmission channel is determined based on the peak value of the crosstalk spikes generated by the active transmission channel and the static reference level. Then, the monitoring circuits of each receiver record the pulse crosstalk intensity from the active transmission channel.

4. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, The pulse crosstalk matrix of an application-specific integrated circuit (ASIC) chip is constructed based on all pulse crosstalk intensities and all clock phase differences, specifically including: The central processing unit acquires the pulse crosstalk intensity recorded in all test rounds, where each round corresponds to the pulse crosstalk of an active transmission channel to all other transmission channels; For each pair of transmission channels, each pair specifically includes a victim transmission channel and an attack transmission channel; Based on the clock phase difference between the victim transmission channel and the attack transmission channel in each pair of transmission channels, the pulse crosstalk intensity recorded on the victim transmission channel and measured from the attack transmission channel is calibrated in the time domain to obtain the crosstalk coupling coefficient corresponding to each pair of transmission channels. The pulse crosstalk matrix of the application-specific integrated circuit chip is constructed based on the crosstalk coupling coefficient corresponding to each pair of transmission channels.

5. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, Based on the pulse crosstalk matrix, pulse edge suppression is performed on the transmission channel experiencing reverse transitions. The specific jitter suppression amount for the pulse edge of the reverse transition transmission channel includes: The combination of transmission channels that simultaneously undergo reverse transitions and the corresponding clock phase difference are identified. The basis for determining the reverse transition is that the polarity of the transition edges of adjacent transmission channels is opposite. Based on the identified transmission channel combination number and clock phase difference, the pulse crosstalk matrix is ​​queried to extract the crosstalk coupling coefficient corresponding to the transmission channel with reverse transition; The edge suppression parameters of the reverse transition transmission channel are determined based on the crosstalk coupling coefficient corresponding to the reverse transition transmission channel. The delay of the signal edge of the reverse transition transmission channel is adjusted by using the edge suppression parameter of the reverse transition transmission channel; The jitter suppression amount of the reverse transition transmission channel pulse edge is determined based on the jitter value of the reverse transition transmission channel pulse edge after delay adjustment.

6. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, The waveform distortion of the reference pulse detected by the receiver of the reverse-switching transmission channel specifically includes: The reference pulse is sampled at equal intervals in the time domain by the sampling circuit at the receiving end of the reverse switching channel to obtain the waveform data of the reference pulse; The amplitude deviation rate, edge slope deviation rate, and pulse width deviation rate are extracted from the waveform data of the reference pulse. The waveform distortion of the reference pulse is determined based on the amplitude deviation rate, the edge slope deviation rate, and the pulse width deviation rate.

7. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, Timing calibration of the timing parameters of the reverse transition transmission channel pulse edge based on the jitter suppression amount and the waveform distortion specifically includes: The timing margin of the reverse transition transmission channel pulse edge is determined by the jitter suppression amount and the waveform distortion. The timing margin is used to adjust the transmission delay time of the pulse edge of the reverse transition transmission channel and the sampling window offset of the reverse transition transmission channel receiver. The timing convergence verification results of the adjusted transmission delay time and sampling window offset are obtained by performing timing convergence verification on the pulse edge of the reverse transition transmission channel. The calibration ends when the timing convergence verification result is satisfactory. When the timing convergence verification result is unqualified, the transmission delay time and the adjustment step size of the sampling window offset are adjusted according to the deviation information of the timing convergence verification, and the timing convergence verification is performed again. The above adjustment and verification process is repeated until the verification result is qualified.

8. The integrated circuit chip signal transmission correction method as described in claim 1, characterized in that, The pulse crosstalk matrix represents a matrix that reflects the pulse crosstalk coupling relationship between transmission channels within an application-specific integrated circuit (ASIC) chip.

9. The signal transmission correction method for an integrated circuit chip as described in claim 1, characterized in that, The jitter suppression amount represents the quantization value of suppressing pulse crosstalk jitter caused by the reverse transition of the transmission channel due to the reverse transition of the adjacent transmission channel.

10. An integrated circuit chip signal transmission correction system, used to perform an integrated circuit chip signal transmission correction method as described in any one of claims 1 to 9, characterized in that, The chip signal transmission correction system includes: The clock signal receiving module is used to receive a reference clock signal through the receiving end of each transmission channel in the dedicated integrated circuit chip, thereby determining the clock phase difference between adjacent transmission channels; The pulse crosstalk analysis module is used to send a transition test signal to each transmission channel in turn during periodic idle periods, while the other transmission channels remain static. The monitoring circuits at each receiving end record the pulse crosstalk intensity from the active transmission channel and construct the pulse crosstalk matrix of the dedicated integrated circuit chip based on all pulse crosstalk intensities and all clock phase differences. The pulse edge suppression module is used to suppress the pulse edges of the transmission channels that have reverse transitions simultaneously when more than a preset number of adjacent transmission channels are detected to be undergoing reverse transitions during the signal transmission stage, based on the pulse crosstalk matrix, to obtain the jitter suppression amount of the pulse edge of the reverse transition transmission channel. The waveform distortion detection module is used to insert a reference pulse during the idle clock cycle of the signal transmission phase and detect the waveform distortion of the reference pulse through the receiving end of the reverse switching transmission channel. The timing calibration module is used to perform timing calibration on the timing parameters of the pulse edge of the reverse transition transmission channel based on the jitter suppression amount and the waveform distortion.

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