Method and system for data transmission of multi-node chassis based on hardware information virtualization

Abstract

The application relates to the technical field of communication device hardware management, and provides a multi-node chassis hardware state data transmission method and system based on hardware information virtualization. The method comprises the following steps: a hardware information virtualization process of a node card reads local hardware information and writes the hardware information into a partition shared memory; a sending end process packetizes information blocks according to a self-defined communication protocol, and sends the information blocks to a main control card through a point-to-point link in parallel, wherein the protocol defines a data packet structure containing a node identifier, a block serial number and a total block number; a receiving end process of the main control card receives, checks and splices the data packets in parallel; the restored information is stored into a main control card shared memory according to the node identifier; and the whole link process and data transmission are monitored, process abnormity is automatically restarted, and selective data packet retransmission is realized. The application solves the problems of dispersion in collection, non-compatibility in protocol, high transmission delay and insufficient reliability in a traditional architecture.

Description

Technical Field

[0001] This application relates to the field of communication equipment hardware management technology, specifically to a multi-node chassis data transmission method and system based on hardware information virtualization. Background Technology

[0002] Existing multi-node chassis data transmission technologies suffer from several core defects: First, the transmission architecture relies on traditional backplane relays, which can easily lead to link contention during concurrent transmission by multiple nodes, resulting in high data transmission latency and low efficiency. Second, hardware information acquisition is scattered across various nodes, with significant differences in hardware interfaces between different node cards and a lack of unified data formats, causing incompatible transmission protocols and difficulties in cross-node data sharing. Third, the core processes (acquisition, transmission, and reception processes) lack effective monitoring and rapid recovery mechanisms, making data loss and acquisition interruptions likely when links are abnormal or processes crash, resulting in insufficient system reliability. Fourth, data storage lacks standardized partition management, making concurrent read and write operations prone to data conflicts and resulting in low query efficiency, which is insufficient to support the real-time monitoring and scheduling needs of upper-layer applications. Summary of the Invention

[0003] To help solve the above-mentioned technical problems, this application provides a multi-node chassis data transmission method and system based on hardware information virtualization.

[0004] Firstly, this application provides a multi-node chassis data transmission method based on hardware information virtualization, employing the following technical solution: A multi-node chassis data transmission method based on hardware information virtualization, applied to a system containing at least two node cards and at least one master control card, the method comprising: S1: The hardware information virtualization process on each node card traverses and reads the information of various local hardware modules and writes it into the shared memory of the node card. S2: The sending process on each node card reads standardized hardware information from shared memory, divides it into packets of a preset size according to a custom communication protocol, and sends them concurrently to the main control card through independent point-to-point links. The custom communication protocol defines the data packet structure for block transmission. The data packet structure includes a packet header and a data segment. The packet header defines at least the node card identifier, the block sequence number, and the total block number segment. S3: The receiving process on the main control card concurrently receives data packets from multiple node cards, performs verification, buffering and splicing based on the field information defined in the data packet structure, and restores it to complete standardized hardware information; S4: Write the restored hardware information to the shared memory on the main control card; S5: Monitors the running status of the hardware information virtualization process, the sending process, and the receiving process, and performs process restart or data retransmission operations when an abnormality is detected.

[0005] The S1 includes: the information of the various local hardware modules includes one or more of the following: board FRU information, voltage, temperature, CPU model and status, memory status, hard disk status, and I2C device information read through the hardware interface configured by the node card.

[0006] S1 includes: performing standardized format conversion on information from various local hardware modules and writing it into the shared memory of the node card. The standardized format conversion includes: uniformly converting the read unstructured data and semi-structured data into a preset structured data format.

[0007] The S2 includes: the step of dividing the data into blocks according to a preset size specifically includes: dividing the standardized hardware information into multiple data blocks according to a preset block size parameter, and generating a corresponding data packet for each data block according to the custom communication protocol. The header of the data packet also includes a data packet type and a single packet data length field. The independent point-to-point link supports hot-swapping of node cards and automatically performs link reconnection after hot-swapping operation.

[0008] The S3 includes: the receiving process on the main control card concurrently receiving data packets from different node cards, parsing the packet header information to verify its legality and caching it according to the block sequence number, and after all the data of the same group from the same node card has been received in blocks, it is reassembled according to the sequence number to restore the complete standardized hardware information.

[0009] S3 includes: the verification of legality includes: verifying the node card identifier, data packet type and block sequence number of the data packet, and discarding data packets that fail verification.

[0010] The S3 includes: the block sequence number caching includes: maintaining a cache queue for each node card, and inserting valid data packets into the corresponding positions of the queue according to the parsed block sequence number.

[0011] S4 includes: the shared memory is stored using a partitioned structure for unified monitoring and scheduling by upper-layer applications. The restored hardware information is partitioned by node card identifier and written to the shared memory on the main control card for unified monitoring and scheduling by upper-layer applications. The partitioning by node card identifier specifically includes: allocating an independent storage area for each node card in the shared memory of the main control card, and writing the restored hardware information of the node card into its corresponding storage area. Within the storage area corresponding to each node card, sub-partitions are further divided according to the type of hardware information for storage.

[0012] S5 includes: monitoring the status of the hardware information virtualization process, the sending process and the receiving process through an independent monitoring module, and automatically restarting the corresponding process within a preset time when an abnormal process is detected; When the receiving process detects missing segments or verification failures during the splicing and restoration process, it sends a retransmission request for a specific segment sequence number to the corresponding node card, triggering the node card to perform selective retransmission. The selective retransmission specifically means that after receiving the retransmission request for a specific segment sequence number, the node card sending end only reassembles and sends the segment data packet corresponding to the requested sequence number. The process anomalies include process crashes or process unresponsiveness, and the automatic restart of the corresponding process is triggered by an independent monitoring module based on the file system event monitoring mechanism.

[0013] Secondly, this application provides a multi-node chassis data transmission system based on hardware information virtualization, employing the following technical solution: A multi-node chassis data transmission system based on hardware information virtualization for implementing the method described in any of the above claims, comprising: At least two node cards, each node card being configured with at least: Processing unit; Hardware information acquisition interface, used to connect to various local hardware modules; Storage module, used to provide shared memory; Interconnect module; The communication module integrates a protocol processing unit; At least one main control card, configured with: Processing unit; Storage module, used to provide shared memory; Interface array; Communication module; The internal physical network consists of independent point-to-point links between the interconnect modules of each node card and the interface array of the main control card; The node card's processing unit is used to run the hardware information virtualization process and the sending process; the node card's protocol processing unit is used to implement a custom communication protocol and to segment and assemble hardware information into packets; the main control card's processing unit is used to run the receiving process; and the main control card's communication module is used to concurrently receive and process data packets from multiple node cards.

[0014] In summary, compared with the prior art, the method of this application has the following advantages: 1. Custom communication protocol: It adopts a custom data packet structure and serialization method, which is specially adapted to the block concurrency requirements of chassis network. It supports flexible specification of data packet block size, balances transmission efficiency and data security, and avoids the problem of excessive resource consumption caused by compatibility with general protocols. 2. Shared memory partition management: Both the node card and the main control card use a partitioned storage strategy for shared memory, combined with a read-write lock mechanism, to achieve safe concurrent read and write operations, while facilitating data classification management and fast querying; 3. Fault self-recovery and retransmission mechanism: The hardware information virtualization process has a self-restart function, the sending end supports data packet caching and retransmission, and the receiving end has dual verification and exception handling capabilities. Combined with the automatic reconnection feature of the internal links of the chassis, a full-link fault protection is formed to ensure the stability of system operation and data integrity. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the multi-node chassis data transmission system based on hardware information virtualization according to this application; Figure 2 This is a schematic diagram illustrating the data interaction and control process between the node cards and the main control card in the multi-node chassis of this application. Figure 3 This is a flowchart illustrating the hardware information virtualization process of this application; Figure 4 This is a detailed flowchart of the sending end of this application; Figure 5 This is a detailed flowchart of the receiving end of this application; Figure 6 This is a detailed flowchart illustrating the fault self-recovery and retransmission mechanism of this application. Detailed Implementation

[0016] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0017] This application provides a multi-node chassis data transmission method based on hardware information virtualization, applicable to a system containing at least two node cards and at least one main control card. The method includes: S1: The hardware information virtualization process on each node card traverses and reads the information of various local hardware modules and writes it into the shared memory of the node card.

[0018] In step S1, after the system is powered on, the hardware information virtualization process of each node card starts, traverses and reads the initial state information of all hardware modules of the card, and writes it into the shared memory of the card after standardization processing.

[0019] S2: The sending process on each node card reads standardized hardware information from shared memory, divides it into packets of a preset size according to a custom communication protocol, and sends them concurrently to the main control card through independent point-to-point links. The custom communication protocol defines the data packet structure for block transmission. This data packet structure includes a packet header and a data segment. The packet header defines at least the node card identifier, the block sequence number, and the total block number segment.

[0020] In step S2, the sending process of each node card is woken up according to a preset period, reads the latest standardized hardware information from the shared memory, calls the protocol processing unit, divides the data into blocks and packets according to a preset size according to the custom communication protocol, generates a series of data packets with packet header information such as node card ID and block sequence number, and then sends them to the main control card concurrently through the corresponding point-to-point link.

[0021] S3: The receiving process on the main control card concurrently receives data packets from multiple node cards, verifies, buffers, and concatenates them according to the field information defined in the data packet structure, and restores them into complete standardized hardware information.

[0022] In step S3, the receiving process of the main control card continuously monitors all links. It concurrently receives data packets from different node cards, parses the packet headers for validity verification. Valid data packets are cached according to the node card ID and block sequence number. When all blocks of a complete set of data from a certain node card have been received, they are concatenated according to the sequence number to restore a complete standardized hardware information data block.

[0023] S4: Write the restored hardware information to the shared memory on the main control card.

[0024] In step S4, the receiving process writes the restored complete hardware information, according to the source node card ID, into the independent storage partition allocated to that node card in the shared memory. The upper-layer monitoring application can then obtain a real-time, unified hardware status view of all node cards by reading this shared memory.

[0025] S5: Monitors the running status of the hardware information virtualization process, the sending process, and the receiving process, and performs process restart or data retransmission operations when an abnormality is detected.

[0026] In step S5, the hardware information virtualization process periodically updates the data in the shared memory. The sending process then initiates a new round of transmission. Simultaneously, the monitoring module deployed in the system monitors the health status of each core process and the integrity of data transmission in real time. If a process anomaly is detected, the monitoring module automatically restarts the process within a few seconds. If the receiving end detects packet loss or a checksum error, it initiates a selective retransmission request for the specific lost data segment to the corresponding node card. The node card only retransmits that segment, not all the data.

[0027] The S1 includes: the information of the various local hardware modules includes one or more of the following: board FRU information, voltage, temperature, CPU model and status, memory status, hard disk status, and I2C device information read through the hardware interface configured by the node card.

[0028] S1 includes: performing standardized format conversion on information from various local hardware modules and writing it into the shared memory of the node card. The standardized format conversion includes: uniformly converting the read unstructured data and semi-structured data into a preset structured data format.

[0029] The S2 includes: the step of dividing the data into blocks according to a preset size specifically includes: dividing the standardized hardware information into multiple data blocks according to a preset block size parameter, and generating a corresponding data packet for each data block according to the custom communication protocol. The header of the data packet also includes a data packet type and a single packet data length field. The independent point-to-point link supports hot-swapping of node cards and automatically performs link reconnection after hot-swapping operation.

[0030] S3 includes: The receiving process on the main control card concurrently receives data packets from different node cards, parses the packet header information to verify its validity, and buffers them according to the block sequence number. After all the data of the same group from the same node card has been received in blocks, they are reassembled according to the sequence number to restore the complete standardized hardware information.

[0031] S3 includes: The verification of legality includes: verifying the node card identifier, data packet type, and block sequence number of the data packet, and discarding data packets that fail verification.

[0032] The S3 includes: the block sequence number caching includes: maintaining a cache queue for each node card, and inserting valid data packets into the corresponding positions of the queue according to the parsed block sequence number.

[0033] S4 includes: The shared memory is stored using a partitioned structure for unified monitoring and scheduling by upper-layer applications. The restored hardware information is partitioned by node card identifier and written to the shared memory on the main control card for unified monitoring and scheduling by upper-layer applications. The partitioning by node card identifier specifically includes: allocating an independent storage area for each node card in the shared memory of the main control card, and writing the restored hardware information of the node card into its corresponding storage area. Within the storage area corresponding to each node card, sub-partitions are further divided according to the type of hardware information for storage.

[0034] S5 includes: The status of the hardware information virtualization process, the sending process, and the receiving process is monitored by an independent monitoring module, and the corresponding process is automatically restarted within a preset time when an abnormal process is detected. When the receiving process detects missing segments or verification failures during the splicing and restoration process, it sends a retransmission request for a specific segment sequence number to the corresponding node card, triggering the node card to perform selective retransmission. The selective retransmission specifically means that after receiving the retransmission request for a specific segment sequence number, the node card sending end only reassembles and sends the segment data packet corresponding to the requested sequence number. The process anomalies include process crashes or process unresponsiveness, and the automatic restart of the corresponding process is triggered by an independent monitoring module based on the file system event monitoring mechanism.

[0035] Specifically, the overall operation flow of this system is as follows, forming a complete closed loop for hardware information processing: After the system starts, the hardware information virtualization process of each node card starts automatically, completes the first traversal reading and standardization of hardware information, and writes it to the local shared memory of the node card. Each node card's transmitting end relies on the interconnect module to listen to local shared memory data, divides standardized hardware information into blocks of preset size, assembles and serializes them, and sends all block data packets concurrently through the internal physical network of the chassis; The main control card receiver concurrently receives the segmented data packets from each node card. After filtering and verification, the data packets are assembled according to the segment sequence number to restore the complete hardware information. Then, after unpacking and deserialization, the data packets are partitioned according to the node card ID and written to the main control card's shared memory. The receiving end sends an acknowledgment signal to the corresponding node card. After the node card sends the data and confirms that the data has been successfully sent, it waits for the next round of data updates. The hardware information virtualization process updates the local shared memory data of the node card according to a preset cycle. The sending end synchronously initiates a new round of data packet transmission, and the receiving end repeats the unpacking and writing process to achieve real-time synchronization of hardware information. Other application software on the main control card can read shared memory data to achieve functions such as hardware status monitoring and fault early warning. At the same time, it can send instructions to the node card through the receiving end to adjust parameters such as hardware information acquisition cycle, transmission cycle, and data packet block size.

[0036] Figure 2The system clearly presents a closed-loop process for collecting, segmenting, and concurrently transmitting system hardware information to management and control. It explicitly demonstrates the core characteristics of "concurrent processing and segmentation according to preset sizes," fully covering segmentation and concurrency logic. It supports adjusting segmentation size parameters and encompasses the collaborative logic of normal data processing links, abnormal segmented data processing branches, and segmentation concurrency mechanisms. Two-way interaction between node cards and the main control card (segmented data upload and response), multiple verification mechanisms, and fault handling mechanisms are all reflected in the process, ensuring its integrity and traceability.

[0037] The hardware information virtualization process is deployed on the local processing unit of each node card, running in a background resident process mode. Its startup priority is higher than other non-core processes on the node card to ensure the real-time nature of hardware information acquisition. The specific implementation steps of this process are as follows: Hardware Information Traversal and Reading: After the process starts, it uses various hardware interfaces configured on the node card to traverse and read information from all hardware modules of the node card at preset intervals (configurable from 1s to 60s). The read content includes, but is not limited to: FRU information, voltage, temperature, chip temperature, optical module data, CPU model, clock speed, utilization rate, and temperature; memory capacity and usage rate; hard drive model, capacity, remaining space, and health status; and other I2C device information. During the reading process, the accuracy of the information is ensured through native operating system interfaces or low-level library APIs.

[0038] Information format standardization processing: Standardize the various types of hardware information read, and convert unstructured data (such as hardware model in string format) and semi-structured data (such as sensor data in binary format) into a preset structured data format.

[0039] Shared memory write and update: Standardized hardware information is written to the shared memory of the node card's local file system. The shared memory uses a partitioned storage strategy, with different types of hardware information stored in corresponding partitions. Each partition is equipped with a read-write lock to prevent data overwriting or corruption caused by concurrent read and write operations. Processes update the corresponding data in the shared memory at preset intervals to ensure that the data in the shared memory is consistent with the actual hardware state. If the hardware information remains unchanged, the original data is maintained, reducing unnecessary write operations and lowering system resource consumption.

[0040] Furthermore, the hardware information virtualization process has a self-recovery function. If the process is interrupted due to a node card hardware malfunction or software failure, the node card's local monitoring module will restart the process within 3 seconds and re-execute the hardware information traversal, reading, and initialization write operations to ensure uninterrupted hardware information acquisition. For details on the hardware information virtualization process, please refer to [link to relevant documentation]. Figure 3 . The sending end is deployed in the communication module of each node card. It establishes a connection with the hardware information virtualization process through a local inter-process communication mechanism and reads hardware information data from the shared memory of the node card at a preset period. The specific implementation steps are as follows: Hardware Information Reading and Packet Assembly: The sending end reads structured hardware information from shared memory at a preset period (consistent with the virtualization process's acquisition period, configurable independently). Before reading, read permissions are obtained through a read-write lock to avoid conflicts with the virtualization process's write operations. After reading, the structured data can be divided into packets according to user-preset parameters. The size of each data packet can be flexibly specified (configurable range: 16384 bytes - 65535 bytes). The packet assembly process follows a custom communication protocol. The structure of each packet is uniform: header (42 bytes, including node card ID, data packet type, packet sequence number, total number of packets, and single packet length), data segment (stores standardized hardware information after segmentation, with a length consistent with the preset single packet size; the last data packet can be adaptively filled), ensuring the integrity and splicability of the segmented data.

[0041] Concurrent Data Packet Transmission Control: The sending end serializes the segmented data packets using a custom communication protocol. Before transmission, the sending end checks the status of the transmission link, relying on the signal feedback function of the node card interconnection module to determine if the link is normal. If the link is normal, all segmented data packets are transmitted concurrently through the link, without priority distinction; if the link is abnormal, the transmission is skipped, and the packets are reassembled and transmitted after the link is restored. Detailed design of the sending end can be found in [reference needed]. Figure 4 .

[0042] The receiving end is deployed in the communication module of the main control card, which can process data packets sent by multiple node cards simultaneously. The specific implementation steps are as follows: Concurrent Data Packet Reception and Filtering / Assembling: The receiving end uses a multi-channel network transceiver chip to monitor the internal physical network links in real time. Relying on the parallel processing capabilities of the main control card interface array, it concurrently receives segmented data packets sent by each node card and processes them one by one in the receiving order. When a data packet is detected, it first deserializes and parses the packet header information to extract key information such as node card ID, segment sequence number, and total number of segments. Illegal data packets (such as non-existent node card ID, mismatched data packet type, or abnormal segment sequence number) are discarded, and the illegal data packet information is recorded. For legitimate data packets, they are buffered according to the node card ID and segment sequence number. After all segmented data packets in a group have been received, they are assembled according to the sequence number to restore the complete structured hardware information.

[0043] Data packet unpacking and data restoration: The receiving end unpacks the assembled complete data packet. First, it strips the packet header, extracts the structured hardware information in the data segment, and then deserializes the data packet using a custom communication protocol to restore it to a standardized hardware information format (consistent with the output format of the node card virtualization process).

[0044] Shared memory writing and data synchronization: The receiving end writes the restored legitimate hardware information into the shared memory of the master control card's file system according to the node card ID partition. Each node card corresponds to an independent shared memory partition, and the partition is further subdivided according to the hardware type for storage, which facilitates subsequent reading and management by the master control card.

[0045] Multi-node data management: The receiving end supports unified management of hardware information for each node card. Node cards send data packets at preset intervals (e.g., 10 seconds). The main control card immediately updates real-time data upon receiving the data packet from the corresponding node card, ensuring efficient utilization of shared memory space. Simultaneously, it supports quick querying of corresponding hardware information by node card ID and hardware type, with data read latency controlled within 1ms. The node card sending module provides a real-time data transmission API interface, sending data immediately before the preset interval to complete the synchronous update of real-time hardware information. Detailed receiver procedures can be found in [link to relevant documentation]. Figure 5 .

[0046] Fault self-recovery and retransmission mechanisms are the core support for ensuring stable system operation. They run through the entire process of hardware information acquisition, transmission, and processing, covering three core scenarios: process fault self-recovery, link fault self-recovery, and data packet retransmission. The specific implementation steps are as follows: Process failure self-recovery: The system's core processes (hardware information virtualization process, sending process, and receiving process) are all equipped with independent monitoring modules. The monitoring modules are lightweight processes that are permanently resident on the node card / main control card and are bound to the core processes. They monitor the process status based on inotify event-driven monitoring. If the monitoring module detects an abnormal state of the core process, it determines that the process is abnormal (such as process crash or freeze). Resumption of execution: Hardware information virtualization process abnormal: The monitoring module restarts the process within 3 seconds. After restarting, it automatically performs interface initialization, initial hardware information traversal and reading, standardization processing, and shared memory initialization and writing to ensure that the acquisition link is not interrupted. Sender / receiver process anomaly: The monitoring module restarts the process within 2 seconds. After restarting, it automatically rebuilds the network connection (sender and virtualization process), initializes the communication link, and restores data transmission capability. Fault logging: The process anomaly and recovery process are recorded in the local log.

[0047] Data packet retransmission mechanism: For scenarios such as data packet loss and verification failure, a precise retransmission strategy is implemented to avoid retransmitting the entire data. When the receiving end reassembles a data packet and finds a missing segment or data verification failure, it determines the data packet to be abnormal. The receiving end sends a retransmission request to the corresponding node card, explicitly specifying the missing / abnormal segment sequence number. The node card only retransmits the target segment, without sending the entire packet. If the sending end still does not receive a response after three retransmissions, or the receiving end still does not obtain a valid segment after requesting retransmission, the data transmission for that group is marked as failed, a fault log is recorded and reported, and the packet is reassembled and sent in the next cycle. For details on the fault self-recovery and retransmission mechanism, please refer to [link to relevant documentation]. Figure 6 .

[0048] This application also proposes a multi-node chassis data transmission system based on hardware information virtualization for implementing the above method, comprising: At least two node cards, each node card being configured with at least: Processing unit; Hardware information acquisition interface, used to connect to various local hardware modules; Storage module, used to provide shared memory; Interconnect module; The communication module integrates a protocol processing unit; At least one main control card, configured with: Processing unit; Storage module, used to provide shared memory; Interface array; Communication module; The internal physical network consists of independent point-to-point links between the interconnect modules of each node card and the interface array of the main control card; The node card's processing unit is used to run the hardware information virtualization process and the sending process; the node card's protocol processing unit is used to implement a custom communication protocol and to segment and assemble hardware information into packets; the main control card's processing unit is used to run the receiving process; and the main control card's communication module is used to concurrently receive and process data packets from multiple node cards.

[0049] System hardware configuration details: 1. Node Card Hardware Configuration Each node card is equipped with an independent processing chip; it is configured with hardware information acquisition interfaces, including but not limited to PCIe, SATA, I2C and GPIO interfaces, which can cover information reading of various hardware modules such as CPU, memory, hard disk, I2C devices; it is configured with a local file system module, a sending end communication module, and integrates an interconnect module and a protocol processing unit. The interconnect module adapts to the link characteristics of the chassis and works with the protocol processing unit to complete the encapsulation and transmission of custom communication protocols.

[0050] 2. Main control card hardware configuration The main control card is equipped with a high-performance processing chip; it is also equipped with a receiver communication module that adapts to the transmission characteristics of multi-node chassis links, supports the simultaneous and concurrent reception of data packets sent by multiple node cards through interconnection links, and has data packet collision detection and reassembly functions. All data packets are processed in the order of concurrent reception; it is also equipped with a data interaction interface that can interact with upper-layer application software to realize the visualization of hardware information and command issuance.

[0051] 3. Internal physical network configuration Based on the hardware configuration of the node cards and the main control card described above, the internal physical network of the chassis in this embodiment is based on a modular communication architecture to achieve efficient interconnection between the main control card and each node card. Under this architecture, each node card establishes a point-to-point communication link with the main control card through an independent interconnection module to adapt to the high-speed data interaction requirements of multiple nodes.

[0052] The main control card, as the core interaction node, interconnects with the interconnect modules of each node card through the interface array. Each node card has its own dedicated transmission link, avoiding link contention when multiple nodes transmit concurrently. It also supports hot-swapping of node cards, so adding or removing node cards does not affect the normal operation of other links, adapting to the high scalability of the architecture.

[0053] In addition, the network interface is adapted to the mechanical layout, and the interface between the node card and the main control card adopts a foolproof plug-and-play design. The interface speed is matched with the link transmission speed, and the link is automatically reconnected during hot-swapping. This ensures the continuity of the overall system operation during node card maintenance and further improves the ease of maintenance of the chassis.

[0054] To intuitively present the core hardware configuration and board interconnection relationships of the system, the following simplified hardware topology diagram is used to abstractly describe the board collaboration scenario: Figure 1 The topology diagram simplifies the core hardware structure, including 2 main control cards, 3 node cards, and key components of each board. It clearly shows the core interconnection logic within the chassis of the node cards, the internal physical network, and the main control cards, while also demonstrating the core driving relationships of each module.

[0055] This embodiment, through the above design, achieves efficient acquisition, secure transmission, and centralized management of hardware information within a multi-node chassis, offering the following advantages compared to existing technologies: High real-time performance: Relying on the characteristics of low-latency links, combined with efficient virtualization and transmission mechanisms, the hardware information acquisition, transmission and restoration process has extremely low latency, which can reflect the hardware operating status in real time. Wide compatibility: Supports information reading from various hardware modules, adapts to different types of node cards, and combines hot-swappable and highly expandable features to flexibly increase or decrease the number of nodes without modifying the core link design; High reliability: Equipped with process self-recovery, data packet retransmission and link automatic reconnection mechanisms, it effectively avoids data loss and errors, and ensures stable operation of the system under the backplane-less architecture; High security: The combination of self-developed protocols and internal closed network transmission prevents data leakage and tampering, ensuring hardware information security.

[0056] In summary, this application addresses the pain points of traditional technologies through overall design, achieving efficient, compatible, and reliable transmission and management of hardware information across multiple nodes in a chassis. At the hardware level, it employs a distributed architecture with dual main control cards and multiple node cards, abandoning traditional backplane relays and allocating dedicated transmission channels to each node card via independent point-to-point links, completely avoiding concurrent link contention. At the data processing level, hardware information virtualization processes are deployed on each node card to uniformly collect various hardware interface data and complete standardized format conversion, resolving compatibility issues with multiple interfaces and heterogeneous data. At the transmission level, a custom communication protocol enables data segmentation and packetization, concurrent transmission, and precise splicing. Combined with partitioned shared memory between node cards and main control cards, it balances transmission efficiency and storage security, improving data query speed. At the assurance level, a full-link fault protection system is constructed. Through inotify-driven independent process monitoring and rapid restart mechanisms, automatic link reconnection, and precise data packet retransmission strategies, it forms a self-recovery capability for the entire process of acquisition, transmission, and storage, ensuring stable system operation and ultimately achieving the core objective of centralized management and real-time monitoring of hardware information.

Claims

1. A multi-node chassis data transmission method based on hardware information virtualization, characterized in that, Applied to a system containing at least two node cards and at least one master control card, the method includes: S1: The hardware information virtualization process on each node card traverses and reads the information of various local hardware modules and writes it into the shared memory of the node card. S2: The sending process on each node card reads standardized hardware information from shared memory, divides it into packets of a preset size according to a custom communication protocol, and sends them concurrently to the main control card through independent point-to-point links. The custom communication protocol defines the data packet structure for block transmission. The data packet structure includes a packet header and a data segment. The packet header defines at least the node card identifier, the block sequence number, and the total block number segment. S3: The receiving process on the main control card concurrently receives data packets from multiple node cards, verifies, buffers, and concatenates them according to the field information defined in the data packet structure, and restores them into complete standardized hardware information; S4: Write the restored hardware information to the shared memory on the main control card; S5: Monitors the running status of the hardware information virtualization process, the sending process, and the receiving process, and performs process restart or data retransmission operations when an abnormality is detected.

2. The method according to claim 1, characterized in that, The S1 includes: the information of the various local hardware modules includes one or more of the following: board FRU information, voltage, temperature, CPU model and status, memory status, hard disk status, and I2C device information read through the hardware interface configured by the node card.

3. The method according to claim 1, characterized in that, S1 includes: performing standardized format conversion on information from various local hardware modules and writing it into the shared memory of the node card. The standardized format conversion includes: uniformly converting the read unstructured data and semi-structured data into a preset structured data format.

4. The method according to claim 1, characterized in that, The S2 includes: the step of dividing the data into blocks according to a preset size specifically includes: dividing the standardized hardware information into multiple data blocks according to a preset block size parameter, and generating a corresponding data packet for each data block according to the custom communication protocol. The header of the data packet also includes a data packet type and a single packet data length field. The independent point-to-point link supports hot-swapping of node cards and automatically performs link reconnection after hot-swapping operation.

5. The method according to claim 1, characterized in that, S3 includes: The receiving process on the main control card concurrently receives data packets from different node cards, parses the packet header information to verify its validity, and buffers them according to the block sequence number. After all the data of the same group from the same node card has been received in blocks, they are reassembled according to the sequence number to restore the complete standardized hardware information.

6. The method according to claim 5, characterized in that, S3 includes: The verification of legality includes: verifying the node card identifier, data packet type, and block sequence number of the data packet, and discarding data packets that fail verification.

7. The method according to claim 5, characterized in that, The S3 includes: the block sequence number caching includes: maintaining a cache queue for each node card, and inserting valid data packets into the corresponding positions of the queue according to the parsed block sequence number.

8. The method according to claim 1, characterized in that, S4 includes: The shared memory is stored using a partitioned structure for unified monitoring and scheduling by upper-layer applications. The restored hardware information is partitioned by node card identifier and written to the shared memory on the main control card for unified monitoring and scheduling by upper-layer applications. The partitioning by node card identifier specifically includes: allocating an independent storage area for each node card in the shared memory of the main control card, and writing the restored hardware information of the node card into its corresponding storage area. Within the storage area corresponding to each node card, sub-partitions are further divided according to the type of hardware information for storage.

9. The method according to claim 1, characterized in that, S5 includes: The status of the hardware information virtualization process, the sending process, and the receiving process is monitored by an independent monitoring module, and the corresponding process is automatically restarted within a preset time when an abnormal process is detected. When the receiving process detects missing segments or verification failures during the splicing and restoration process, it sends a retransmission request for a specific segment sequence number to the corresponding node card, triggering the node card to perform selective retransmission. The selective retransmission specifically means that after receiving the retransmission request for a specific segment sequence number, the node card sending end only reassembles and sends the segment data packet corresponding to the requested sequence number. The process anomalies include process crashes or process unresponsiveness, and the automatic restart of the corresponding process is triggered by an independent monitoring module based on the file system event monitoring mechanism.

10. A multi-node chassis data transmission system based on hardware information virtualization for implementing the method as described in any one of claims 1 to 9, characterized in that, include: At least two node cards, each node card being configured with at least: Processing unit; Hardware information acquisition interface, used to connect to various local hardware modules; Storage module, used to provide shared memory; Interconnect module; The communication module integrates a protocol processing unit; At least one main control card, configured with: Processing unit; Storage module, used to provide shared memory; Interface array; Communication module; The internal physical network consists of independent point-to-point links between the interconnect modules of each node card and the interface array of the main control card; The node card's processing unit is used to run the hardware information virtualization process and the sending process; the node card's protocol processing unit is used to implement a custom communication protocol and to segment and assemble hardware information into packets; the main control card's processing unit is used to run the receiving process; and the main control card's communication module is used to concurrently receive and process data packets from multiple node cards.

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