Heterojunction bipolar transistor and preparation method thereof, semiconductor integrated device and preparation method thereof
By employing a vertical structure design in the heterojunction bipolar transistor, carrier transport is directly realized in the vertical direction, solving the problems of parasitic resistance and parasitic capacitance, and improving high-frequency performance.
CN122121186APending Publication Date: 2026-05-29WUXI CANGHAI YUNFAN ELECTRONIC TECH CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CANGHAI YUNFAN ELECTRONIC TECH CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-29
AI Technical Summary
Technical Problem
Existing heterojunction bipolar transistors have large parasitic resistance and parasitic capacitance, which limits their application in high-frequency circuits.
Method used
By adopting a vertical structure design, the signal port of the collector region is located on one side of the second surface of the first substrate layer. Through the vertical conductive structure and the signal ports of the base region and emitter region located on one side of the first surface, the direct transmission of charge carriers in the vertical direction is realized, shortening the transmission path.
Benefits of technology
This reduces the parasitic resistance and capacitance of the device, improving its performance in high-frequency applications.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122121186A_ABST
Abstract
The application relates to the technical field of semiconductor integrated circuits, and discloses a heterojunction bipolar transistor and a preparation method thereof, and a semiconductor integrated device and a preparation method thereof. The transistor comprises a first substrate layer, a collector region, a base region, an emitter region, a base, an emitter and a first conductive structure, the collector region is formed on a first surface of the first substrate layer; the base region is formed on the collector region; the emitter region is formed on part of the surface of the base region; the base and the emitter are arranged on the first surface side of the first substrate layer, the base is connected with the base region, and the emitter is connected with the emitter region; and the first conductive structure is arranged on the second surface side and electrically connected with the collector region in the vertical direction. In the application, the signal ports of the base region and the emitter region are arranged on the first surface side, the signal port of the collector region is arranged on the second surface side opposite to the first surface, carrier transmission is directly realized in the longitudinal direction, the parasitic resistance and the parasitic capacitance of the device are reduced, and the device is helpful for the wide application of the device in a high-frequency scene.
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