An automatic gain control circuit for a transimpedance amplifier

Abstract

The application discloses an automatic gain control circuit of a trans-impedance amplifier, comprising a basic TIA circuit, an NMOS tube Q4, a voltage clamping module and a gain control module; the basic TIA circuit comprises NMOS tubes Q1, Q2 and Q3, resistors R1, R2, R3 and R4 and a capacitor C1; the source end of the NMOS tube Q4 is connected with the drain end of the NMOS tube Q2, and the drain end thereof is connected with the gate end of the NMOS tube Q1; the voltage clamping module is used for clamping the drain-source voltage of the NMOS tube Q4 at a fixed value, so that the NMOS tube Q4 works in a linear region; the gain control module is used for adjusting the gate end voltage of the NMOS tube Q4 according to the change of input optical power, so as to change the equivalent linear resistance of the NMOS tube Q4, realize continuous adjustment of the trans-impedance gain and elimination of direct current offset. The application introduces the NMOS tube Q4 working in the linear region, innovatively multiplexes the direct current offset circuit into the automatic gain control circuit, realizes continuous adjustment of the trans-impedance gain, reduces the parasitic capacitance introduced by the AGC circuit and optimizes the AGC circuit with continuous adjustable gain, so that the problem of difficult adjustment of a damping factor caused by the traditional gain continuous adjustable AGC circuit is solved.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to an automatic gain control circuit for a transimpedance amplifier. Background Technology

[0002] In the front-end of an optical receiver, the transimpedance amplifier (TIA) converts and amplifies the current signal output from the photodiode (PD) into a voltage signal before sending it to the subsequent amplifier for processing. As a core amplifier, the TIA's noise, sensitivity, and overload performance have a significant impact on the overall performance of the receiver system.

[0003] The sensitivity and overload performance of a TIA (Transient Identifier) ​​are defined as the minimum and maximum input optical power of the optical receiver within a specific bit error rate range. The difference between these two values ​​defines the input dynamic range of the TIA. Sensitivity is determined by the equivalent input noise; the lower the equivalent input noise, the higher the sensitivity. Overload performance is determined by the pulse width distortion of the output signal. To obtain lower equivalent input noise, a larger transimpedance gain is often required. However, a larger transimpedance gain results in greater signal distortion and lower overload capacity at higher input optical power.

[0004] Automatic gain control (AGC) circuits are used to balance the sensitivity and overload performance of the TIA. When the input optical power is high, AGC reduces the transimpedance gain, which can greatly improve the overload capability of the TIA while maintaining the input signal-to-noise ratio.

[0005] Traditional AGC circuits employ two main approaches: one uses a comparator to control the switching of the transimpedance to reduce transimpedance gain, offering discrete gain adjustment but often requiring a large switching array, which introduces significant parasitic capacitance and impacts bandwidth performance; the other involves connecting a MOSFET operating in the linear region in parallel across the transimpedance, providing continuously adjustable gain, but making TIA damping factor adjustment difficult. Therefore, specific circuit techniques are needed to address the shortcomings of traditional AGC circuits, further improving overload performance while maintaining sensitivity. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing an automatic gain control circuit for a transimpedance amplifier. This automatic gain control circuit multiplexes the DC offset circuit into an automatic gain control circuit, thereby achieving continuous adjustment of the transimpedance gain while reducing the parasitic capacitance introduced by the AGC circuit and optimizing the problem that the damping factor adjustment is difficult in traditional continuously adjustable AGC circuits.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] An automatic gain control circuit for a transimpedance amplifier includes a basic TIA circuit, an NMOS transistor Q4, a voltage clamping module, and a gain control module.

[0009] The basic TIA circuit includes NMOS transistors Q1, Q2, and Q3, resistors R1, R2, R3, and R4, and capacitor C1.

[0010] The gate of NMOS transistor Q1 is connected to photodiode PD, and the drain of NMOS transistor Q1 is connected to the source of NMOS transistor Q2; the drain of NMOS transistor Q2 is connected to the gate of NMOS transistor Q3.

[0011] The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of the resistor R1.

[0012] The drain terminal of the NMOS transistor Q2 and the supply voltage VDD are respectively connected to the two ends of the resistor R2.

[0013] The drain of NMOS transistor Q3 and the supply voltage VDD are respectively connected to the two ends of resistor R3.

[0014] The source terminal of NMOS transistor Q3 and the ground line GND are respectively connected to the two ends of resistor R4.

[0015] The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of capacitor C1.

[0016] The source terminal of NMOS transistor Q4 is connected to the drain terminal of NMOS transistor Q2, and the drain terminal of NMOS transistor Q4 is connected to the gate terminal of NMOS transistor Q1.

[0017] The input terminal V of the voltage clamping module IN1 Connect the gate terminal of NMOS transistor Q1, and connect its output terminal to the gate terminal of NMOS transistor Q2.

[0018] The input terminal V of the gain control module IN2 Connect the source terminal of NMOS transistor Q3, and its input terminal V IN3 Connect the gate terminal of NMOS transistor Q1, and its output terminal V OUT2 Connect to the gate of NMOS transistor Q4.

[0019] The voltage clamping module is used to clamp the drain-source voltage of NMOS transistor Q4 to a fixed value, so that it operates in the linear region.

[0020] The gain control module is used to adjust the gate voltage of NMOS transistor Q4 according to the change of input optical power, thereby changing its equivalent linear resistance and realizing continuous adjustment of transimpedance gain and elimination of DC offset.

[0021] The voltage clamping module includes PMOS transistors Q5, Q6, Q7, and Q8, current sources I1, I2, and I3, and operational amplifier Amp1.

[0022] The gate terminal of PMOS transistor Q5 is the input terminal VIN1 of the voltage clamping module; the drain terminal of PMOS transistor Q5 is connected to ground GND; the source terminal of PMOS transistor Q5 is connected to the output terminal of current source I1; the input terminal of current source I1 is connected to the supply voltage VDD; the drain terminal of PMOS transistor Q6 is connected to ground GND; the source terminal of PMOS transistor Q6 is connected to the output terminal of current source I2; the input terminal of current source I2 is connected to the supply voltage VDD; the gate terminal of PMOS transistor Q6 is connected to the drain terminal of NMOS transistor Q7.

[0023] The gate of the NMOS transistor Q7 is connected to the output of the operational amplifier; the drain of the NMOS transistor Q7 is connected to the source of the NMOS transistor Q8; the gate and drain of the NMOS transistor Q8 are connected to the power supply voltage VDD.

[0024] The positive input terminal of the operational amplifier is connected to the source terminal of PMOS transistor Q5, and its negative input terminal is connected to the source terminal of PMOS transistor Q6.

[0025] The input terminal of the current source I3 is connected to the gate terminal of the PMOS transistor Q6, and its output terminal is connected to ground GND.

[0026] The output current of current source I1 and current source I2 is the same.

[0027] The PMOS transistors Q5 and Q6 have identical geometric dimensions, and the source voltage V of PMOS transistor Q5 is the same. S5 and the source voltage V of PMOS transistor Q6 S6 Equal, the gate voltage V of PMOS transistor Q5 G5 and the gate voltage V of PMOS transistor Q6 G6 equal.

[0028] Let ΔV be the drain-source voltage difference of NMOS transistor Q4, and it be a fixed value. Then the gate voltage of NMOS transistor Q7 is the same as the gate voltage of NMOS transistor Q2. By adjusting the dimensions of NMOS transistors Q7 and Q2, the drain voltage V of NMOS transistor Q7 can be adjusted. S7 and the drain voltage V of NMOS transistor Q2 S2 Satisfy the following formula:

[0029] .

[0030] The gain control module includes PMOS transistor Q9 and PMOS transistor Q. 10Resistors R5, R6, and R7; current source I4 and I5; capacitors C2 and C3; and operational amplifier Amp2.

[0031] The gate terminal of PMOS transistor Q9 is the input terminal V of the gain control module. IN2 Its drain end is connected to ground GND.

[0032] PMOS transistor Q 10 The gate terminal is the input terminal V of the gain control module. IN3 Its drain is connected to ground GND, and its source is connected to the output of current source I5.

[0033] The input terminals of current source I4 and current source I5 are both connected to the supply voltage VDD.

[0034] The two ends of resistor R5 are connected to the source terminal of PMOS transistor Q9 and the output terminal of current source I4, respectively.

[0035] The two ends of resistor R6 are connected to the output terminal of current source I5 and the positive input terminal of operational amplifier Amp2, respectively.

[0036] The two ends of resistor R7 are connected to the output terminal of current source I4 and the negative input terminal of operational amplifier Amp2, respectively.

[0037] The two ends of capacitor C2 are connected to the positive input terminal of op-amp Amp2 and ground GND, respectively.

[0038] The two ends of capacitor C3 are connected to the negative input terminal and the output terminal of op-amp Amp2, respectively.

[0039] The output of op-amp Amp2 is also connected to the output of the gain control module V. OUT2 Connected.

[0040] The output currents of current source I4 and current source I5 are equal, resistors R6 and R7 are exactly the same, and capacitors C2 and C3 are exactly the same.

[0041] PMOS transistor Q9 and PMOS transistor Q 10 Their geometric dimensions are exactly the same, and the gate-source voltage difference V of PMOS transistor Q9 is the same. GS9 and PMOS transistor Q 10 Gate-source voltage difference V GS10 Equal; when the input optical power is 0, the source voltage difference V of PMOS transistor Q9 is equal. S9 and PMOS transistor Q 10 Source voltage V S10 equal.

[0042] Resistor R5 can set the automatic gain control threshold voltage V. TH And V TH=I4 R5; When the input optical power is low, the voltage difference across resistor R1 should not exceed the threshold voltage V. TH When the input optical power is high, the output of operational amplifier Amp2 is 0, the gain control module is not activated, NMOS transistor Q4 is turned off, and the gain remains at its maximum value. When the input optical power increases, the voltage difference across resistor R1 can exceed the threshold voltage V. TH When the output of op-amp Amp2 increases, the gain control module is activated, NMOS transistor Q4 turns on, and the gain begins to decrease.

[0043] The equivalent linear resistance of NMOS transistor Q4 satisfies the following formula:

[0044]

[0045] In the formula, R ON It is the equivalent linear resistance of NMOS transistor Q4; μ is the electron mobility; C OX V is the gate oxide capacitance per unit area of ​​NMOS transistor Q4; W is the channel width of NMOS transistor Q4; L is the channel length of NMOS transistor Q4; V GS It is the gate-source voltage difference of NMOS transistor Q4, V TH It is the threshold voltage for the NMOS transistor Q4 to turn on.

[0046] The present invention has the following beneficial effects: The present invention innovatively reuses the DC offset circuit as an automatic gain control circuit by using an NMOS transistor Q4 connected across the gate and drain of the input transistor and operating in the linear region. This achieves continuous adjustment of the transimpedance gain while reducing the parasitic capacitance introduced by the AGC circuit and optimizing the problem that the damping factor adjustment is difficult in the traditional continuously adjustable AGC circuit. Attached Figure Description

[0047] Figure 1 A schematic diagram of an automatic gain control circuit for a transimpedance amplifier according to the present invention is shown.

[0048] Figure 2 The circuit diagram of the voltage clamping module in this invention is shown.

[0049] Figure 3 The circuit diagram of the gain control module in this invention is shown.

[0050] Figure 4 The graph shows the variation of the transimpedance amplifier gain with the input current Ipd_dc in this invention.

[0051] Figure 5 This shows the drain-source voltage difference V of NMOS transistor Q4 in this invention. DS4 The graph shows the variation of input current Ipd_dc. Detailed Implementation

[0052] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0053] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0054] like Figure 1 As shown, an automatic gain control circuit for a transimpedance amplifier includes a basic TIA circuit, an NMOS transistor Q4, a voltage clamping module, and a gain control module.

[0055] The basic TIA circuit includes NMOS transistors Q1, Q2, and Q3, resistors R1, R2, R3, and R4, and capacitor C1.

[0056] The gate of NMOS transistor Q1 is connected to the anode of photodiode PD, and the cathode of photodiode PD is connected to the power supply voltage VDDPD; the drain of NMOS transistor Q1 is connected to the source of NMOS transistor Q2; and the drain of NMOS transistor Q2 is connected to the gate of NMOS transistor Q3.

[0057] The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of the resistor R1.

[0058] The drain terminal of the NMOS transistor Q2 and the supply voltage VDD are respectively connected to the two ends of the resistor R2.

[0059] The drain of NMOS transistor Q3 and the supply voltage VDD are respectively connected to the two ends of resistor R3.

[0060] The source terminal of NMOS transistor Q3 and the ground line GND are respectively connected to the two ends of resistor R4.

[0061] The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of capacitor C1.

[0062] The source terminal of NMOS transistor Q4 is connected to the drain terminal of NMOS transistor Q2, and the drain terminal of NMOS transistor Q4 is connected to the gate terminal of NMOS transistor Q1.

[0063] The input terminal V of the voltage clamping module IN1 Connect the gate terminal of NMOS transistor Q1, and connect its output terminal to the gate terminal of NMOS transistor Q2.

[0064] like Figure 2 As shown, the voltage clamping module includes PMOS transistors Q5, Q6, Q7, and Q8, current sources I1, I2, and I3, and operational amplifier Amp1.

[0065] The gate terminal of PMOS transistor Q5 is the input terminal VIN1 of the voltage clamping module; the drain terminal of PMOS transistor Q5 is connected to ground GND; the source terminal of PMOS transistor Q5 is connected to the output terminal of current source I1; the input terminal of current source I1 is connected to the supply voltage VDD; the drain terminal of PMOS transistor Q6 is connected to ground GND; the source terminal of PMOS transistor Q6 is connected to the output terminal of current source I2; the input terminal of current source I2 is connected to the supply voltage VDD; the gate terminal of PMOS transistor Q6 is connected to the drain terminal of NMOS transistor Q7.

[0066] The gate of the NMOS transistor Q7 is connected to the output of the operational amplifier; the drain of the NMOS transistor Q7 is connected to the source of the NMOS transistor Q8; the gate and drain of the NMOS transistor Q8 are connected to the power supply voltage VDD.

[0067] The positive input terminal of the operational amplifier is connected to the source terminal of PMOS transistor Q5, and its negative input terminal is connected to the source terminal of PMOS transistor Q6.

[0068] The input terminal of the current source I3 is connected to the gate terminal of the PMOS transistor Q6, and its output terminal is connected to ground GND.

[0069] The output currents of current sources I1 and I2 are the same, and the geometric dimensions of PMOS transistors Q5 and Q6 are identical. According to the current formula for MOS transistors:

[0070]

[0071] Where I is the output current of the MOSFET, μ is the electron mobility, and C... OX V is the gate oxide capacitance per unit area of ​​the MOSFET, W is the channel width of the MOSFET, L is the channel length of the MOSFET, and V is the gate oxide capacitance per unit area of ​​the MOSFET. GS It is the gate-source voltage difference of the MOSFET, V TH It is the threshold voltage for the turn-on of the MOSFET.

[0072] Therefore, the source voltage V of PMOS transistor Q5 S5 and the source voltage V of PMOS transistor Q6 S6 Equal, the gate voltage V of PMOS transistor Q5 G5 and the gate voltage V of PMOS transistor Q6 G6 equal.

[0073] Therefore, the drain-source voltage difference V of NMOS transistor Q4 can be obtained. DS4 Let ΔV be a fixed value, and under the action of the voltage clamping module, V DS4 It will hardly change, ensuring that the NMOS transistor Q4 operates in the linear region.

[0074] The gate voltage of NMOS transistor Q7 is the same as that of NMOS transistor Q2. By adjusting the dimensions of NMOS transistors Q7 and Q2, the drain voltage V of NMOS transistor Q7 can be made the same. S7 and the drain voltage V of NMOS transistor Q2 S2 Satisfy the following formula:

[0075] .

[0076] The voltage clamping module described above clamps the drain-source voltage of NMOS transistor Q4 to a fixed value ΔV, causing it to operate in the linear region, i.e., NMOS transistor Q4 is used as a linear resistor. As the input optical power of the photodiode PD increases, the gate voltage of NMOS transistor Q4 gradually increases under the control of the gain control module, and the gate-source voltage difference V of NMOS transistor Q4... GS As the resistance gradually increases, the equivalent linear resistance satisfies the following formula:

[0077]

[0078] In the formula, R ON It is the equivalent linear resistance of NMOS transistor Q4; μ is the electron mobility; C OX V is the gate oxide capacitance per unit area of ​​NMOS transistor Q4; W is the channel width of NMOS transistor Q4; L is the channel length of NMOS transistor Q4; V GS It is the gate-source voltage difference of NMOS transistor Q4, V TH It is the threshold voltage for the NMOS transistor Q4 to turn on.

[0079] The input terminal V of the gain control module IN2 Connect the source terminal of NMOS transistor Q3, and its input terminal V IN3 Connect the gate terminal of NMOS transistor Q1, and its output terminal V OUT2 Connect to the gate of NMOS transistor Q4.

[0080] The gain control module is used to adjust the gate voltage of NMOS transistor Q4 according to the change of input optical power, thereby changing its equivalent linear resistance and realizing continuous adjustment of transimpedance gain and elimination of DC offset.

[0081] like Figure 3 As shown, the gain control module includes PMOS transistor Q9 and PMOS transistor Q... 10Resistors R5, R6, and R7; current source I4 and I5; capacitors C2 and C3; and operational amplifier Amp2.

[0082] The gate terminal of PMOS transistor Q9 is the input terminal V of the gain control module. IN2 Its drain end is connected to ground GND.

[0083] PMOS transistor Q 10 The gate terminal is the input terminal V of the gain control module. IN3 Its drain is connected to ground GND, and its source is connected to the output of current source I5.

[0084] The input terminals of current source I4 and current source I5 are both connected to the supply voltage VDD.

[0085] The two ends of resistor R5 are connected to the source terminal of PMOS transistor Q9 and the output terminal of current source I4, respectively.

[0086] The two ends of resistor R6 are connected to the output terminal of current source I5 and the positive input terminal of operational amplifier Amp2, respectively.

[0087] The two ends of resistor R7 are connected to the output terminal of current source I4 and the negative input terminal of operational amplifier Amp2, respectively.

[0088] The two ends of capacitor C2 are connected to the positive input terminal of op-amp Amp2 and ground GND, respectively.

[0089] The two ends of capacitor C3 are connected to the negative input terminal and the output terminal of op-amp Amp2, respectively.

[0090] The output of op-amp Amp2 is also connected to the output of the gain control module V. OUT2 Connected.

[0091] The output currents of current source I4 and current source I5 are equal, resistors R6 and R7 are exactly the same, and capacitors C2 and C3 are exactly the same.

[0092] PMOS transistor Q9 and PMOS transistor Q 10 Their geometric dimensions are exactly the same, and the gate-source voltage difference V of PMOS transistor Q9 is the same. GS9 and PMOS transistor Q 10 Gate-source voltage difference V GS10 Equal; when the input optical power is 0, the source voltage difference V of PMOS transistor Q9 is equal. S9 and PMOS transistor Q 10 Source voltage V S10 equal.

[0093] Therefore, the equivalent linear resistance of NMOS transistor Q4 gradually decreases as the input optical power increases.

[0094] The gain control module detects and compares the voltage difference across resistor R1. Once the voltage difference exceeds a set threshold, the gain control module generates a control signal to increase the gate voltage of NMOS transistor Q4, thus eliminating DC offset. Specifically, resistor R5 sets the automatic gain control threshold voltage V. TH And V TH =I4 R5; When the input optical power is low, the voltage difference across resistor R1 should not exceed the threshold voltage V. TH When the input optical power is high, the output of operational amplifier Amp2 is 0, the gain control module is not activated, NMOS transistor Q4 is turned off, and the gain remains at its maximum value. When the input optical power increases, the voltage difference across resistor R1 can exceed the threshold voltage V. TH When the output of op-amp Amp2 increases, the gain control module is activated, NMOS transistor Q4 turns on, and the gain begins to decrease.

[0095] Therefore, the equivalent linear resistance of NMOS transistor Q4 decreases, and the input impedance of TIA also gradually decreases, thus achieving the adjustment of transimpedance gain.

[0096] As the input optical power increases, the transimpedance input voltage remains constant while the transimpedance output voltage decreases. Therefore, the voltage at the positive terminal of the op-amp remains constant while the voltage at the negative terminal of the op-amp continuously decreases until the voltage at the negative terminal of the op-amp is greater than the voltage at the positive terminal. At this point, the output voltage of the op-amp increases, controlling the NMOS transistor Q4 to turn on and draw DC current, thus eliminating DC offset.

[0097] Meanwhile, the presence of R5 provides the entire AGC circuit with an activation threshold, preventing it from turning on near the sensitivity threshold and affecting the system's sensitivity performance.

[0098] The curve of TIA gain versus input current Ipd_dc is as follows: Figure 4 As shown; In Figure 4 In the diagram, the horizontal axis represents the DC current output by the photodiode (PD), which is proportional to the input optical power; the vertical axis represents the gain of the multi-amplifier. Figure 4 The inflection point of the curve is the threshold voltage V. TH .

[0099] The drain-source voltage difference V of NMOS transistor Q4 DS4 The curve of the variation of input current Ipd_dc is as follows: Figure 5 As shown, after AGC is enabled, V DS4 It remains basically unchanged. Figure 5 In the diagram, the horizontal axis represents the DC current output by the photodiode PD, which is proportional to the input optical power, and the vertical axis represents the drain-source voltage difference of the NMOS transistor Q4.

[0100] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. An automatic gain control circuit for a transimpedance amplifier, characterized in that: Includes a basic TIA circuit, NMOS transistor Q4, voltage clamping module, and gain control module; The basic TIA circuit includes NMOS transistors Q1, Q2, Q3, resistors R1, R2, R3, R4, and capacitor C1; The gate of NMOS transistor Q1 is connected to photodiode PD, the drain of NMOS transistor Q1 is connected to the source of NMOS transistor Q2, and the drain of NMOS transistor Q2 is connected to the gate of NMOS transistor Q3. The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of the resistor R1; The drain of NMOS transistor Q2 and the supply voltage VDD are respectively connected to the two ends of resistor R2; The drain of NMOS transistor Q3 and the supply voltage VDD are respectively connected to the two ends of resistor R3; The source terminal of NMOS transistor Q3 and the ground line GND are respectively connected to the two ends of resistor R4; The gate terminal of NMOS transistor Q1 and the source terminal of NMOS transistor Q3 are respectively connected to the two ends of capacitor C1; The source terminal of NMOS transistor Q4 is connected to the drain terminal of NMOS transistor Q2, and the drain terminal of NMOS transistor Q4 is connected to the gate terminal of NMOS transistor Q1. The input terminal V of the voltage clamping module IN1 Connect the gate terminal of NMOS transistor Q1, and connect its output terminal to the gate terminal of NMOS transistor Q2; The input terminal V of the gain control module IN2 Connect the source terminal of NMOS transistor Q3, and its input terminal V IN3 Connect the gate terminal of NMOS transistor Q1, and its output terminal V OUT2 Connect to the gate of NMOS transistor Q4; The voltage clamping module is used to clamp the drain-source voltage of NMOS transistor Q4 to a fixed value, so that it operates in the linear region; The gain control module is used to adjust the gate voltage of NMOS transistor Q4 according to the change of input optical power, thereby changing its equivalent linear resistance and realizing continuous adjustment of transimpedance gain and elimination of DC offset.

2. The automatic gain control circuit for the transimpedance amplifier according to claim 1, characterized in that: The voltage clamping module includes PMOS transistors Q5, Q6, Q7, and Q8, current sources I1, I2, and I3, and operational amplifier Amp1. The gate terminal of PMOS transistor Q5 is the input terminal VIN1 of the voltage clamping module; the drain terminal of PMOS transistor Q5 is connected to ground GND; the source terminal of PMOS transistor Q5 is connected to the output terminal of current source I1; the input terminal of current source I1 is connected to the supply voltage VDD; the drain terminal of PMOS transistor Q6 is connected to ground GND; the source terminal of PMOS transistor Q6 is connected to the output terminal of current source I2; the input terminal of current source I2 is connected to the supply voltage VDD; the gate terminal of PMOS transistor Q6 is connected to the drain terminal of NMOS transistor Q7. The gate terminal of the NMOS transistor Q7 is connected to the output terminal of the operational amplifier; the drain terminal of the NMOS transistor Q7 is connected to the source terminal of the NMOS transistor Q8; the gate terminal and drain terminal of the NMOS transistor Q8 are connected to the power supply voltage VDD. The positive input terminal of the operational amplifier is connected to the source terminal of PMOS transistor Q5, and its negative input terminal is connected to the source terminal of PMOS transistor Q6. The input terminal of the current source I3 is connected to the gate terminal of the PMOS transistor Q6, and its output terminal is connected to ground GND.

3. The automatic gain control circuit for the transimpedance amplifier according to claim 2, characterized in that: The output current of current source I1 and current source I2 is the same.

4. The automatic gain control circuit for the transimpedance amplifier according to claim 3, characterized in that: The PMOS transistors Q5 and Q6 have identical geometric dimensions, and the source voltage V of PMOS transistor Q5 is the same. S5 and the source voltage V of PMOS transistor Q6 S6 Equal, the gate voltage V of PMOS transistor Q5 G5 and the gate voltage V of PMOS transistor Q6 G6 equal.

5. The automatic gain control circuit for the transimpedance amplifier according to claim 4, characterized in that: Let ΔV be the drain-source voltage difference of NMOS transistor Q4, and it be a fixed value. Then the gate voltage of NMOS transistor Q7 is the same as the gate voltage of NMOS transistor Q2. By adjusting the dimensions of NMOS transistors Q7 and Q2, the drain voltage V of NMOS transistor Q7 can be adjusted. S7 and the drain voltage V of NMOS transistor Q2 S2 Satisfy the following formula: 。 6. The automatic gain control circuit for the transimpedance amplifier according to claim 1, characterized in that: The gain control module includes PMOS transistor Q9, PMOS transistor Q 10 Resistors R5, R6, and R7; current source I4; current source I5; capacitors C2 and C3; and operational amplifier Amp2. The gate terminal of PMOS transistor Q9 is the input terminal V of the gain control module. IN2 Its drain end is connected to ground GND; PMOS transistor Q 10 The gate terminal is the input terminal V of the gain control module. IN3 Its drain is connected to ground GND, and its source is connected to the output of current source I5. The input terminals of current source I4 and current source I5 are both connected to the supply voltage VDD; The two ends of resistor R5 are connected to the source terminal of PMOS transistor Q9 and the output terminal of current source I4, respectively. The two ends of resistor R6 are connected to the output terminal of current source I5 and the positive input terminal of operational amplifier Amp2, respectively; The two ends of resistor R7 are connected to the output terminal of current source I4 and the negative input terminal of operational amplifier Amp2, respectively; The two ends of capacitor C2 are connected to the positive input terminal of operational amplifier Amp2 and ground GND, respectively; The two ends of capacitor C3 are connected to the negative input terminal and the output terminal of op-amp Amp2, respectively; The output of op-amp Amp2 is also connected to the output of the gain control module V. OUT2 Connected.

7. The automatic gain control circuit for the transimpedance amplifier according to claim 6, characterized in that: The output currents of current source I4 and current source I5 are equal, resistors R6 and R7 are exactly the same, and capacitors C2 and C3 are exactly the same.

8. The automatic gain control circuit for the transimpedance amplifier according to claim 7, characterized in that: PMOS transistor Q9 and PMOS transistor Q 10 Their geometric dimensions are exactly the same, and the gate-source voltage difference V of PMOS transistor Q9 is the same. GS9 and PMOS transistor Q 10 Gate-source voltage difference V GS10 Equal; when the input optical power is 0, the source voltage difference V of PMOS transistor Q9 is equal. S9 and PMOS transistor Q 10 Source voltage V S10 equal.

9. The automatic gain control circuit for the transimpedance amplifier according to claim 6, characterized in that: Resistor R5 can set the automatic gain control threshold voltage V. TH And V TH =I4 R5; When the input optical power is low, the voltage difference across resistor R1 should not exceed the threshold voltage V. TH When the input optical power is high, the output of operational amplifier Amp2 is 0, the gain control module is not activated, NMOS transistor Q4 is turned off, and the gain remains at its maximum value. When the input optical power increases, the voltage difference across resistor R1 can exceed the threshold voltage V. TH When the output of op-amp Amp2 increases, the gain control module is activated, NMOS transistor Q4 turns on, and the gain begins to decrease.

10. The automatic gain control circuit for the transimpedance amplifier according to claim 1, characterized in that: The equivalent linear resistance of NMOS transistor Q4 satisfies the following formula: ; In the formula, R ON It is the equivalent linear resistance of NMOS transistor Q4; μ is the electron mobility; C OX V is the gate oxide capacitance per unit area of ​​NMOS transistor Q4; W is the channel width of NMOS transistor Q4; L is the channel length of NMOS transistor Q4; V GS It is the gate-source voltage difference of NMOS transistor Q4, V TH It is the threshold voltage for the NMOS transistor Q4 to turn on.

Images