Semiconductor device and manufacturing method therefor, integrated circuit, and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a semiconductor device and a manufacturing method therefor, an integrated circuit, and an electronic device. The semiconductor device comprises a drift layer, a well layer, an emitter, a gate, a dummy gate, a first insulating film layer, and a second insulating film layer. A first trench and a second trench are formed in the well layer, the first trench and the second trench are spaced apart from each other, the well layer and the portion of the drift layer close to the well layer are arranged around the first trench and the second trench, and the side surface of the emitter close to the first trench serves as the inner wall of the first trench. The gate fills the first trench, and the dummy gate fills the second trench. The first insulating film layer is arranged between the gate and the inner wall of the first trench, and the second insulating film layer is arranged between the dummy gate and the inner wall of the second trench. The thickness of at least a portion of the second insulating film layer is greater than the thickness of the portion of the first insulating film layer in contact with a channel region. The semiconductor device has a small parasitic capacitance, a minimal voltage tailing issue, and low turn-on loss.

Description

Semiconductor devices and their fabrication methods, integrated circuits, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411377897.X, filed on September 29, 2024, entitled "Semiconductor Device and Preparation Method Thereof, Integrated Circuit, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a semiconductor device and its fabrication method, integrated circuits, and electronic devices. Background Technology

[0003] An insulated-gate bipolar transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated-gate field-effect transistor (MOSFET).

[0004] IGBTs include planar gate type and trench gate type. Compared with planar gate IGBTs, the channel in trench gate IGBTs changes from horizontal to vertical, which increases the carrier concentration on the emitter side and optimizes the hole flow path. This results in a lower on-state voltage drop and enhanced anti-latch-up capability, making trench gate IGBTs increasingly popular.

[0005] However, with the development of electronic equipment technology, the size of IGBTs has gradually been miniaturized, which has greatly affected the electrical performance of trench gate IGBTs. How to improve the electrical performance of trench gate IGBTs has become one of the technical problems that need to be solved. Summary of the Invention

[0006] This application provides a semiconductor device and its fabrication method, an integrated circuit, and an electronic device, with the aim of reducing the parasitic capacitance generated in the semiconductor device, thereby reducing the turn-on loss of the semiconductor device and improving its electrical performance.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, a semiconductor device is provided, the semiconductor device comprising a drift layer, a well layer, an emitter, a gate and a dummy gate, a first insulating film layer and a second insulating film layer.

[0009] The well layer is disposed on the drift layer, and the emitter is embedded in the well layer, extending from a first surface of the well layer into the well layer. The first surface is the surface of the well layer away from the drift layer. On one side of the first surface of the well layer, a first trench and a second trench are formed in a direction perpendicular to the first surface. The first trench and the second trench are spaced apart. The portions of the well layer and the drift layer near the well layer are arranged around the first trench and around the second trench, respectively. The side of the emitter near the first trench serves as the inner wall of the first trench. The gate is filled in the first trench, and a first insulating film layer is disposed between the gate and the inner wall of the first trench. A dummy gate is filled in the second trench, and a second insulating film layer is disposed between the dummy gate and the inner wall of the second trench.

[0010] Wherein, at least a portion of the thickness of the second insulating film layer is greater than the thickness of the portion of the first insulating film layer that contacts the channel region; the channel region is the portion of the well layer located between the emitter and the drift layer.

[0011] In the semiconductor device provided in this application embodiment, by setting at least a thin insulating film layer between the gate and the channel region, the channel region can quickly respond to gate control, thereby accelerating the turn-on rate and response speed of the semiconductor device. It can also improve input impedance, reduce device loss, and optimize the electrical performance of the semiconductor device. At the same time, setting at least a portion of the second insulating film layer to have a thicker thickness can increase the spacing between the dummy gate and the well layer, as well as between the dummy gate and the drift layer, thereby reducing parasitic capacitance. Thus, without affecting the gate control effect, the overall parasitic capacitance of the semiconductor device can be reduced, the tailing effect of the semiconductor device during the turn-on process can be reduced, thereby reducing the turn-on loss of the semiconductor device and optimizing its electrical performance.

[0012] In one possible implementation of the first aspect, the thickness of the first insulating film layer is the same at different positions on a cross section perpendicular to the second direction; the second direction is the length extension direction of the first trench and the second trench, and the second direction intersects the arrangement direction of the first trench and the second trench.

[0013] That is, the thickness of the first insulating film layer is the same at different locations on the same cross-section (a cross-section perpendicular to the length direction). For example, on the same cross-section, the portion of the first insulating film layer located at the bottom of the first trench has the same thickness as the portion located on the wall of the first trench. This allows for a more uniform distribution of charge carriers controlled by the gate near the inner wall of the first trench, resulting in a more uniform voltage or other factors (such as parasitic capacitance) at that location. This improves the controllability and product yield of the semiconductor device. Furthermore, it allows for the integral molding of the first insulating film layer, reducing the fabrication difficulty of the semiconductor device.

[0014] In one possible implementation of the first aspect, the average thickness of the second insulating film layer is greater than the average thickness of the first insulating film layer. This can reduce the parasitic capacitance between the dummy gate and the well layer, and between the dummy gate and the drift layer, without affecting the gate control effect of the gate. This reduces the overall parasitic capacitance of the semiconductor device, reduces the tailing effect of the semiconductor device during the turn-on process, and thus reduces the turn-on loss of the semiconductor device and optimizes its electrical performance.

[0015] In one possible implementation of the first aspect, a plurality of second trenches are spaced apart on one side of the first surface of the well layer in a direction perpendicular to the first surface. The thickness of the first insulating film layer is the same at different locations, and the thickness of the second insulating film layer in the same second trench is the same at different locations.

[0016] That is, the thickness of the first insulating film layer is uniformly set, and the thickness of the second insulating film layer is uniformly set. This can ensure that the various parameters around the gate are uniformly distributed, such as the uniform distribution of charge carriers and the relatively uniform voltage. It can also ensure that the various parameters around the dummy gate are uniformly distributed, such as the uniform distribution of parasitic capacitance, thereby improving the reliability of the semiconductor device. At the same time, the thickness of the second trench is designed to be greater than that of the first trench to reduce the parasitic capacitance of the semiconductor device.

[0017] In one possible implementation of the first aspect, the thickness of the second insulating layer in each second trench is greater than the thickness of the first insulating layer, thereby reducing the parasitic capacitance between the plurality of dummy gates and well layers, as well as between the dummy gates and drift layers, and further optimizing the electrical performance of the semiconductor device.

[0018] In one possible implementation of the first aspect, the thickness of the second insulating film layer in the multiple second trenches is the same, which facilitates the simultaneous preparation of the second insulating film layer in the multiple second trenches and reduces the preparation difficulty.

[0019] In a possible implementation of the first aspect, among a plurality of second trenches, the thickness of the second insulating film layer in the second trench adjacent to the first trench is the same as the thickness of the first insulating film layer; the thickness of the second insulating film layer in the second trench having at least one second trench spaced apart from the first trench is greater than the thickness of the first insulating film layer.

[0020] That is, the thickness of the second insulating film layer in the second trench near the first trench is small, and the thickness of the second insulating film layer in the second trench far away from the first trench is increased. In this way, while reducing the overall parasitic capacitance of the semiconductor device, the depth of the well layer that can be controlled by the gate is consistent. For example, the depth of the well layer between the first trench and the second trench is relatively uniform, thereby avoiding the impact of the increased thickness of the second insulating film layer on the gate control effect and improving the structural reliability of the semiconductor device.

[0021] In a possible implementation of the first aspect, the semiconductor device includes a plurality of emitters, which are sequentially spaced along a second direction, and each emitter is in contact with a first insulating film layer. The first insulating film layer includes a plurality of first sub-layers and a plurality of second sub-layers, which are alternately arranged along the second direction, with the first sub-layers in contact with the emitters. The second insulating film layer includes a plurality of third sub-layers and a plurality of fourth sub-layers, which are alternately arranged along the second direction; the third sub-layers and first sub-layers are arranged in a first direction, and the fourth and second sub-layers are arranged in a first direction; the first direction is the arrangement direction of the first trench and the second trench.

[0022] The first and third sublayers have the same thickness, the second and fourth sublayers have the same thickness, and the thickness of the second and fourth sublayers is greater than the thickness of the first and third sublayers.

[0023] This design facilitates the simultaneous fabrication of the first and third sublayers, as well as the simultaneous fabrication of the second and fourth sublayers. Specifically, insulating materials can be deposited sequentially along the second direction to form the first and second insulating film layers. This allows for the simultaneous fabrication of the non-gate-controlled portion of the first insulating film layer and the thicker portion of the second insulating film layer. Similarly, without affecting the gate control effect, it reduces the parasitic capacitance between the gate and the well layer or the gate and the drift layer, as well as the parasitic capacitance between the dummy gate and the well layer or the dummy gate and the drift layer, further reducing the overall parasitic capacitance of the semiconductor device and optimizing its electrical performance.

[0024] In a possible implementation of the first aspect, the first insulating film layer includes a plurality of first sub-layers, a plurality of second sub-layers, and a fifth sub-layer. The fifth sub-layer is disposed on the same side of the plurality of first sub-layers and the plurality of second sub-layers along a second direction, and at least one second sub-layer is spaced between the fifth sub-layer and the first sub-layers. The second insulating film layer includes a plurality of third sub-layers, a plurality of fourth sub-layers, and a sixth sub-layer. The sixth sub-layer is disposed on the same side of the plurality of third sub-layers and the plurality of fourth sub-layers along the second direction, and at least one fourth sub-layer is spaced between the sixth sub-layer and the third sub-layers. The sixth sub-layer and the fifth sub-layer are arranged in a first direction.

[0025] The first, second, third, and fourth sublayers have the same thickness, the fifth and sixth sublayers have the same thickness, and the thickness of the fifth and sixth sublayers is greater than the thickness of the first, second, third, and fourth sublayers.

[0026] This design facilitates the simultaneous fabrication of the first, second, third, and fourth sublayers, ensuring that the depth of the well layer near the gate is approximately the same at different locations. For example, the depth of the portion of the well layer used to form the channel is approximately the same as the depth of the portions located on both sides of the channel region along the second direction, thus avoiding the impact of different depths on the electrical performance of the channel region. Simultaneously, the simultaneous fabrication of the fifth and sixth sublayers reduces fabrication difficulty. Furthermore, without affecting the gate control effect, it reduces the parasitic capacitance between the gate and the well layer or between the gate and the drift layer, as well as the parasitic capacitance between the dummy gate and the well layer or between the dummy gate and the drift layer, further reducing the overall parasitic capacitance of the semiconductor device and optimizing its electrical performance.

[0027] In one possible implementation of the first aspect, at least a portion of the thickness of the second insulating film layer is 1.5 to 3 times the thickness of the portion of the first insulating film layer in contact with the channel region. By setting the thickness of the thicker portion of the insulating film layer (the first insulating film layer and the second insulating film layer) to be 1.5 to 3 times the thickness of the thinner portion, flexible control of the electrical performance in the semiconductor device can be achieved.

[0028] In one possible implementation of the first aspect, the dielectric constant of the second insulating layer is less than or equal to that of the first insulating layer. This allows for further reduction of the parasitic capacitance between the dummy gate and the well layer or between the gate and the drift layer without affecting the gate control performance, thereby reducing the overall parasitic capacitance of the semiconductor device, alleviating voltage tailing problems, and lowering the turn-on loss of the semiconductor device.

[0029] Secondly, a method for fabricating a semiconductor device is provided, the method comprising:

[0030] A first trench and a second trench are formed on one side surface of the semiconductor layer; the first trench and the second trench are spaced apart. A first insulating film layer and a second insulating film layer are formed; the first insulating film layer is located on the inner wall of the first trench, and the second insulating film layer is located on the inner wall of the second trench. A gate and a dummy gate are formed; the gate fills the first trench, and the dummy gate fills the second trench. The semiconductor layer is doped to form a drift layer, a well layer, and an emitter; the well layer is disposed on the drift layer; the emitter is embedded in the well layer, and the emitter extends from the surface of the well layer away from the drift layer into the well layer; the portions of the well layer and the drift layer near the well layer are disposed around the first trench and around the second trench, and the side of the emitter near the first trench serves as the inner wall of the first trench.

[0031] Wherein, at least a portion of the thickness of the second insulating film layer is at least greater than the thickness of the portion of the first insulating film layer in contact with the channel region; the channel region is the portion of the well layer located between the emitter and the drift layer.

[0032] The preparation method provided in this application embodiment can form a thicker second insulating film layer, so that the parasitic capacitance of the formed semiconductor device during the conduction process is smaller, the voltage tailing problem is alleviated, and its turn-on loss is effectively reduced.

[0033] In a possible implementation of the second aspect, forming the first insulating film layer and the second insulating film layer includes:

[0034] A protective layer is formed on the inner wall of the first trench. A first oxide layer is formed on the inner wall of the second trench. The protective layer is removed. A second oxide layer is formed on the inner wall of the first trench and on the first oxide layer; the portion of the second oxide layer on the inner wall of the first trench serves as a first insulating film layer, and the portion of the second oxide layer in the second trench, together with the first oxide layer, serves as a second insulating film layer.

[0035] That is, this embodiment allows the second insulating film layer to have two oxide layers (a first oxide layer and a second oxide layer), while the first insulating film layer has only one oxide layer (a second oxide layer). This ensures that the thickness of the second insulating film layer is greater than that of the first insulating film layer. As a result, the first insulating film layer that participates in gate control has a thinner thickness, thus ensuring the gate control effect, while the second insulating film layer that does not participate in gate control has a thicker thickness. This reduces the parasitic capacitance in the semiconductor device and optimizes its electrical performance.

[0036] Thirdly, an integrated circuit is provided, which includes electronic devices and semiconductor devices as provided in any of the embodiments of the first aspect above, wherein the electronic devices are electrically connected to the semiconductor devices.

[0037] Fourthly, an electronic device is provided, including a circuit board and a semiconductor device as provided in any of the embodiments of the first aspect above, or an integrated circuit as provided in the embodiments of the third aspect above, wherein the semiconductor device or integrated circuit is disposed on the circuit board.

[0038] The technological effects brought about by integrated circuits in the third aspect and by electronic devices in the fourth aspect can be found in the technological effects brought about by the structural design of semiconductor devices in the first aspect, and will not be repeated here. Attached Figure Description

[0039] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of this application;

[0040] Figure 2 is a schematic diagram of another structure of the electronic device provided in an embodiment of this application;

[0041] Figure 3 is a schematic diagram of a semiconductor device provided in an embodiment of this application;

[0042] Figure 4 is a top view of a semiconductor device provided in an embodiment of this application;

[0043] Figure 5 is a cross-sectional view along section line A-A' in Figure 4;

[0044] Figure 6 is a cross-sectional view along section line B-B' in Figure 4;

[0045] Figure 7 is another top view of the semiconductor device provided in the embodiment of this application;

[0046] Figure 8 is a cross-sectional view of the semiconductor device corresponding to Figure 7;

[0047] Figure 9 is another top view of the semiconductor device provided in the embodiment of this application;

[0048] Figure 10 is a cross-sectional view of the semiconductor device corresponding to Figure 9;

[0049] Figure 11 is a simulation analysis diagram of a semiconductor device provided in an embodiment of this application;

[0050] Figure 12 is another simulation analysis diagram of the semiconductor device provided in the embodiment of this application;

[0051] Figure 13 is another top view of the semiconductor device provided in the embodiment of this application;

[0052] Figure 14 is a cross-sectional view along section line C-C' in Figure 13;

[0053] Figure 15 is a cross-sectional view along section line D-D' in Figure 13;

[0054] Figure 16 is another top view of the semiconductor device provided in the embodiment of this application;

[0055] Figure 17 is a cross-sectional view along section line E-E' in Figure 16;

[0056] Figure 18 is a cross-sectional view along section line F-F' in Figure 16;

[0057] Figure 19 is another top view of the semiconductor device provided in the embodiment of this application;

[0058] Figure 20 is a cross-sectional view along section line H-H' in Figure 19;

[0059] Figure 21 is a cross-sectional view along section line I-I' in Figure 19;

[0060] Figures 22 and 23 are flowcharts illustrating the fabrication process of the semiconductor device provided in the embodiments of this application;

[0061] Figures 24 to 41 are cross-sectional views corresponding to each fabrication step of a semiconductor device. Detailed Implementation

[0062] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0063] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0064] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0065] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0066] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0067] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0068] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0069] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0070] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0071] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0072] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0073] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a power converter such as a boost-buck converter, an uninterruptible power supply (UPS) or other power conversion device, a charging device, or a photovoltaic power conversion device; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0074] Figures 1 and 2 are schematic diagrams of the structure of an electronic device provided by example in the embodiments of this application.

[0075] In some embodiments, as shown in FIG1, the electronic device 1000 may include an integrated circuit 100 and a circuit board 200, wherein the integrated circuit 100 may be disposed on the circuit board 200.

[0076] For example, circuit board 200 may be a printed circuit board (PCB).

[0077] It is understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1, or may combine some of the components shown in FIG1, or may have a different arrangement of components than those shown in FIG1.

[0078] This application also provides an integrated circuit 100.

[0079] For example, as shown in FIG1, the integrated circuit 100 may include logic circuit 101, analog circuit 102, storage circuit 103, and input / output circuit 104, etc.

[0080] It should be understood that integrated circuit 100 includes, but is not limited to, logic circuit 101, analog circuit 102, storage circuit 103 and input / output circuit 104. For example, in addition to the four types of circuits mentioned above, integrated circuit 100 may also include other types or functions of circuits, or discrete devices.

[0081] In addition, integrated circuit 100 may include one or more of logic circuit 101, analog circuit 102, storage circuit 103, and input / output circuit 104.

[0082] Based on this, the number of logic circuits 101, analog circuits 102, storage circuits 103, and input / output circuits 104 included in integrated circuit 100 can be set as needed. Integrated circuit 100 may include one or more logic circuits 101. Integrated circuit 100 may also include one or more analog circuits 102. Integrated circuit 100 may also include one or more storage circuits 103. Integrated circuit 100 may also include one or more input / output circuits 104.

[0083] As shown in Figure 1, the integrated circuit 100 may include a semiconductor device 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the semiconductor device 10.

[0084] For example, referring to FIG1, the semiconductor device 10 and the electronic device 20 can be integrated in the logic circuit 101. The semiconductor device 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to realize the "AND", "OR", "NOT" and other functions in the logic circuit 101.

[0085] Alternatively, by way of example, the semiconductor device 10 may also be integrated into other circuits, such as power integrated circuits. This application does not impose any specific limitations in this regard.

[0086] Alternatively, for example, the semiconductor device 10 can also be disposed as a discrete device in the integrated circuit 100. For example, the semiconductor device 10 can be integrated as a power device together with the logic circuit 101, analog circuit 102, etc. in the integrated circuit 100.

[0087] For example, electronic device 20 can be an electronic device such as a resistor or a capacitor.

[0088] In some other embodiments, as shown in FIG2, the electronic device 1000 may include a semiconductor device 10 and a circuit board 200, wherein the semiconductor device 10 is disposed on the circuit board 200.

[0089] That is, the semiconductor device 10 can be disposed independently on the circuit board 200 as a discrete device, or it can be integrated into the integrated circuit 100 and then disposed on the circuit board 200.

[0090] For example, referring to FIG2, the semiconductor device 10 disposed on the circuit board 200 as a discrete device can also be electrically connected to multiple electronic devices 20.

[0091] This application also provides a semiconductor device 10.

[0092] Figure 3 is a schematic diagram of the structure of the semiconductor device 10 provided in the embodiment of this application. Figure 4 is a top view of the semiconductor device 10 corresponding to Figure 3. Figure 5 is a cross-sectional view along the section line A-A' in Figure 4. Figure 6 is a cross-sectional view along the section line B-B' in Figure 4.

[0093] For example, the semiconductor device 10 can be an IGBT structure, or it can be a semiconductor device including an IGBT structure.

[0094] For example, the semiconductor device 10 can be a semiconductor device that integrates a diode and an IGBT structure, such as a reverse conduction IGBT (RC-IGBT).

[0095] The diodes may include freewheeling diodes (FWD) or fast recovery diodes (FRD).

[0096] For example, the IGBT structure in the semiconductor device 10 can be a non-punch-through IGBT (NPT-IGBT) or a field-stop IGBT (FS-IGBT).

[0097] As shown in Figure 3, the semiconductor device 10 may include a drift layer 2C, a well layer 2A, an emitter 2B, a gate 3, a dummy gate 4, a first insulating film layer 51, and a second insulating film layer 52.

[0098] The drift layer 2C is used to allow charge carriers (holes and electrons) to pass through. For example, electrons can be emitted from the emitter 2B located on one side of the drift layer 2C and flow into the drift layer 2C through the channel formed by the interface between the well layer 2A and the first insulating film layer 51. Then, they diffuse from the drift layer 2C to the injection layer 1 located on the other side of the drift layer 2C (see Figure 3), completing the current transfer in the semiconductor device 10. Charge carriers can also accumulate in the drift layer 2C (and the memory region 2E mentioned later), so that the drift layer 2C can participate in conductivity modulation during the conduction process of the semiconductor device 10, reducing the on-state voltage drop of the semiconductor device 10.

[0099] For example, the doping type of the drift layer 2C is different from that of the well layer 2A. For instance, the drift layer 2C is N-type doped.

[0100] For example, the doping concentration of the drift layer 2C is less than the doping concentration of the well layer 2A. For instance, the doping concentration of the drift layer 2C can be N-.

[0101] Referring to Figures 3, 5 and 6, the trap layer 2A can be disposed on the drift layer 2C.

[0102] The well layer 2A is used to form a channel under the control of the gate 3, thereby realizing the transfer of charge carriers between the emitter 2B and the injection layer 1, that is, realizing the current transfer of the semiconductor device 10.

[0103] For example, the doping type of the well layer 2A may be different from the doping type of the drift layer 2C. For instance, the doping type of the well layer 2A may be P-type doping.

[0104] Referring to Figures 3 and 5, the emitter 2B is embedded in the well layer 2A, and the emitter 2B extends from the first surface of the well layer 2A into the well layer 2A, wherein the first surface is the surface of the well layer 2A that is away from the drift layer 2C.

[0105] The emitter 2B is used to generate charge carriers. For example, when the semiconductor device 10 is turned on, the emitter 2B can generate electrons, which flow from the emitter 2B through the well layer 2A, the drift layer 2C, and finally to the injection layer 1, thereby generating a current.

[0106] For example, an emitter 2B can be formed by locally implanting impurities (e.g., N-type impurities) into the well layer 2A using ion implantation.

[0107] For example, the doping type of the emitter 2B is different from the doping type of the well layer 2A. For instance, the emitter 2B can be N-type doped.

[0108] For example, the doping concentration of the emitter 2B is greater than the doping concentration of the well layer 2A. For instance, the doping concentration of the emitter 2B can be N+.

[0109] For example, the embodiments of this application do not impose restrictions on the position of the emitter 2B embedded in the well layer 2A. For example, referring to FIG5, the emitter 2B may be embedded only in the portion of the well layer 2A near the first trench U1, or for example, referring to FIG8, the emitter 2B may extend from the first trench U1 to the second trench U2.

[0110] For example, the aforementioned drift layer 2C, well layer 2A and emitter 2B can be integrally formed. For example, referring to FIG3, the drift layer 2C, well layer 2A and emitter 2B can be different parts of the semiconductor layer 2. For example, ion implantation can be performed at different positions of the semiconductor layer 2 to obtain the drift layer 2C, well layer 2A and emitter 2B.

[0111] For example, referring to FIG3, the semiconductor layer 2 is disposed on the implantation layer 1.

[0112] For example, the material of the semiconductor layer 2 is a semiconductor material.

[0113] For example, the method of forming semiconductor layer 2 may include metal-organic chemical vapor deposition (MOCVD) growth method or molecular beam epitaxy (MBE) growth method, etc.

[0114] For example, the semiconductor layer 2 can be grown directly on the implantation layer 1, or the semiconductor layer 2 can be formed on the substrate first, and then the substrate can be thinned and impurities can be implanted to form the implantation layer 1, or other implementation methods can be used, which are not limited in this application.

[0115] In addition to the semiconductor layer 2 including the drift layer 2C, the well layer 2A and the emitter 2B, the semiconductor layer 2 may also include other regions in order to achieve better current transmission performance of the semiconductor device 10.

[0116] For example, referring to Figures 3, 5 and 6, the semiconductor layer 2 may also include a buffer 2D located between the drift layer 2C and the injection layer 1, which can buffer the carriers flowing through the drift layer 2C, thereby reducing the on-state voltage drop and power consumption of the semiconductor device 10.

[0117] For example, the doping type of buffer 2D is the same as that of drift layer 2C.

[0118] For example, the doping concentration of buffer 2D is greater than the doping concentration of drift layer 2C. For instance, the doping concentration of buffer 2D can be N.

[0119] For example, referring to Figures 3, 5 and 6, the semiconductor layer 2 may further include a storage region 2E disposed between the well layer 2A and the drift layer 2C. The N-type doped storage region 2E is used to form a hole barrier to prevent holes from being rapidly drawn away by the emitter electrode 7 (see Figure 8) when the semiconductor device 10 is turned on, thereby improving the injection efficiency of the drift layer 2C on the side near the emitter electrode 7.

[0120] For example, the doping type of storage region 2E is the same as that of drift layer 2C.

[0121] For example, the doping concentration of storage region 2E is greater than the doping concentration of drift layer 2C. For instance, the doping concentration of storage region 2E can be N.

[0122] For example, referring to Figures 3, 5 and 6, the semiconductor device 10 may also include an injection layer 1 disposed on the side of the drift layer 2C away from the well layer 2A.

[0123] The injection layer 1 is used to generate charge carriers. For example, when the semiconductor device 10 is turned on, the injection layer 1 can generate holes, which flow from the injection layer 1 to the side of the drift layer 2C in the semiconductor device 10 away from the injection layer 1, thereby generating current.

[0124] For example, the material of the implantation layer 1 is a semiconductor material.

[0125] For example, the doping type of the implanted layer 1 is different from that of the drift layer 2C, so that a PN junction is formed between the implanted layer 1 and the drift layer 2C. For example, the implanted layer 1 can be P-type doped.

[0126] For example, the doping concentration of the injection layer 1 is greater than that of the drift layer 2C, thereby facilitating the flow of charge carriers (e.g., holes) from the injection layer 1 to the drift layer 2C. For example, the doping concentration of the injection layer 1 can be P, or it can be P+.

[0127] In the embodiments of this application, P or P+ indicates that holes are the majority carriers, and N-, N+, or N++ indicates that electrons are the majority carriers. Furthermore, a "+" marked on N or P indicates a higher doping concentration than the unmarked structure, and a "-" marked on N or P indicates a lower doping concentration than the unmarked structure. It can be understood that more "+" signs indicate a higher doping concentration, and similarly, more "-" signs indicate a lower doping concentration.

[0128] Figure 7 is another top view of the semiconductor device 10 provided in the embodiment of this application, Figure 8 is a cross-sectional view of the semiconductor device 10 corresponding to Figure 7, Figure 9 is another top view of the semiconductor device 10 provided in the embodiment of this application, and Figure 10 is a cross-sectional view of the semiconductor device 10 corresponding to Figure 9.

[0129] For example, referring to Figures 8 and 10, the semiconductor device 10 may further include a collector 6, which is disposed on the side of the injection layer 1 away from the drift layer 2C and in contact with the injection layer 1. The collector 6 serves as a conductive terminal of the semiconductor device 10 for connecting to an external power source. The collector 6 can collect charge carriers (e.g., electrons) in the semiconductor device 10, thereby enabling the semiconductor device 10 to participate in the current transport process.

[0130] The implanted layer 1 with a high doping concentration can form a good ohmic contact with the collector 6, thereby reducing the turn-on loss of the semiconductor device 10 and improving the electrical performance of the semiconductor device 10.

[0131] Referring, as exemplarily to Figures 8 and 10, the semiconductor device 10 may further include an emitter electrode 7, which is disposed on the side of the semiconductor layer 2 away from the implantation layer 1 and is in contact with the emitter 2B. The emitter electrode 7 serves as another conductive terminal of the semiconductor device 10, used to connect to an external power source so that electrons can be generated at the emitter 2B, thereby forming a current in the semiconductor device 10 and ultimately forming a current path with the collector 6, thus realizing current transmission in the semiconductor device 10.

[0132] The emitter 2B with a high doping concentration can form a good ohmic contact with the emitter electrode 7, thereby reducing the turn-on loss of the semiconductor device 10 and improving the electrical performance of the semiconductor device 10.

[0133] For example, the emitter electrode 7 can be in planar contact with the semiconductor layer 2 (e.g., the well layer 2A in the semiconductor layer 2). For example, similar to the contact between the implantation layer 1 and the semiconductor layer 2, the emitter electrode 7 can also be laid on the surface of the semiconductor layer 2, thereby contacting the emitter 2B in the semiconductor layer 2.

[0134] Alternatively, as exemplarily provided in Figures 8 and 10, the emitter electrode 7 may also be embedded in the semiconductor layer 2 (e.g., the well layer 2A in the semiconductor layer 2) and in contact with the semiconductor layer 2. For example, as exemplarily provided in Figures 8 and 10, a groove K may be formed on the surface of the side where the emitter 2B is located. The groove K exposes at least the side of the emitter 2B and a portion of the surface of the well layer 2A. At least a portion of the emitter electrode 7 is embedded in the groove K so as to contact the emitter 2B and the well layer 2A.

[0135] For example, the emitter electrode 7 can be disposed in a local area of ​​the surface of the semiconductor layer 2. For example, the emitter electrode 7 can be disposed only in the area where the emitter 2B of the semiconductor layer 2 is located. Or, for example, referring to FIG8 and FIG10, the emitter electrode 7 can completely cover the surface of the semiconductor layer 2 (e.g., the upper surface in FIG8). Any arrangement that enables the emitter electrode 7 to contact the emitter 2B is within the protection scope of the embodiments of this application, and the embodiments of this application do not limit it.

[0136] For example, referring to Figures 8 and 10, the emitter electrode 7 is also in contact with the well layer 2A in the semiconductor layer 2 so that holes located in the well layer 2A can be extracted from the emitter electrode 7 during the turn-off process of the semiconductor device 10.

[0137] For example, referring to Figures 7, 8, 9 and 10, the well layer 2A may further include a contact region 2A', the doping type of the contact region 2A' is the same as that of the well layer 2A, and the doping concentration of the contact region 2A' is greater than that of the well layer 2A. For example, the doping concentration of the well layer 2A may be P, and the doping concentration of the contact region 2A' may be P+.

[0138] Referring to Figures 8 and 10, the well layer 2A is in contact with the emitter electrode 7 through the contact region 2A'. By setting the contact region 2A' with a high doping concentration, an ohmic contact can be formed between the well layer 2A and the emitter electrode 7, so that during the turn-off process of the semiconductor device 10, the holes accumulated in the well layer 2A can be quickly discharged through the emitter electrode 7.

[0139] For example, referring to Figures 8 and 10, when the semiconductor layer 2 is provided with a groove K, the contact area 2A' can be provided on the inner wall of the groove K.

[0140] For example, referring to Figures 7 and 8, the groove K is at least disposed between the first groove U1 and the second groove U2 disposed adjacent to the first groove U1, and the groove K exposes the side of the emitter 2B. The contact area 2A' can be disposed at the bottom of the groove K. At least a portion of the emitter electrode 7 is filled in the groove K and contacts the side of the emitter 2B and the contact area 2A' at the bottom of the groove K, respectively.

[0141] Alternatively, as exemplarily provided in Figures 9 and 10, the groove K can also be disposed on both sides of the second trench U2. In a semiconductor device 10 with a high integration density, distributing the groove K on both sides of the second trench U2 allows the groove K to be etched with the side of the second trench U2 as the boundary, thereby reducing the width of the groove K and ensuring that the emitter 2B near the first trench U1 has sufficient area.

[0142] For example, referring to Figures 8 and 10, the semiconductor device 10 may also include a dielectric layer 8, which is disposed at least between the gate 3 and the emitter electrode 7 to avoid the problem that the potential of the gate 3 and the potential of the emitter electrode 7 (i.e. the potential of the emitter 2B) are the same, which would prevent the device from conducting.

[0143] For example, referring to FIG10, the dielectric layer 8 may also be disposed between the dummy gate 4 and the emitter electrode 7 to achieve electrical insulation between the dummy gate 4 and the emitter electrode 7.

[0144] Referring to Figure 3, on one side of the first surface of the trap layer 2A, a first groove U1 and a second groove U2 are formed in a direction perpendicular to the first surface, and the first groove U1 and the second groove U2 are arranged at intervals.

[0145] Referring to Figures 3, 4, 5 and 6, the first trench U1 and the second trench U2 are arranged at intervals along a first direction X, which is parallel to the injection layer 1.

[0146] For example, referring to Figures 3, 4, 5 and 6, both the first trench U1 and the second trench U2 can be strip-shaped, with their length extending along the second direction Y, which is parallel to the injection layer 1, and the first direction X and the second direction Y intersect each other, for example, they are perpendicular to each other.

[0147] For example, referring to Figures 3, 4, 5 and 6, the depth direction of the first trench U1 and the second trench U2 is a third direction X, which can be perpendicular to both the first direction X and the second direction Y.

[0148] Referring to Figures 3 and 5, the portions of the well layer 2A and the drift layer 2C near the well layer 2A are arranged around the first trench U1 and around the second trench U2, and the side of the emitter 2B near the first trench U1 serves as the inner wall of the first trench U1.

[0149] That is, the first trench U1 passes through the emitter 2B and the well layer 2A and extends into the interior of the drift layer 2C, and the second trench U2 passes through the well layer 2A and extends into the interior of the drift layer 2C.

[0150] Referring to Figures 3 and 5, at least a portion of the sidewall of the first trench U1 belongs to the emitter 2B and at least a portion belongs to the well layer 2A, thereby facilitating the formation of a channel near the sidewall of the first trench U1. At least a portion of the sidewall of the second trench U2 belongs to the well layer 2A, but the second trench U2 does not necessarily have to penetrate the emitter 2B, that is, no channel needs to be formed near the sidewall of the second trench U2.

[0151] That is, the first trench U1 is used to form a transistor structure, while the second trench U2 is not used to form a transistor structure. For example, the second trench U2 can be used to form an isolation structure in order to achieve isolation between two adjacent transistor structures.

[0152] For example, the semiconductor device 10 may also be provided with a plurality of first trenches U1 to facilitate the formation of a plurality of transistor structures.

[0153] For example, among the plurality of first trenches U1, at least one second trench U2 may be provided between at least one pair of adjacent first trenches U1 so that the transistor structure formed by the at least one pair of first trenches U1 can be isolated by the isolation structure formed by the second trench U2, thereby reducing the distribution density of the first trenches U1 (or transistors) and enhancing the short-circuit characteristics of the semiconductor device 10.

[0154] It is understood that the accompanying drawings corresponding to the embodiments of this application only illustrate the structure of the semiconductor device 10 by way of one first trench U1 and two second trenches U2, and do not limit the number of first trenches U1 and the number of second trenches U2 in the semiconductor device 10.

[0155] Referring to Figures 3, 4, 5 and 6, the gate 3 is filled in the first trench U1 and the dummy gate 4 is filled in the second trench U2.

[0156] The gate 3 serves as a control terminal for the semiconductor device 10, used to transmit a gate signal to the semiconductor device 10 in order to control the formation of a channel near the sidewall of the first trench U1 (e.g., in the portion of the well layer 2A belonging to the sidewall of the first trench U1), thereby realizing the conduction between the emitter electrode 7 and the collector electrode 6, that is, realizing the circuit conduction of the semiconductor device 10.

[0157] It can be understood that the portion of the well layer 2A located between the emitter 2B and the drift layer 2C and close to the gate 3 can form a channel under the control of the gate 3, that is, this portion can serve as the channel region 2' of the semiconductor device 10.

[0158] The pseudo-gate 4 fills the second trench U2, but it cannot control the formation of trenches in the well layer 2A.

[0159] For example, both the gate 3 and the dummy gate 4 can be made of metal or alloy.

[0160] For example, gate 3 and pseudo gate 4 can be integrally formed, and both can be made of the same material.

[0161] For example, the dummy gate 4 can be conductive. For instance, the dummy gate 4 can be electrically connected to the emitter electrode 7 (not shown in the figure). For instance, the dielectric layer 8 may not be provided between the dummy gate 4 and the emitter electrode 7. Alternatively, the emitter electrode 7 can penetrate the dielectric layer 8 and be electrically connected to the dummy gate 4, thereby making the dummy gate 4 and the emitter electrode 7 have the same potential, which serves to fix the potential.

[0162] Alternatively, for example, the dummy gate 4 can also be electrically connected to the gate 3 (not shown) to adjust the gate junction capacitance of the semiconductor device 10.

[0163] For example, when the dummy gate 4 is electrically connected to the emitter electrode 7, the second trench U2 can also penetrate the emitter 2B (see Figures 7 and 8, where the emitter 2B is also arranged around the dummy gate 4).

[0164] When the dummy gate 4 is electrically connected to the emitter electrode 7, the dummy gate 4 and the emitter electrode 7 have the same potential. Therefore, no voltage difference will be generated between the dummy gate 4 and the emitter electrode 7. That is, no channel will be formed in the well layer 2A near the dummy gate 4. Therefore, regardless of whether the emitter 2B is provided near the dummy gate 4, the dummy gate 4 will not form a transistor. Therefore, in this embodiment, the second trench U2 can penetrate the emitter 2B.

[0165] For example, when the dummy gate 4 is electrically connected to the gate 3, the second trench U2 only penetrates the well layer 2A, that is, the emitter 2B is disposed away from the dummy gate 4 (refer to FIG. 5, there is no emitter 2B disposed around the dummy gate 4).

[0166] When the dummy gate 4 is electrically connected to the gate 3, the dummy gate 4 shares the gate potential. There is a voltage difference between the dummy gate 4 and the emitter electrode 7. If the emitter 2B is provided on the sidewall of the second trench U2, a voltage difference will be formed between the emitter 2B, which is electrically connected to the emitter electrode 7, and the dummy gate 4. This will cause the well layer 2A to form a channel under the influence of the dummy gate 4 and the emitter 2B, so that the function of the dummy gate 4 is equivalent to that of the gate 3, and it cannot play the role of reducing the distribution density of the transistor structure. Therefore, in this embodiment, the emitter 2B is set to avoid the dummy gate 4.

[0167] Referring to Figures 3, 4, 5 and 6, the first insulating film layer 51 is disposed between the gate 3 and the inner wall of the first trench U1, and the second insulating film layer 52 is disposed between the dummy gate 4 and the inner wall of the second trench U2.

[0168] The first insulating film layer 51 is used to achieve electrical insulation between the gate 3 and the semiconductor layer 2 (e.g., between the gate 3 and the well layer 2A, between the gate 3 and the emitter 2B, and between the gate 3 and the drift layer 2C), thereby preventing the gate 3 from being directly electrically connected to the semiconductor layer 2, so that the gate 3 can be controlled to form a channel in the well layer 2A.

[0169] The second insulating film layer 52 is used to achieve electrical insulation between the dummy gate 4 and the semiconductor layer 2 (e.g., between the dummy gate 4 and the well layer 2A, and between the dummy gate 4 and the drift layer 2C), thereby preventing the electrical connection between the conductive dummy gate 4 and the semiconductor layer 2 from affecting the control of the gate 3.

[0170] For example, the materials of the first insulating film layer 51 and the second insulating film layer 52 are both electrically insulating. For example, the materials of both may include insulating oxides, or they may also include materials with high dielectric constants.

[0171] Referring to Figures 3, 4, 5 and 6, the thickness of at least a portion of the second insulating film layer 52 is at least greater than the thickness of the portion of the first insulating film layer 51 that contacts the channel region 2'.

[0172] That is, at least the insulating film layer between the gate 3 and the channel region 2' has a relatively thin thickness, while part or even all of the second insulating film layer 52 has a relatively thick thickness.

[0173] Wherein, the thickness of the first insulating film layer 51 is the dimension of the first insulating film layer 51 in the direction perpendicular to the inner wall of the first trench U1, and the thickness of the second insulating film layer 52 is the dimension of the second insulating film layer 52 in the direction perpendicular to the inner wall of the second trench U2. That is, the insulating film layers (the first insulating film layer 51 and the second insulating film layer 52) are thin films, and the insulating film layers are laid along the inner wall of the trench (the first trench U1 and the second trench U2). The thickness of the target part of the insulating film layer is the dimension of the insulating film layer in the direction perpendicular to the inner wall of the trench where the target part is set. For example, the thickness of the part of the first insulating film layer 51 that contacts the channel region 2' can be the dimension of the first insulating film layer 51 in the direction perpendicular to the inner wall of the first trench U1 formed by the channel region 2'.

[0174] In the semiconductor device 10 provided in this application embodiment, by providing an insulating film layer with a relatively thin or normal thickness between at least the gate 3 and the channel region 2', the channel region 2' of the well layer 2A can quickly respond to the control of the gate 3, thereby accelerating or maintaining the turn-on rate and response speed of the semiconductor device 10, thereby reducing device losses and optimizing the electrical performance of the semiconductor device 10. At the same time, by providing at least a portion of the second insulating film layer 52 with a relatively thick thickness, the spacing between the dummy gate 4 and the semiconductor layer 2 can be increased, and the parasitic capacitance between the gate and the dummy gate (emitter), and between the collector and the dummy gate can be reduced. This increases the gate control effect of the gate 3 while reducing the overall parasitic capacitance of the semiconductor device 10, reducing the tailing effect of the semiconductor device 10 during the turn-on process, thereby reducing the turn-on loss of the semiconductor device 10 and optimizing its electrical performance.

[0175] The electrical performance of the semiconductor device 10 provided in the embodiments of this application will be analyzed below.

[0176] Figures 11 and 12 are simulation analysis diagrams of the semiconductor device 10 provided in the embodiments of this application, and Table 1 is a summary of the simulation results of the semiconductor device 10.

[0177] Table 1:

[0178] In Figure 11, VGE refers to the voltage between the gate 3 and the emitter electrode 7, Ig refers to the current of the gate 3, I (pseudo-gate) refers to the current flowing through the pseudo-gate 4 during the turn-on process of the semiconductor device 10, ICE refers to the current between the collector 6 and the emitter electrode 7, and VCE refers to the voltage between the collector 6 and the emitter electrode 7. Referring to Figure 11, stage t0 is the charging period of the gate 3, and the change of the charging charge of the pseudo-gate 4 during this stage can be obtained from the I (pseudo-gate) curve. In stage t1, the charging charge of the capacitor formed between the collector 6 and the pseudo-gate 4 can be reflected.

[0179] As shown in Figure 12, as the thickness of the second insulating film layer 52 in the semiconductor device 10 is increased (100nm→400nm) in this embodiment, the slope of the curve corresponding to the voltage between the collector 6 and the emitter 7 of the semiconductor device 10 (VCE in Figure 12) gradually increases. That is, the VCE curve gradually approaches the ideal curve in Figure 11, effectively alleviating the voltage tailing problem in the semiconductor device 10. Referring to Figure 12, as the thickness of the second insulating film layer 52 increases, the current curve between the collector 6 and the emitter 7 (ICE in Figure 12) and the voltage curve between the gate 3 and the emitter 7 (VGE in Figure 12) are both corrected. That is, these values ​​gradually tend towards the ideal values, effectively improving the electrical performance of the semiconductor device 10.

[0180] As shown in Table 1, corresponding to the simulation curve in Figure 12, as the thickness of the second insulating film layer 52 increases, the charge between the collector 6 and the pseudo gate 4 gradually decreases, that is, the parasitic capacitance gradually decreases, thereby gradually reducing the turn-on loss of the semiconductor device 10 and lowering the Eon ratio, that is, increasing the performance and efficiency of the semiconductor device 10.

[0181] In some embodiments, as shown in Figures 3, 5 and 6, the thickness of the first insulating film layer 51 is the same at different locations on a cross section (i.e., the XZ section) perpendicular to the second direction Y.

[0182] That is, the thickness of the first insulating film layer 51 is the same at different locations on the same cross section (XZ section). For example, on an XZ section, the portion of the first insulating film layer 51 located at the bottom of the first trench U1 has the same thickness as the portion of the first insulating film layer 51 located on the wall of the first trench U1. This allows for a more uniform distribution of the charge carriers controlled by the gate 3 near the inner wall of the first trench U1, resulting in a more uniform voltage or other factors (such as parasitic capacitance) at that location. This improves the controllability and product yield of the semiconductor device 10. Furthermore, it allows for the integral molding of the first insulating film layer 51, reducing the fabrication difficulty of the semiconductor device 10.

[0183] Figure 13 is another top view of the semiconductor device 10 provided in the embodiment of this application, Figure 14 is a cross-sectional view along section line C-C' in Figure 13, and Figure 15 is a cross-sectional view along section line D-D' in Figure 13.

[0184] In some embodiments, as shown in Figures 4, 5, 6, 13, 14, and 15, the average thickness of the second insulating film layer 52 is greater than the average thickness of the first insulating film layer 51. This allows for the reduction of parasitic capacitance between the dummy gate 4 and the semiconductor layer 2 or the implantation layer 1 without affecting the gate control effect of the gate 3. This reduces the overall parasitic capacitance of the semiconductor device 10, decreases the tailing effect of the semiconductor device 10 during the turn-on process, reduces the turn-on loss of the semiconductor device 10, and optimizes its electrical performance.

[0185] For example, the thickness of the first insulating film layer 51 at different locations may not be uniform, and the thickness of the second insulating film layer 52 at different locations may also not be uniform. However, the average thickness of the second insulating film layer 52 is greater than the average thickness of the first insulating film layer 51. Thus, without affecting the gate control effect of the gate 3, the parasitic capacitance between the pseudo gate 4 and the semiconductor layer 2 is reduced, thereby reducing the overall parasitic capacitance of the semiconductor device 10 and optimizing the electrical performance of the semiconductor device 10.

[0186] Or, for example, referring to Figures 4, 5, 6, 13, 14 and 15, the thickness of the first insulating film layer 51 is the same at different locations, the thickness of the second insulating film layer 52 in the same second trench U2 is the same at different locations, and the thickness of the second trench U2 is greater than the thickness of the first trench U1.

[0187] That is, the thickness of the first insulating film layer 51 is uniformly set, and the thickness of the second insulating film layer 52 is uniformly set. This can ensure that the various parameters around the gate 3 are uniformly distributed, such as the uniform distribution of charge carriers and the relatively uniform voltage. It can also ensure that the various parameters around the pseudo gate 4 are uniformly distributed, such as the uniform distribution of parasitic capacitance, thereby improving the reliability of the semiconductor device 10. At the same time, the thickness of the second trench U2 is designed to be greater than the thickness of the first trench U1, thereby reducing the parasitic capacitance of the semiconductor device 10.

[0188] In some embodiments, referring to Figures 4, 5, 6, 13, 14 and 15, the semiconductor device 10 includes a plurality of dummy gates 4, that is, on one side of the first surface of the well layer 2A, a plurality of spaced second trenches U2 are formed in a direction perpendicular to the first surface, and a second insulating film layer 52 is disposed on the inner wall of the plurality of second trenches U2.

[0189] For example, as shown in Figures 4, 5 and 6, the thickness of the second insulating film layer 52 in each second trench U2 is greater than the thickness of the first insulating film layer 51, thereby reducing the parasitic capacitance between the plurality of dummy gates 4 and the semiconductor layer 2, and further optimizing the electrical performance of the semiconductor device 10.

[0190] For example, as shown in Figures 4, 5 and 6, the second insulating film layer 52 in the plurality of second trenches U2 has the same thickness, which facilitates the synchronous preparation of the second insulating film layer 52 in the plurality of second trenches U2 and reduces the preparation difficulty.

[0191] For example, as shown in Figures 13, 14 and 15, in a plurality of second trenches U2, the thickness of the second insulating film layer 52 in the second trench U2 adjacent to the first trench U1 is the same as the thickness of the first insulating film layer 51, and the thickness of the second insulating film layer 52 in the second trench U2 that is spaced apart from the first trench U1 is greater than the thickness of the first insulating film layer 51.

[0192] That is, the thickness of the second insulating film layer 52 in the second trench U2 near the first trench U1 is small, and the thickness of the second insulating film layer 52 in the second trench U2 far away from the first trench U1 is increased. In this way, while reducing the overall parasitic capacitance of the semiconductor device 10, the depth of each region in the semiconductor layer 2 portion that the gate 3 can control (e.g., the portion of the semiconductor layer 2 between the first trench U1 and the second trench U2) is the same. For example, the depth of the well layer 2A is relatively uniform, thereby avoiding the impact of the increased thickness of the second insulating film layer 52 on the gate control effect of the gate 3 and improving the structural reliability of the semiconductor device 10.

[0193] Figure 16 is another top view of the semiconductor device 10 provided in the embodiment of this application, Figure 17 is a cross-sectional view along section line E-E' in Figure 16, and Figure 18 is a cross-sectional view along section line F-F' in Figure 16.

[0194] In some embodiments, as shown in FIG16, the semiconductor device 10 includes a plurality of emitters 2B, which are arranged sequentially at intervals along the second direction Y, and all emitters 2B are in contact with the first insulating film layer 51.

[0195] Each emitter 2B can be used to form a transistor structure.

[0196] It is understandable that the portion of the well layer 2A located between two adjacent emitters 2B does not belong to the channel region 2', does not generate a channel, and is not involved in the current transport process of the semiconductor device 10.

[0197] Referring to Figure 16, the first insulating film layer 51 includes a plurality of first sub-layers 511 and a plurality of second sub-layers 512. The plurality of first sub-layers 511 and the plurality of second sub-layers 512 are alternately arranged along the second direction Y. The first sub-layers 511 are in contact with the emitter 2B. That is, the first sub-layers 511 are the portion of the corresponding channel region 2' of the first insulating film layer 51, and the second sub-layers 512 are the portions of the first insulating film layer 51 that do not participate in current transmission.

[0198] For example, referring to FIG16, the thickness of the second sub-layer 512 can be greater than the thickness of the first sub-layer 511. That is, in the first insulating film layer 51, the part that participates in gate control is thinner and the part that does not participate in gate control is thicker. Similarly, without affecting the gate control effect of the gate 3, the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the implantation layer 1 can be reduced, thereby reducing the overall parasitic capacitance of the semiconductor device 10, reducing the tailing effect of the semiconductor device 10 during the turn-on process, thereby reducing the turn-on loss of the semiconductor device 10 and optimizing its electrical performance.

[0199] Referring to Figure 16, the second insulating film layer 52 includes a plurality of third sub-layers 521 and a plurality of fourth sub-layers 522. The plurality of third sub-layers 521 and the plurality of fourth sub-layers 522 are alternately arranged along the second direction Y. The third sub-layers 521 and the first sub-layer 511 are arranged in the first direction X. The fourth sub-layers 522 and the second sub-layers 512 are arranged in the first direction X.

[0200] That is, the third sub-layer 521 is the part of the second insulating film layer 52 that corresponds to the first sub-layer 511 of the first insulating film layer 51, and the fourth sub-layer 522 is the part of the second insulating film layer 52 that corresponds to the second sub-layer 512 of the first insulating film layer 51.

[0201] For example, referring to FIG17, the first sublayer 511 and the third sublayer 521 have the same thickness; referring to FIG18, the second sublayer 512 and the fourth sublayer 522 have the same thickness; referring to FIG16, or comparing FIG17 and FIG18, the thickness of the second sublayer 512 and the fourth sublayer 522 is greater than the thickness of the first sublayer 511 and the third sublayer 521.

[0202] This design facilitates the simultaneous fabrication of the first sublayer 511 and the third sublayer 521, as well as the simultaneous fabrication of the second sublayer 512 and the fourth sublayer 522. Specifically, insulating materials can be deposited sequentially along the second direction Y to form the first insulating film layer 51 and the second insulating film layer 52. This allows for the simultaneous fabrication of the portion of the first insulating film layer 51 that does not participate in gate control, and the thicker portion of the second insulating film layer 52. Similarly, without affecting the gate control effect of the gate 3, it reduces the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the implantation layer 1, and also reduces the parasitic capacitance between the dummy gate 4 and the semiconductor layer 2 or the implantation layer 1, further reducing the overall parasitic capacitance of the semiconductor device 10 and optimizing its electrical performance.

[0203] Figure 19 is another top view of the semiconductor device 10 provided in the embodiment of this application, Figure 20 is a cross-sectional view along section line H-H' in Figure 19, and Figure 21 is a cross-sectional view along section line I-I' in Figure 19.

[0204] The cross-sectional view along section line G-G' in Figure 19 can be found in Figure 17 above.

[0205] In some embodiments, as shown in FIG19, the first insulating film layer 51 includes a plurality of first sub-layers 511, a plurality of second sub-layers 512 and a fifth sub-layer 515. The fifth sub-layer 515 is disposed on the same side of the plurality of first sub-layers 511 and the plurality of second sub-layers 512 along the second direction Y. At least one second sub-layer 512 is spaced between the fifth sub-layer 515 and the first sub-layer 511.

[0206] Referring to Figure 19, the first sub-layer 511 can be understood as the part of the first insulating film layer 51 that participates in gate control. For example, the first sub-layer 511 includes the part of the first insulating film layer 51 that contacts the channel region 2' and the part of the first insulating film layer 51 that contacts the emitter 2B.

[0207] Referring to Figure 19, the second sub-layer 512 and the fifth sub-layer 515 are both non-gate-controlled portions of the first insulating film layer 51.

[0208] Referring to Figure 19, the second sub-layer 512 can be understood as the portion of the first insulating film layer 51 that is not involved in gate control (i.e., the portion other than the first sub-layer 511), which is adjacent to the first sub-layer 511 and has a preset length (the dimension in the second direction Y). The preset length (i.e. the length of the second sub-layer 512) can be the spacing between two emitters 2B that are adjacent to each other along the second direction Y.

[0209] For example, the second sub-layer 512 may include the portion of the first insulating film layer 51 located between two adjacent emitters 2B disposed along the second direction Y, and may also include the portions of the first insulating film layer 51 located on both sides of the first sub-layer 511 and within a preset length.

[0210] Referring to Figure 19, the fifth sub-layer 515 can be understood as the portion of the first insulating film layer 51 that is away from the first sub-layer 511. For example, the fifth sub-layer 515 can be the portion of the first insulating film layer 51 that is not involved in gate control, which is spaced from the first sub-layer 511 by the aforementioned preset length. For example, the fifth sub-layer 515 can be the portion located above the first second sub-layer 512 from top to bottom in Figure 19, so that the fifth sub-layer 515 is disposed away from the first sub-layer 511 relative to the second sub-layer 512.

[0211] It is understood that the fifth sub-layer 515 can also be located below in Figure 19. Figure 19 is merely an example and does not impose any limitation on the number and size of the fifth sub-layer 515.

[0212] For example, the thickness of the second sub-layer 512 can be the same as the thickness of the first sub-layer 511, and the thickness of the fifth sub-layer 515 can be greater than the thickness of the first sub-layer 511 and the second sub-layer 512. That is, in the first insulating film layer 51, the portion involved in gate control is thinner, and in the portion not involved in gate control, the portion surrounding the first sub-layer 511 is also thinner. Only the portion not involved in gate control and far from the first sub-layer 511 is thicker. The thickness of the second sub-layer 512 is the same as the thickness of the first sub-layer 511, which can ensure that the depth of each region in the portion of the semiconductor layer 2 near the gate 3 is approximately the same. For example, this makes the well layer 2... The depth of the portion of A used to form the channel (i.e., the portion of the well layer 2A that contacts the first sub-layer 511) is approximately the same as the depth of the portion located on both sides of the channel region 2' along the second direction Y (i.e., the portion of the well layer 2A that contacts the second sub-layer 512). This avoids the impact of different depths on the electrical performance of the channel region 2'. By only thickening the fifth sub-layer 515, which is far from the gate control region (e.g., the channel region 2'), the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the implantation layer 1 is reduced, thereby reducing the overall parasitic capacitance of the semiconductor device 10 and reducing the tailing effect of the semiconductor device 10 during the turn-on process.

[0213] As shown in Figure 19, the second insulating film layer 52 includes a plurality of third sub-layers 521, a plurality of fourth sub-layers 522 and a sixth sub-layer 526. The sixth sub-layer 526 is disposed on the same side of the plurality of third sub-layers 521 and the plurality of fourth sub-layers 522 along the second direction Y. At least one fourth sub-layer 522 is spaced between the sixth sub-layer 526 and the third sub-layer 521. The sixth sub-layer 526 and the fifth sub-layer 515 are arranged in the first direction X.

[0214] That is, the sixth sub-layer 526 is the portion of the second insulating film layer 52 that corresponds to the fifth sub-layer 515 of the first insulating film layer 51.

[0215] For example, referring to Figures 19, 17 and 20, the first sublayer 511, the second sublayer 512, the third sublayer 521 and the fourth sublayer 522 have the same thickness. Referring to Figure 21, the fifth sublayer 515 and the sixth sublayer 526 have the same thickness. Referring to Figure 19, or comparing Figures 17, 20 and 21, it can be seen that the thickness of the fifth sublayer 515 and the sixth sublayer 526 is greater than the thickness of the first sublayer 511, the second sublayer 512, the third sublayer 521 and the fourth sublayer 522.

[0216] This design facilitates the simultaneous fabrication of the first sublayer 511, the second sublayer 512, the third sublayer 521, and the fourth sublayer 522, as well as the simultaneous fabrication of the fifth sublayer 515 and the sixth sublayer 526, reducing fabrication difficulty. Simultaneously, without affecting the gate control effect of the gate 3, it reduces the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the implantation layer 1, and also reduces the parasitic capacitance between the dummy gate 4 and the semiconductor layer 2 or the implantation layer 1, further reducing the overall parasitic capacitance of the semiconductor device 10 and optimizing its electrical performance.

[0217] In some embodiments, the thickness of at least a portion of the second insulating film layer 52 is 1.5 to 3 times the thickness d1 of the portion of the first insulating film layer 51 that contacts the channel region 2'.

[0218] For example, it can be 1.5 times, 2 times, 2.75 times or 3 times.

[0219] For example, when the thickness of the first insulating film layer 51 is uniformly set and the thickness of the second insulating film layer 52 is uniformly set, the thickness of the second insulating film layer 52 can be 1.5 to 3 times the thickness of the first insulating film layer 51.

[0220] Alternatively, for example, the average thickness of the second insulating film layer 52 can be 1.5 to 3 times the average thickness of the first insulating film layer 51.

[0221] For example, referring to Figures 16 to 21, the thickness of the thicker portion of the first insulating film layer 51 (e.g., the fifth sub-layer 515) can be 1.5 to 3 times the thickness of the thinner portion of the first insulating film layer 51 (e.g., the first sub-layer 511), and the same applies to the second insulating film layer 52.

[0222] By setting the thickness of the thicker portion of the insulating film layer (first insulating film layer 51 and second insulating film layer 52) to be 1.5 to 3 times that of the thinner portion, flexible control of the electrical performance of the semiconductor device 10 can be achieved.

[0223] In some embodiments, the dielectric constant of the second insulating layer 52 may be less than or equal to the dielectric constant of the first insulating layer 51, thereby further reducing the parasitic capacitance between the dummy gate 4 and the semiconductor layer 2 or the implantation layer 1 without affecting the gate control performance of the gate 3, thereby reducing the overall parasitic capacitance of the semiconductor device 10, alleviating the voltage tailing problem, and reducing the turn-on loss of the semiconductor device 10.

[0224] For example, the dielectric constant of the material of the second insulating film layer 52 can be approximately 3.9, the dielectric constant of the material of the first insulating film layer 51 can be approximately 7.5, or the dielectric constant can even reach 25 if the material of the first insulating film layer 51 includes a high dielectric constant material such as hafnium oxide.

[0225] For example, the first insulating film layer 51 and / or the second insulating film layer 52 may also be a multilayer composite structure, and the materials of the different layers may be different.

[0226] This application also provides a method for fabricating a semiconductor device 10.

[0227] Figure 22 is a flowchart of one fabrication process of the semiconductor device 10 provided in the embodiment of this application, Figure 23 is another flowchart of fabrication process of the semiconductor device 10 provided in the embodiment of this application, and Figures 24 to 41 are cross-sectional views corresponding to each fabrication step of the semiconductor device 10.

[0228] In some embodiments, as shown in FIG21, the preparation method includes the following steps S1 to S4:

[0229] S1: Referring to Figure 25, a first trench U1 and a second trench U2 are formed on the semiconductor layer 2.

[0230] For example, referring to Figures 24 and 25, the alignment etching of the first trench U1 and the second trench U2 can be achieved by using a hard mask M.

[0231] Referring to Figure 25, the first groove U1 and the second groove U2 are arranged alternately.

[0232] For example, referring to FIG25, both the first trench U1 and the second trench U2 extend into the interior of the semiconductor layer 2.

[0233] For example, referring to Figure 26, before performing step S3, the hard mask M needs to be removed to avoid affecting subsequent fabrication steps.

[0234] S2: Form the first insulating film layer 51 and the second insulating film layer 52.

[0235] Referring to Figure 30, the first insulating film layer 51 is located on the inner wall of the first trench U1, and the second insulating film layer 52 is located on the inner wall of the second trench U2.

[0236] Referring to Figure 30, at least a portion of the thickness of the second insulating film layer 52 is greater than the thickness of the first insulating film layer 51.

[0237] The preparation method provided in this application embodiment can form a thicker second insulating film layer 52, so that the parasitic capacitance of the formed semiconductor device 10 during the conduction process is smaller, the voltage tailing problem is alleviated, and its turn-on loss is effectively reduced.

[0238] For example, as shown in FIG23, step S2 may include the following steps S21 to S24:

[0239] S21: Referring to Figure 27, a protective layer A1 is formed on the inner wall of the first trench U1.

[0240] The protective layer A1 is used to cover the first trench U1 to prevent subsequent steps from damaging the inner wall of the first trench U1.

[0241] For example, the material of the protective layer A1 may include oxide or silicon nitride.

[0242] In some embodiments, referring to FIG27, the protective layer A1 may also cover the second trench U2, and the portion of the protective layer A1 covering the second trench U2 may be used for subsequent oxidation to form the first oxide layer B1 (refer to FIG28).

[0243] S22: Referring to Figure 28, a first oxide layer B1 is formed on the inner wall of the second trench U2.

[0244] For example, when the protective layer A1 only covers the first trench U1, the protective layer A1 can be used to prevent the inner wall of the first trench U1 from oxidizing and forming an oxide layer, so that the first oxide layer B1 is formed only on the inner wall of the second trench U2.

[0245] Alternatively, referring to Figures 27 and 28, when the protective layer A1 covers both the first trench U1 and the second trench U2, a mask (not shown in the figure) can be used to cover the first trench U1 and the protective layer A1 in the first trench U1, and then the protective layer A1 on the inner wall of the second trench U2 can be oxidized to form the first oxide layer B1.

[0246] S23: Refer to Figure 29 and remove the protective layer A1.

[0247] Referring to Figure 29, after removing the protective layer A1, the inner wall of the first trench U1 is exposed. At this time, a first oxide layer B1 already exists on the inner wall of the second trench U2.

[0248] S24: Referring to Figure 30, a second oxide layer B2 is formed on the inner wall of the first trench U1 and on the first oxide layer B1.

[0249] Referring to Figure 30, it can be understood that at this time, the inner wall of the first trench U1 has only one layer of the second oxide layer B2, while the inner wall of the second trench U2 has one layer of the first oxide layer B1 and one layer of the second oxide layer B2.

[0250] The portion of the second oxide layer B2 located on the inner wall of the first trench U1 serves as the first insulating film layer 51, and the portion of the second oxide layer B2 located in the second trench U2, together with the first oxide layer B1, serves as the second insulating film layer 52.

[0251] That is, the second insulating film layer 52 has two oxide layers (first oxide layer B1 and second oxide layer B2), while the first insulating film layer 51 has only one oxide layer (second oxide layer B2). This ensures that the thickness of the second insulating film layer 52 is greater than the thickness of the first insulating film layer 51. This allows the first insulating film layer 51, which participates in gate control, to have a thinner thickness, thus ensuring the gate control effect. Meanwhile, the second insulating film layer 52, which does not participate in gate control, has a thicker thickness, thereby reducing the parasitic capacitance in the semiconductor device 10 and optimizing its electrical performance.

[0252] In some embodiments, it is understood that, with reference to the aforementioned modifications to the structure of the semiconductor device 10, the fabrication steps can be adjusted accordingly. For example, the size of the region where the protective layer A1 is located can be adjusted accordingly. For example, the protective layer A1 can be formed at the location where a thinner insulating film layer needs to be formed. For example, the protective layer can be formed only on the inner wall of the portion of the first trench U1 that corresponds to the channel region 2', so that the thickness of the portion of the first insulating film layer 51 that participates in gate control (i.e., the portion corresponding to the channel region 2') is thinner, while the thickness of the portion of the first insulating film layer 51 that does not participate in gate control (i.e., the portion located between two adjacent channel regions 2' along the second direction Y) is thicker. The second insulating film layer 52 is similarly treated.

[0253] S3: Referring to Figure 31, gate 3 and pseudo gate 4 are formed.

[0254] Referring to Figure 31, the gate 3 is filled in the first trench U1, and the dummy gate 4 is filled in the second trench U2.

[0255] It is understandable that after the gate 3 fills the first trench U1, the first insulating film layer 51 can be sandwiched between the inner wall of the first trench U1 and the gate 3, thereby achieving electrical insulation between the semiconductor layer 2 and the gate 3.

[0256] Similarly, after the dummy gate 4 fills the second trench U2, the second insulating film layer 52 can be sandwiched between the inner wall of the second trench U2 and the dummy gate 4, thereby realizing the electrical connection between the semiconductor layer 2 and the dummy gate 4.

[0257] For example, referring to FIG31, in this step, the top of the gate 3 and / or the dummy gate 4 may also be partially etched to leave space for the fabrication of the intermediate layer 81 (see FIG32).

[0258] S4: Doping semiconductor layer 2 forms drift layer 2C, well layer 2A and emitter 2B.

[0259] For example, referring to Figures 32 and 33, step S4 may include:

[0260] S41: Referring to Figure 32, ion implantation is performed on one side surface of the semiconductor layer 2 where the first trench U1 and the second trench U2 are formed to form a well layer 2A.

[0261] Referring to Figure 32, this step can fabricate a well layer 2A around the opening of the first trench U1 and the opening of the second trench U2 in the semiconductor layer 2, that is, the first trench U1 and the second trench U2 can penetrate the well layer 2A.

[0262] For example, step S41 may be located before or after the aforementioned step S3. This application embodiment is only used as an example of step S41 being located after step S3 to illustrate the preparation method, and is not intended to limit the preceding and following steps in the preparation method.

[0263] For example, referring to FIG32, when step S41 is after step S3, before ion implantation, an intermediate layer 81 can be provided on the exposed surfaces of the gate 3 and the dummy gate 4. The intermediate layer 81 has insulation properties to protect the gate 3 and the dummy gate 4 from the effects of ion implantation.

[0264] For example, referring to FIG32, in this step, a portion of the semiconductor layer 2 may also be doped to form a memory region 2E.

[0265] S42: Referring to Figure 33, ion implantation is performed on one side surface of the trap layer 2A to form the emitter 2B.

[0266] Referring to Figure 33, the emitter 2B is embedded in the well layer 2A, and the emitter 2B extends from the surface of the well layer 2A into the well layer 2A.

[0267] For example, referring to FIG33, a first shielding layer N1 can be used to cover the part where the emitter 2B does not need to be formed. For example, the first shielding layer N1 covers the dummy gate 4 and the well layer 2A around the dummy gate 4, exposing only the well layer 2A around the gate 3, so that the emitter 2B is formed only around the gate 3.

[0268] For example, in other embodiments, the well layer 2A around the dummy gate 4 may also be exposed, thereby forming an emitter 2B around the dummy gate 4 as well, reducing the precision of the emitter 2B fabrication. However, it should be noted that in this case, the dummy gate 4 cannot be connected to the gate signal to avoid the dummy gate 4 also playing a gate control role under the influence of the surrounding emitters 2B.

[0269] Referring to Figure 33, the portion of semiconductor layer 2 other than well layer 2A (and memory region 2E) can serve as drift layer 2C.

[0270] Referring to Figure 33, the trap layer 2A is disposed on the drift layer 2C.

[0271] Referring to Figure 33, after step S4, the portions of the well layer 2A and the drift layer 2C near the well layer 2A can be arranged around the first trench U1 and around the second trench U2, and the side of the emitter 2B near the first trench U1 serves as the inner wall of the first trench U1. That is, the first trench U1 penetrates the emitter 2B and the well layer 2A and extends to the drift layer 2C, and the second trench U2 at least penetrates the well layer 2A and extends to the drift layer 2C.

[0272] Referring to Figure 33, after the aforementioned steps S1 to S4, the thickness of at least a portion of the second insulating film layer 52 can be made to be at least greater than the thickness of the portion of the first insulating film layer 51 that is in contact with the channel region 2', where the channel region 2' is the portion of the well layer 2A located between the emitter 2B and the drift layer 2C.

[0273] For example, referring to Figures 34 to 41, the preparation method may also include the following other steps.

[0274] Referring to Figure 34, a second shielding layer N2 can be covered on the side of the gate 3 and the emitter 2B away from the drift layer 2C, and the pseudo gate 4 and the structure near the pseudo gate 4 can be annealed or otherwise processed.

[0275] Referring to Figure 35, a dielectric layer 8 can be disposed on the same side of the gate 3, the dummy gate 4, and the semiconductor layer 2 to achieve electrical insulation between the gate 3 and other conductive structures, and electrical insulation between the dummy gate 4 and other conductive structures.

[0276] Referring to Figure 36, the dielectric layer 8 is cut using the third shielding layer N3 to expose at least a portion of the emitter 2B and at least a portion of the well layer 2A, so that the emitter 2B and the well layer 2A can be electrically connected to the emitter electrode 7 formed thereafter.

[0277] For example, referring to FIG36, in this step, portions of the first insulating film layer 51 and the second insulating film layer 52 located on the side surface of the well layer 2A away from the drift layer 2C can also be removed simultaneously to expose the emitter 2B and the well layer 2A.

[0278] Referring to Figure 37, an emitter electrode 7 can be formed to enable the input and output of electrical signals.

[0279] Referring to Figure 38, the semiconductor layer 2 (the side of the drift layer 2C away from the well layer 2A) can be doped to form a buffer layer 2D and an implantation layer 1.

[0280] For example, this step can be prepared in various ways. For instance, a semiconductor layer 2 can be grown on the implantation layer 1 before step S1, or a semiconductor layer 2 can be epitaxially grown on a substrate first, and then the substrate can be removed before ion implantation of the semiconductor layer 2 to form the implantation layer 1, or the semiconductor layer 2 can be directly doped to form the implantation layer 1. The embodiments of this application do not limit the preparation order or preparation method of the two. Any preparation process that can realize the stacking of the implantation layer 1 and the semiconductor layer 2 is within the protection scope of the embodiments of this application.

[0281] Referring to Figure 38, after the injection layer 1 is formed, a collector 6 can be formed on the side of the injection layer 1 away from the drift layer 2C.

[0282] The preparation method can also be modified in some ways. For example, referring to Figures 39, 40 and 41, during the cutting of the dielectric layer 8, the dielectric layer 8 on at least one side of the well layer 2A of at least one second trench U2 (e.g., the well layer 2A on the right side of the rightmost second trench U2 in Figures 39, 40 and 41) can be retained, so that this part of the well layer 2A will not be in electrical contact with the emitter electrode 7 (see Figure 41), thereby achieving the electrical levitation of this part of the well layer 2A.

[0283] The following is an embodiment of fabricating a semiconductor device 10:

[0284] (a) Photolithography and dry etching of oxide masks on semiconductor layers.

[0285] (b) Trench etching and damage removal (e.g., etching oxide layer, CDE etching away a certain thickness of silicon).

[0286] (c) Removal of oxides, cleaning, sacrificial oxidation and its removal.

[0287] (d) Deposition of thermally grown pad oxide (30 nm) and silicon nitride.

[0288] (e) Photolithography and etching of silicon nitride, and selective oxidation to form a thick oxide (200 nm thick).

[0289] (f) Removal of silicon nitride (Si3N4) and pad oxide.

[0290] (g) Gate oxidation, forming a gate oxide layer and a pseudo trench oxide layer.

[0291] (h) Doped polycrystalline or amorphous silicon trench filling and etchback.

[0292] (i) Subsequent process steps to form IGBT semiconductor devices.

[0293] Depending on the specific process integration plan, process steps (d) to (f) can also be replaced with the following order:

[0294] 1) Deposit a high-temperature oxide (HTO) with a thickness of 150nm to 300nm and densify it.

[0295] 2) Photolithography and etching HTO.

[0296] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Drift layer; A trap layer is disposed on the drift layer; An emitter is embedded in the well layer, and the emitter extends from a first surface of the well layer into the well layer, the first surface being the surface of the well layer away from the drift layer; On one side of the first surface of the well layer, a first groove and a second groove are formed in a direction perpendicular to the first surface. The first groove and the second groove are spaced apart. The portions of the well layer and the drift layer near the well layer are arranged around the first groove and around the second groove, and the side of the emitter near the first groove serves as the inner wall of the first groove. A gate, wherein the gate is filled in the first trench, and a first insulating film layer is disposed between the gate and the inner wall of the first trench; and, A dummy gate is filled in the second trench, and a second insulating film layer is provided between the dummy gate and the inner wall of the second trench; Wherein, at least a portion of the thickness of the second insulating film layer is greater than the thickness of the portion of the first insulating film layer in contact with the channel region; the channel region is the portion of the well layer located between the emitter and the drift layer.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the first insulating film layer is the same at different positions on the cross section perpendicular to the second direction; the second direction is the length extension direction of the first trench and the second trench, and the second direction intersects the arrangement direction of the first trench and the second trench.

3. The semiconductor device according to claim 1 or 2, characterized in that, The average thickness of the second insulating film layer is greater than the average thickness of the first insulating film layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, On one side of the first surface of the well layer, a plurality of second grooves are provided at intervals along a direction perpendicular to the first surface; The thickness of the first insulating film layer is the same at different locations, and the thickness of the second insulating film layer in the same second trench is the same at different locations.

5. The semiconductor device according to claim 4, characterized in that, The thickness of the second insulating film layer in each of the second trenches is greater than the thickness of the first insulating film layer.

6. The semiconductor device according to claim 5, characterized in that, The thickness of the second insulating film layer in the multiple second trenches is the same.

7. The semiconductor device according to claim 4, characterized in that, In a plurality of second trenches, the thickness of the second insulating film layer in the second trench adjacent to the first trench is the same as the thickness of the first insulating film layer; The thickness of the second insulating film layer in the second trench, which is spaced apart from the first trench by at least one second trench, is greater than the thickness of the first insulating film layer.

8. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device includes a plurality of emitters, which are arranged sequentially at intervals along a second direction, and each emitter is in contact with the first insulating film layer. The first insulating film layer includes a plurality of first sub-layers and a plurality of second sub-layers, the plurality of first sub-layers and the plurality of second sub-layers being alternately arranged along the second direction, and the first sub-layers being in contact with the emitter; The second insulating film layer includes a plurality of third sub-layers and a plurality of fourth sub-layers, which are alternately arranged along the second direction; the third sub-layers and the first sub-layers are arranged in a first direction, and the fourth sub-layers and the second sub-layers are arranged in the first direction; the first direction is the arrangement direction of the first trench and the second trench; The first sub-layer and the third sub-layer have the same thickness, the second sub-layer and the fourth sub-layer have the same thickness, and the thickness of the second sub-layer and the fourth sub-layer is greater than the thickness of the first sub-layer and the third sub-layer.

9. The semiconductor device according to claim 1 or 2, characterized in that, The first insulating film layer includes a plurality of first sub-layers, a plurality of second sub-layers and a fifth sub-layer, wherein the fifth sub-layer is disposed on the same side of the plurality of first sub-layers and the plurality of second sub-layers along a second direction, and at least one second sub-layer is spaced between the fifth sub-layer and the first sub-layer; The second insulating film layer includes a plurality of third sub-layers, a plurality of fourth sub-layers, and a sixth sub-layer. The sixth sub-layer is disposed on the same side of the plurality of third sub-layers and the plurality of fourth sub-layers along a second direction. At least one fourth sub-layer is spaced between the sixth sub-layer and the third sub-layer. The sixth sub-layer and the fifth sub-layer are arranged in a first direction. The first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer have the same thickness, the fifth sub-layer and the sixth sub-layer have the same thickness, and the thickness of the fifth sub-layer and the sixth sub-layer is greater than the thickness of the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The thickness of at least a portion of the second insulating film layer is 1.5 to 3 times the thickness of the portion of the first insulating film layer that contacts the channel region.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The dielectric constant of the second insulating film layer is less than or equal to the dielectric constant of the first insulating film layer.

12. A method for fabricating a semiconductor device, characterized in that, include: A first trench and a second trench are formed on one side surface of the semiconductor layer; The first trench and the second trench are spaced apart; A first insulating film layer and a second insulating film layer are formed; the first insulating film layer is located on the inner wall of the first trench, and the second insulating film layer is located on the inner wall of the second trench; A gate and a dummy gate are formed; the gate is filled in the first trench, and the dummy gate is filled in the second trench; The semiconductor layer is doped to form a drift layer, a well layer, and an emitter; the well layer is disposed on the drift layer. The emitter is embedded in the well layer, and the emitter extends from the surface of the well layer away from the drift layer into the well layer; The well layer and the drift layer are disposed around the first trench and around the second trench, respectively, with the side of the emitter near the first trench serving as the inner wall of the first trench. Wherein, at least a portion of the thickness of the second insulating film layer is at least greater than the thickness of the portion of the first insulating film layer that contacts the channel region; The channel region is the portion of the trap layer located between the emitter and the drift layer.

13. The preparation method according to claim 12, characterized in that, The formation of the first insulating film layer and the second insulating film layer includes: A protective layer is formed on the inner wall of the first trench; A first oxide layer is formed on the inner wall of the second trench; Remove the protective layer; A second oxide layer is formed on the inner wall of the first trench and on the first oxide layer; the portion of the second oxide layer located on the inner wall of the first trench serves as a first insulating film layer, and the portion of the second oxide layer located in the second trench, together with the first oxide layer, serves as the second insulating film layer.

14. An integrated circuit, characterized in that, include: The semiconductor device as described in any one of claims 1 to 11; Electronic devices, electrically connected to the semiconductor devices.

15. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 1 to 11, or the integrated circuit as described in claim 14; A circuit board, wherein the semiconductor device or the integrated circuit is disposed on the circuit board.

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