Instruction processing method and apparatus, processor, electronic device, and readable storage medium

Abstract

This application relates to an instruction processing method and apparatus, a processor, an electronic device, and a readable storage medium. The method includes: when the addresses of a first memory access instruction and a second memory access instruction overlap, obtaining first address information of the first memory access instruction and second address information of the second memory access instruction; determining a merging base address and a merging address offset for a merge instruction between the first and second memory access instructions based on the first and second address information; and processing the first and second memory access instructions based on the merging base address and the merging address offset. This method can improve the scenario applicability of the instruction merging scheme.

Description

Technical Field

[0001] This application relates to the field of instruction processing technology, and in particular to an instruction processing method and apparatus, processor, electronic device, and readable storage medium. Background Technology

[0002] In the current field of electronic devices, the processor, as a core component, undertakes important tasks such as executing instructions, processing data, and controlling system operations. For example, the processor interacts with memory through specific interfaces and communication protocols to perform data access operations.

[0003] Typically, different computer architectures have memory access instructions of varying lengths. In order to utilize the processor's memory access bandwidth, related technologies often combine multiple memory access instructions of different lengths into a long instruction. This can significantly reduce the number of instructions, effectively improve computational efficiency, and fully leverage the processor's memory access capabilities.

[0004] However, the instruction merging scheme used by processors in related technologies to process memory access instructions has the technical problem of poor applicability to various scenarios. Summary of the Invention

[0005] Therefore, it is necessary to provide an instruction processing method and apparatus, processor, electronic device, and readable storage medium that can improve the scenario applicability of the instruction merging scheme in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides an instruction processing method, including:

[0007] If the addresses of the first memory access instruction and the second memory access instruction overlap, obtain the first address information of the first memory access instruction and the second address information of the second memory access instruction.

[0008] Based on the first address information and the second address information, determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction;

[0009] The first and second memory access instructions are processed based on the merge base address and merge address offset of the merge instruction.

[0010] In one embodiment, determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes:

[0011] Based on the first address information and the second address information, determine the address overlap type between the first memory access instruction and the second memory access instruction;

[0012] Based on the address overlap type, determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction.

[0013] In one embodiment, determining the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes:

[0014] If the base address in the first address information is less than the base address in the second address information, the end address in the first address information is greater than the base address in the second address information, and the end address in the first address information is less than the end address in the second address information, then the address overlap type is determined to be a partial address overlap type.

[0015] If the base address in the first address information is less than or equal to the base address in the second address information, and the end address of the first address information is greater than or equal to the end address of the second address information, the address overlap type is determined to be a full coverage address overlap type.

[0016] In one embodiment, determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the address overlap type includes:

[0017] When the address overlap type is partial address overlap type, and the base address in the first address information is less than the base address in the second address information, the base address in the first address information is determined as the merged base address. The base address in the first address information and the offset are added together, and then the base address in the second address information is subtracted to obtain the merged address offset.

[0018] When the address overlap type is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the base address in the first address information is determined as the merged base address, and the offset in the first address information is determined as the merged address offset.

[0019] In one embodiment, the first memory access instruction and the second memory access instruction are processed according to the merge base address and merge address offset of the merge instruction, including:

[0020] The instruction type of the merge instruction is determined based on the instruction type of the first memory access instruction and the instruction type of the second memory access instruction.

[0021] Based on the instruction type, the merge base address, and the merge address offset of the merge instruction, the first memory access instruction and the second memory access instruction are processed.

[0022] In one embodiment, the first memory access instruction and the second memory access instruction are processed according to the instruction type of the merge instruction, the merge base address of the merge instruction, and the merge address offset, including:

[0023] When the instruction type of the merge instruction indicates that data at the merge address offset is to be loaded, the target data is read from memory according to the merge base address and merge address offset of the merge instruction, and the target data is processed according to the first memory access instruction and the second memory access instruction.

[0024] When the instruction type of the merge instruction indicates that the data to be stored is the merged address offset, the merged data, which is the merged data corresponding to the first address information of the first memory access instruction and the merged address offset of the second memory access instruction, is stored in the memory according to the merge base address and the merged address offset of the merge instruction.

[0025] In one embodiment, target data is read from memory according to the merge base address and merge address offset of the merge instruction, and the target data is processed according to the first memory access instruction and the second memory access instruction, including:

[0026] Based on the merge base address and merge address offset of the merge instruction, the target data read from memory is stored in the target register;

[0027] According to the first memory access instruction, the data corresponding to the first address information in the target register is stored in the first register;

[0028] According to the second memory access instruction, the data corresponding to the second address information in the target register is stored in the second register.

[0029] In one embodiment, target data is read from memory according to the merge base address and merge address offset of the merge instruction, and the target data is processed according to the first memory access instruction and the second memory access instruction, including:

[0030] When the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the target data read from the memory is stored in the first register according to the merge base address and merge address offset of the merge instruction, and according to the first memory access instruction.

[0031] According to the second memory access instruction, the data corresponding to the second address information stored in the first register is stored in the second register.

[0032] In one embodiment, based on the merge base address and merge address offset of the merge instruction, the merged data, which is the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction, is stored in the memory, including:

[0033] According to the writing order of the data to be stored corresponding to the first address information in the third register indicated by the first memory access instruction and the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction, the data to be stored corresponding to the first address information and the data to be stored corresponding to the second address information are overwritten and stored in the designated register so that the designated register stores the merged data.

[0034] Based on the merge base address and merge address offset of the merge instruction, the merged data stored in the specified register is stored into the memory.

[0035] In one embodiment, storing the merged data—the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction—into memory according to the merge base address and merge address offset of the merge instruction includes:

[0036] If the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the merged data stored in the third register indicated by the first memory access instruction is stored in the memory according to the merge base address and merge address offset of the merge instruction.

[0037] In one embodiment, storing the merged data stored in the third register indicated by the first memory access instruction into the memory according to the merge base address and merge address offset of the merge instruction includes:

[0038] If the writing order of the data to be stored corresponding to the first address information is after the writing order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the first address information stored in the third register indicated by the first memory access instruction is determined as the merged data, and the merged data stored in the third register is stored in the memory according to the merge base address and merge address offset of the merge instruction.

[0039] If the writing order of the data to be stored corresponding to the first address information is before the writing order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction is overwritten and written into the third register indicated by the first memory access instruction for storing the data to be stored corresponding to the first address information. Then, according to the merging base address and merging address offset of the merging instruction, the merged data stored in the third register is stored in the memory.

[0040] Secondly, this application provides an instruction processing apparatus, the apparatus comprising:

[0041] The acquisition module is used to acquire the first address information of the first memory access instruction and the second address information of the second memory access instruction when the addresses of the first memory access instruction and the second memory access instruction overlap.

[0042] The determination module is used to determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the first address information and the second address information.

[0043] The processing module is used to process the first memory access instruction and the second memory access instruction according to the merge base address and merge address offset of the merge instruction.

[0044] Thirdly, this application provides a processor that implements the steps of any of the above methods when executing a computer program.

[0045] Fourthly, this application provides an electronic device, which includes the processor of the third aspect.

[0046] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the methods described above.

[0047] In this embodiment of the application, the instructions can be merged even when the addresses of the first memory access instruction and the second memory access instruction overlap. Then, the first memory access instruction and the second memory access instruction are processed according to the merging base address and the merging address offset of the merging instruction. Thus, the instruction merging scheme can be applied to scenarios where the addresses of the two memory access instructions overlap, thereby improving the scenario applicability of the instruction merging scheme. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic diagram of the structure of a system provided in this application embodiment;

[0050] Figure 2 A flowchart illustrating an instruction processing method provided in the first embodiment of this application;

[0051] Figure 3 A flowchart illustrating an instruction processing method provided in the second embodiment of this application;

[0052] Figure 4 A flowchart illustrating an instruction processing method provided in the third embodiment of this application;

[0053] Figures 5a to 5i A schematic diagram illustrating the address overlap of a first memory access instruction and a second memory access instruction provided for some embodiments;

[0054] Figure 6 A flowchart illustrating an instruction processing method provided in the fourth embodiment of this application;

[0055] Figure 7 This is a schematic diagram of the structure of an instruction processing apparatus provided in some embodiments of this application;

[0056] Figure 8 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] The technical solutions of this application will be described in detail below through embodiments and in conjunction with the accompanying drawings. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0059] It should be noted that in this application example, "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0060] Furthermore, the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0061] Taking a graphics processing unit (GPU) as an example, different computer architectures have memory access instructions of varying lengths. To fully utilize the GPU's memory access bandwidth, multiple short instructions can be merged into longer instructions. For instance, two adjacent BUFFER_LOAD_B32 instructions (instructions for loading 32 bits of cached data) can be merged into a BUFFER_LOAD_B64 instruction (instructions for loading 64 bits of cached data). This significantly reduces the number of instructions, effectively improving computational efficiency and fully leveraging the GPU's memory access capabilities.

[0062] In some implementation scenarios, instruction merging methods are mainly used for merging instructions with adjacent memory access addresses. Merging needs to meet the following condition: the difference between the offset 0 of the first instruction address and the offset 1 of the second instruction address needs to be equal to the width 1 of the first instruction address, that is, the width 0 of the first instruction address must be equal to (offset 1 - offset 0).

[0063] However, this instruction merging method is suitable for scenarios where memory access addresses are adjacent and do not overlap, but it cannot solve scenarios where the memory access address ranges of two instructions are not only adjacent but also overlap.

[0064] The instruction processing method provided in this application embodiment can be applied in a processing module. Figure 1 This is a schematic diagram of a system provided in an embodiment of this application. The system 10 includes a processor 11 and a memory 12. The processor 11 can read data from the memory 12 or store data in the memory 12. For example, the memory access instruction can be a load instruction or a store instruction. When the processor 11 generates a load instruction, the processor 11 can read data from the memory 12 into a register according to the load instruction. When the processor 11 generates a store instruction, the processor 11 can store data from the register into the memory 12 according to the store instruction.

[0065] The processor in any embodiment of this application may include integration of any one or more of the following: general-purpose processor, application-specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field-programmable gate array (FPGA), central processing unit (CPU), GPU, embedded neural-network processing unit (NPU), controller, microcontroller, microprocessor, programmable logic device, discrete gate or transistor logic device, discrete hardware component, hardware decoding processor.

[0066] The memory or computer-readable storage medium in any embodiment of this application may include at least one of non-volatile memory and volatile memory. Non-volatile memory includes integration of one or more of the following: Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory, Optical Disc, Compact Disc Read-Only Memory (CD-ROM), Magnetic Tape, Floppy Disk, Flash Memory, Optical Memory, High-Density Embedded Non-Volatile Memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Graphene Memory, Volatile Memory, etc. Volatile memory includes one or more of the following: Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0067] In some embodiments, registers may be included in the processor.

[0068] In some embodiments, the storage may encompass memory. For example, memory may include shared memory or local memory.

[0069] Figure 2This is a flowchart illustrating an instruction processing method provided in the first embodiment of this application. The method is applied to a processor and includes:

[0070] S201. If the address of the first memory access instruction and the address of the second memory access instruction overlap, obtain the first address information of the first memory access instruction and the second address information of the second memory access instruction.

[0071] In some embodiments, the first memory access instruction and the second memory access instruction have the same instruction type. For example, both the first memory access instruction and the second memory access instruction are load instructions, or both the first memory access instruction and the second memory access instruction are store instructions.

[0072] In some embodiments, the first memory access instruction and the second memory access instruction may be instructions in the same queue, or they may be instructions in different queues. In some embodiments, the first memory access instruction and the second memory access instruction may be two adjacent instructions in the same queue, or two non-adjacent instructions. In other embodiments, the first memory access instruction and the second memory access instruction may be instructions in two queues that need to be processed in parallel. In some embodiments, the order difference between the first memory access instruction and the second memory access instruction is less than or equal to a target threshold.

[0073] In some implementations, when the processor receives one of the first memory access instruction and the second memory access instruction, it can look up the other instruction from the queue containing that instruction. In other implementations, the processor can select the first memory access instruction and the second memory access instruction from the queue.

[0074] The address of a memory access instruction (e.g., a first memory access instruction or a second memory access instruction) can be the address of the memory that the memory access instruction needs to access. For example, if the memory access instruction is a load instruction, the address of the load instruction is the address at which the load instruction loads data from memory. As another example, if the memory access instruction is a store instruction, the address of the store instruction is the address at which data is stored in memory.

[0075] The first address information of the first memory access instruction may include at least one of the following: a first base address, a first address offset (also called an offset address), and a first end address. The second address information of the second memory access instruction may include at least one of the following: a second base address, a second address offset, and a second end address. For example, the first address information of the first memory access instruction may include the address information included in the first memory access instruction, such as the first base address and the first address offset. For example, the second address information of the second memory access instruction may include the address information included in the second memory access instruction, such as the second base address and the second address offset.

[0076] In some embodiments, the first address information and the second address information may be the same (the first address range corresponding to the first address information is the same as the second address range corresponding to the second address information), or partially overlapping (a partial range in the first address range corresponding to the first address information overlaps with a partial range in the second address range corresponding to the second address information), or fully covering (the first address range corresponding to the first address information completely covers the second address range corresponding to the second address information, or the second address range corresponding to the second address information completely covers the first address range corresponding to the first address information).

[0077] In some embodiments, the processor may determine that the addresses of the first memory access instruction and the second memory access instruction overlap based on the first address information and the second address information.

[0078] Taking the base address of the first address information being less than the base address of the second address information as an example, the base address and address offset of the first address information are offset0 and width0 respectively, and the base address and address offset of the second address information are offset1 and width1 respectively. If offset0 < offset1 and (offset0 + width0) > offset1 + width1 are satisfied, it indicates that the overlap type of the first address information and the second address information is full coverage. If offset0 < offset1, (offset0 + width0) > offset1 and (offset0 + width0) < offset1 + width1 are satisfied, it indicates that the overlap type of the first address information and the second address information is partial overlap.

[0079] S202. Determine the combined base address and combined address offset of the combined instruction between the first memory access instruction and the second memory access instruction according to the first address information and the second address information.

[0080] In some embodiments, the combined instruction may also be referred to as a wide instruction, and the address offset included in the combined instruction should be greater than or equal to the maximum value of the address offsets in the first address information and the second address information.

[0081] In some embodiments, there may be an operation of combining the first memory access instruction and the second memory access instruction to obtain a combined instruction, or there may be no operation of combining the first memory access instruction and the second memory access instruction to obtain a combined instruction, but only the combined base address and combined address offset are obtained.

[0082] In some embodiments, if a combined instruction needs to be obtained, the combined instruction may be determined according to at least one of the combined base address, the combined address offset, the register identifier corresponding to the combined address offset, the instruction type, etc.

[0083] S203. Process the first memory access instruction and the second memory access instruction according to the merge base address and merge address offset of the merge instruction.

[0084] In some embodiments, processing the first memory access instruction and the second memory access instruction may include: if both the first memory access instruction and the second memory access instruction are load instructions, performing data loading processing according to the first memory access instruction, and performing data loading processing according to the second memory access instruction. For example, according to the first memory access instruction, data corresponding to the first address information in memory is loaded into the register indicated by the first memory access instruction; according to the second memory access instruction, data corresponding to the second address information in memory is loaded into the register indicated by the second memory access instruction.

[0085] In some embodiments, processing the first memory access instruction and the second memory access instruction may include: when both the first memory access instruction and the second memory access instruction are store instructions, performing data storage processing according to the first memory access instruction, and performing data storage processing according to the second memory access instruction. For example, according to the first memory access instruction, data corresponding to the first address information in the register indicated by the first memory access instruction is stored to the first address information in the memory; according to the second memory access instruction, data corresponding to the second address information in the register indicated by the second memory access instruction is stored to the second address information in the memory.

[0086] In this embodiment of the application, the instructions can be merged even when the addresses of the first memory access instruction and the second memory access instruction overlap. Then, the first memory access instruction and the second memory access instruction are processed according to the merging base address and the merging address offset of the merging instruction. Thus, the instruction merging scheme can be applied to scenarios where the addresses of the two memory access instructions overlap, thereby improving the scenario applicability of the instruction merging scheme.

[0087] Furthermore, taking the first memory access instruction and the second memory access instruction as the first load instruction and the second load instruction, respectively, as examples, in related technologies, the addresses of the first load instruction and the second load instruction overlap. Therefore, the first load instruction and the second load instruction cannot be merged. The processor reads data within the first address range in the memory corresponding to the first address information according to the first load instruction, and the processor reads data within the second address range in the memory corresponding to the second address information according to the second load instruction. Since the first address range and the second address range overlap, the data read by the processor from the memory also overlaps. Due to memory read limitations, the processor's speed in reading data from memory is much slower than the speed in reading data from registers, thus resulting in a slow data read speed from memory. However, in this embodiment, by merging instructions to read data, there is no overlapping data read, and the size of the read data is smaller than in related technologies, thereby reducing the data read speed from memory and improving data loading efficiency.

[0088] Taking the first memory access instruction and the second memory access instruction as examples, respectively, in related technologies, the addresses of the first memory access instruction and the second memory access instruction overlap. Therefore, the first memory access instruction and the second memory access instruction cannot be merged. The processor writes data to the first address range in the memory corresponding to the first address information according to the first memory access instruction, and writes data to the second address range in the memory corresponding to the second address information according to the second memory access instruction. Since the first address range and the second address range overlap, the processor writes data to the overlapping address twice. Due to memory write limitations, the speed at which the processor writes data to memory is much slower than the speed at which it writes data to registers. This results in a slow data writing speed. However, in this embodiment, by merging instructions to write data, there is no situation where data is written to the same address twice. The size of the written data is smaller than in related technologies, thereby reducing the speed of writing data to memory and improving data writing efficiency.

[0089] Figure 3 This is a flowchart illustrating an instruction processing method provided in the second embodiment of this application. The method is applied to a processor, and compared to... Figure 2 The difference is that, Figure 2 S202 in the text includes:

[0090] S2021. Determine the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information.

[0091] In some embodiments, the address overlap type may include at least one of the following: address-same overlap type, partial address overlap type, and full-coverage address overlap type. For example, when the first address information and the second address information are the same, the address overlap type is the address-same overlap type.

[0092] S2022. Based on the address overlap type, determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction.

[0093] This section explains how to determine whether the address overlap type is partial or full coverage:

[0094] In some embodiments, determining the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes: if the base address in the first address information is less than the base address in the second address information, the end address in the first address information is greater than the base address in the second address information, and the end address in the first address information is less than the end address in the second address information, then the address overlap type is determined to be a partial address overlap type.

[0095] In some embodiments, determining the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes: if the base address in the first address information is less than or equal to the base address in the second address information, and the end address of the first address information is greater than or equal to the end address of the second address information, the address overlap type is determined to be a full-coverage address overlap type.

[0096] This section explains how to determine the merge base address and merge address offset based on the address overlap type:

[0097] In some embodiments, determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction according to the address overlap type includes: when the address overlap type is a partial address overlap type and the base address in the first address information is less than the base address in the second address information, determining the base address in the first address information as the merge base address, adding the base address in the first address information and the offset, and then subtracting the base address in the second address information to obtain the merge address offset.

[0098] In some embodiments, determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction according to the address overlap type includes: when the address overlap type is a full-coverage address overlap type and the base address in the first address information is less than the base address in the second address information, determining the base address in the first address information as the merge base address and the offset in the first address information as the merge address offset.

[0099] Figure 4 This is a flowchart illustrating an instruction processing method provided in the third embodiment of this application. The method is applied to a processor and, compared to... Figure 2 The difference is that, Figure 2 S203 in the text includes:

[0100] S2031. Determine the instruction type of the merge instruction based on the instruction type of the first memory access instruction and the instruction type of the second memory access instruction.

[0101] In some embodiments, the instruction type may include a load instruction type or a store instruction type. For example, a load instruction type may be represented as one of the following: load (ld), load global (ldg), load shared memory (lds), or load local memory (ldl). For example, a store instruction type may be represented as one of the following: store (st), store global (stg), store shared memory (sts), or store local memory (stl).

[0102] In some embodiments, the instruction type may include an instruction type for loading a first length, an instruction type for loading a second length, an instruction type for storing a first length, and an instruction type for storing a second length. Different instruction types correspond to different lengths. For example, a load instruction type may be represented as one of the following: ldg32, ldg64, ldg96, ldg128. Here, ldg32, ldg64, ldg96, and ldg128 represent loading data from global memory in 32-bit, 64-bit, 96-bit, and 128-bit increments, respectively. Similarly, a store instruction type may be represented as one of the following: stg32, stg64, stg96, stg128. Here, stg32, stg64, stg96, and stg128 represent storing data from global memory in 32-bit, 64-bit, 96-bit, and 128-bit increments, respectively.

[0103] In some embodiments, the length of an instruction type can be the same as the address offset included in the instruction.

[0104] S2032. Process the first memory access instruction and the second memory access instruction according to the instruction type, the base address and offset of the merge instruction.

[0105] The following uses the merge instruction as either a load instruction or a store instruction as examples to illustrate the processing flow of the first and second memory access instructions:

[0106] In some embodiments, when the instruction type of the merge instruction indicates that data at the merge address offset is to be loaded, the target data is read from memory according to the merge base address and the merge address offset of the merge instruction, and the target data is processed according to the first memory access instruction and the second memory access instruction.

[0107] In some embodiments, when the instruction type of the merge instruction indicates data for storing the merge address offset, the merged data, which is the merged data corresponding to the first address information of the first memory access instruction and the merge address offset of the second memory access instruction, is stored in the memory according to the merge base address and the merge address offset of the merge instruction.

[0108] The following describes embodiments of loading the first and second memory access instructions, using address overlap types that are applicable to both partial and full-coverage address overlap types (full-coverage address overlap types include address-identical overlap types):

[0109] According to the merge base address and merge address offset of the merge instruction, the target data is read from the memory, and processed according to the first memory access instruction and the second memory access instruction, including: storing the target data read from the memory into the target register according to the merge base address and merge address offset of the merge instruction; storing the data corresponding to the first address information in the target register into the first register according to the first memory access instruction; and storing the data corresponding to the second address information in the target register into the second register according to the second memory access instruction.

[0110] For example, the processor can also determine the destination register based on the merged address offset so that the destination register can store data of the merged address offset size.

[0111] For example, the target register can be indicated by a merge instruction (i.e., a merge load instruction). For example, the first register can be indicated by a first load instruction, and the second register can be indicated by a second load instruction.

[0112] In some embodiments, in the merged data stored in the target register, the starting address for reading the data corresponding to the second address information is the same as the offset of the base address of the second address information relative to the base address of the first address information.

[0113] The following describes embodiments of storing the first and second memory access instructions, using either partial or full address overlap types (full overlap types include address-identical overlap types) as examples.

[0114] Based on the merge base address and merge address offset of the merge instruction, the merged data, which combines the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction, is stored in memory, including:

[0115] According to the writing order of the data to be stored corresponding to the first address information in the third register indicated by the first memory access instruction (also called the first data to be stored) and the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction (also called the second data to be stored) (i.e., the writing order of the first data to be stored and the second data to be stored, for example, the first data to be stored is written before or after the second data to be stored), the data to be stored corresponding to the first address information and the data to be stored corresponding to the second address information are overwritten and stored in the designated register so that the designated register stores the merged data; according to the merge base address and merge address offset of the merge instruction, the merged data stored in the designated register is stored in the memory.

[0116] For example, the processor can also determine a designated register based on the merged address offset so that the designated register can store data of the size of the merged address offset.

[0117] For example, a specified register can be indicated by a merge instruction (i.e., a merge store instruction). For example, a third register can be indicated by a first store instruction, and a fourth register can be indicated by a second store instruction.

[0118] In some embodiments, in the merged data stored in the designated register, the starting address of the data to be stored corresponding to the second address information is the same as the offset of the base address of the second address information relative to the base address of the first address information.

[0119] The following describes embodiments of loading the first and second memory access instructions, using the address overlap type as an example of a full-coverage address overlap type (full-coverage address overlap type includes address-same overlap type):

[0120] According to the merge base address and merge address offset of the merge instruction, the target data is read from the memory, and the target data is processed according to the first memory access instruction and the second memory access instruction, including: when the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the target data read from the memory is stored in the first register according to the merge base address and merge address offset of the merge instruction, and according to the first memory access instruction (i.e., the first load instruction); according to the second memory access instruction (i.e., the second load instruction), the data stored in the first register corresponding to the second address information is stored in the second register.

[0121] For example, the first register may be indicated by a first load instruction, and the second register may be indicated by a second load instruction.

[0122] The following describes embodiments of storing the first and second memory access instructions, using the address overlap type as an example of a full-coverage address overlap type (full-coverage address overlap type includes address-same overlap type):

[0123] In some embodiments, storing merged data—the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction—into memory according to the merge base address and merge address offset of the merge instruction includes: when the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, storing the data to be stored corresponding to the first address information stored in the third register into memory according to the merge base address and merge address offset of the merge instruction.

[0124] For example, the third register may be indicated by the first store instruction.

[0125] In some embodiments, storing the merged data stored in the third register indicated by the first memory access instruction into the memory according to the merge base address and merge address offset of the merge instruction includes: when the write order of the data to be stored corresponding to the first address information is after the write order of the data to be stored corresponding to the second address information, determining the data to be stored corresponding to the first address information stored in the third register indicated by the first memory access instruction as the merged data, and storing the merged data stored in the third register into the memory according to the merge base address and merge address offset of the merge instruction.

[0126] Thus, when the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, and the write order of the data to be stored corresponding to the first address information is after the write order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the first address information stored in the third register indicated by the first memory access instruction is determined as the merged data, and the merged data stored in the third register is stored in the memory according to the merge base address and merge address offset of the merge instruction.

[0127] In some embodiments, storing the merged data stored in the third register indicated by the first memory access instruction into the memory according to the merge base address and merge address offset of the merge instruction includes: when the write order of the data to be stored corresponding to the first address information is before the write order of the data to be stored corresponding to the second address information, overwriting the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction into the third register indicated by the first memory access instruction for storing the data to be stored corresponding to the first address information, and storing the merged data stored in the third register into the memory according to the merge base address and merge address offset of the merge instruction.

[0128] Thus, when the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, the base address in the first address information is less than the base address in the second address information, and the write order of the data to be stored corresponding to the first address information is before the write order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction is overwritten and written into the third register indicated by the first memory access instruction for storing the data to be stored corresponding to the first address information. Then, according to the merge base address and merge address offset of the merge instruction, the merged data stored in the third register is stored in the memory.

[0129] For example, the third register may be indicated by the first store instruction, and the fourth register may be indicated by the second store instruction.

[0130] In some embodiments, in the merged data stored in the third register, the starting address of the data to be stored corresponding to the second address information is the same as the offset address of the base address of the second address information relative to the base address of the first address information.

[0131] Figures 5a to 5iSchematic diagram showing the address overlap of the first memory access instruction and the second memory access instruction provided for some embodiments. In FIG. 5, Figures 5a to 5i In each of them, the upper part represents the address range of the first memory access instruction, and the lower part represents the address range of the second memory access instruction. Among them, Figure 5a and Figure 5b have a partial address overlap type, Figures 5c to 5i has a full coverage address overlap type.

[0132] The following is described with the base address of the first memory access address as base address 0 (also called offset0), the offset as bandwidth 0 (also called width0), the base address of the second memory access address as base address 1 (also called offset1), and the offset as bandwidth 1 (also called width1):

[0133] Figures 5a to 5i There is an overlap between the address range [offset0, (offset0 + width0)] of the first memory access instruction and the address range [offset1, (offset1 + width1)] of the second memory access instruction.

[0134] Taking Figure 5a as an example, it satisfies offset0 < offset1, (offset0 + width0) > offset1, and (offset0 + width0) < offset1 + width1.

[0135] Taking Figure 5c as an example, it satisfies offset0 < offset1 and (offset0 + width0) > offset1 + width1.

[0136] Among them, instruction merging for address overlap situations is also beneficial. For example, the data contents loaded by two instructions ldg64 res, base_addr, 0 (indicating a load instruction for loading 64-bit data with a base address of 0) and ldg64 res, base_addr, 32 (indicating a load instruction for loading 32-bit data with a base address of 32) can also be solved at once by one instruction ldg96 res, base_addr, 0 (indicating a load instruction for loading 96-bit data with a base address of 0). Therefore, the embodiments of the present application provide a memory access method applicable to address overlap between instructions.

[0137] Figure 6 Schematic flowchart of an instruction processing method provided for the fourth embodiment of the present application. As Figure 6 shown, this method is applied to a processor, and this method includes:

[0138] S601. The addresses of the first memory access instruction and the second memory access instruction overlap.

[0139] S602, calculate the instruction bandwidth and base address of the wide instruction after instruction merging.

[0140] Bandwidth is also known as address offset.

[0141] S603. Select the type of merged instruction based on the instruction bandwidth.

[0142] S604. Based on the processing result of the merged wide instruction, distribute the address of the first memory access instruction and the result of the second memory access instruction.

[0143] The address range of the first memory access instruction is [offset0, offset0 + width0], and the address range of the second memory access instruction (i.e., the second memory access instruction) is [offset1, offset1 + width1]. There are generally two situations where address instructions overlap: one is when the addresses of two instructions overlap, such as... Figure 5a and 5b Another situation is where the address range of one instruction completely covers the address range of another instruction, such as... Figures 5c to 5i .by Figure 5a For example, the address range of the merged instruction is [offset0, offset1 + width1]. Figure 5c For example, the address range of the merged instruction is [offset0, offset0 + width0]. Figure 5a For example, the bandwidth of the merged command is offset1 + width1 - offset0. Figure 5c For example, the bandwidth of the merged command after merging is width0.

[0144] In some embodiments, the bandwidth of the merged instruction should be less than or equal to the target bandwidth. If the bandwidth of the merged instruction is greater than the target bandwidth, the first memory access instruction and the second memory access instruction cannot be merged. In other embodiments, the bandwidth of the merged instruction can be greater than the target bandwidth. The merged instruction includes a third memory access instruction and a fourth memory access instruction, wherein the addresses of the third memory access instruction and the fourth memory access instruction are adjacent. The union of the addresses of the first memory access instruction and the second memory access instruction is the first merged address, and the union of the addresses of the third memory access instruction and the fourth memory access instruction is the second merged address. The first merged address and the second merged address are the same.

[0145] The following explains how to select the type of merged instruction based on instruction bandwidth: For memory access instructions of different widths, we refer to the ROCM Instruction Set Architecture (ISA). Instructions are represented by ldg32 / ldg64 / ldg96 / ldg128 to indicate loading data from global memory in 32-bit / 64-bit / 96-bit / 128-bit increments, and by stg32 / stg64 / stg96 / stg128 to indicate storing data into global memory in 32-bit / 64-bit / 96-bit / 128-bit increments. After obtaining the bandwidth of the merged wide instruction using the above method, the corresponding ldg or stg instruction needs to be selected based on the bandwidth. Table 1 shows an example of instruction bandwidth and corresponding instruction types.

[0146] Table 1

[0147] Command bandwidth Instruction type 32 bits / 4 bytes ldg32 / stg32 64bit / 8byte ldg64 / stg64 96bit / 12byte ldg96 / stg96 128bit / 16byte ldg128 / stg128

[0148] The following explains how, based on the processing result of the merged wide instructions, the address of the first memory access instruction and the result of the second memory access instruction are distributed, using the memory access instruction as a load instruction as an example:

[0149] The result of merging the wide instructions is that the data read will be placed into the destination register using the merge instruction, and the data corresponding to the two unmerged narrow instructions will be written back from the destination register to their respective registers.

[0150] For example, the destination register segment [0, width0] is copied to the first register corresponding to the first memory access instruction, and the destination register segment [offset1-offset0, offset1+width1-offset0] is copied to the second register corresponding to the second memory access instruction.

[0151] For example, the first load instruction ldg64r0,r4,0 (where ldg64 indicates loading 64 bits of data, and the first register in the first register to which the data is loaded is identified as r0; since a register stores 32 bits of data, r0 indicates loading data into the first registers r0 and r1, r4 indicates the register type, and 0 indicates a base address of 0×8 bits) and the second load instruction ldg64r2,r4,4 (where ldg64 indicates loading 64 bits of data, and the first register in the second register to which the data is loaded is identified as r2, since...) If a register stores 32 bits of data, then r2 indicates loading data into the first registers r2 and r3, r4 indicates the register type, and 4 indicates a base address of 4 × 8 = 32 bits. This is then combined into the merge instruction ldg96r6,r4,0 (where ldg96 indicates loading 96 bits of data, and the first register in the target register to which the data is loaded is identified as r6; since a register stores 32 bits of data, r4 indicates loading data into the first registers r6, r7, and r8; r4 indicates the register type, and 0 indicates a base address of 0 × 8 bits). The processor, according to ldg96r6,r4,0, stores the read 96 bits of data into r6, r7, and r8. That is, r6, r7, and r8 hold the data loaded by ldg96. The processor then copies the data from r6 and r7 to r0 and r1 respectively according to the first load instruction, and copies the data from r7 and r8 to r2 and r3 respectively according to the second load instruction.

[0152] For example, when the address of the first load instruction covers the address of the second load instruction, and the address width of the merge instruction is the same as the address width of the first load instruction (width0), the data corresponding to the address of the wide instruction (i.e., the merge instruction) can be copied to the first register corresponding to the first memory access instruction, and the [offset1-offset0, offset1+width1-offset0] segment of the first register can be copied to the second register corresponding to the second memory access instruction. For example, ldg128r0,r4,0 (where ldg128 indicates loading 128 bits of data, and the first register in the first register where the data is loaded is identified as r0; since a register stores 32 bits of data, r0 indicates loading data into the first registers r0, r1, r2, and r3; r4 indicates the register type; and 0 indicates a base address of 0×8 bits) and ldg64r12,r4,4 (where ldg64 indicates loading 64 bits of data, and the first register in the second register where the data is loaded is identified as r0) and ldg64r12,r4,4 (where ldg64 indicates loading 64 bits of data, and the first register in the second register where the data is loaded is identified as r0) can be copied to the second register where the data is loaded to the second register. The register is identified as r12. Since a register stores 32 bits of data, r12 indicates that the data is loaded into the first register r12 and r13. r4 indicates the register type, and 4 indicates that the base address is 4×8=32 bits. The instruction is combined into ldg128r0,r4,0. According to the instruction ldg128r0,r4,0, the processor stores the loaded 128 bits of data into r0, r1, r2 and r3. According to the instruction ldg64r12,r4,4, the data in r1 and r2 is copied to r12 and r13.

[0153] For example, when the address of the first load instruction covers the address of the second load instruction, and the address width of the merge instruction is the same as the address width of the first load instruction (width0), the data corresponding to the address of the wide instruction (i.e., the merge instruction) can be copied to the destination register corresponding to the wide address. Then, the [0, width0] segment of the destination register can be copied to the first register corresponding to the first memory access instruction, and the [offset1-offset0, offset1+width1-offset0] segment of the destination register can be copied to the register corresponding to the second memory access instruction.

[0154] By employing a scheme that allows for the merging of memory access instructions with overlapping addresses, the embodiments of this application significantly increase the probability of instruction merging, reduce the number of memory access instructions, and improve instruction bandwidth.

[0155] The following lists the command merging scenarios for different types of two load commands (ldg). It should be noted that the store command (stg) also follows these merging rules:

[0156] Scenario 1: The address ranges of two ldg32 instructions completely overlap, so a single ldg32 instruction is generated.

[0157] Scenario 2: Two ldg32 instructions have base addresses that are 4 bytes (32 bits) apart. The combined bandwidth is equal to 8 bytes (64 bits), i.e. (offset0 + 8 bytes = offset1 + width1), which generates one ldg64 instruction.

[0158] Scenario 3: Two ldg64 addresses completely overlap, directly generating one ldg64 instruction.

[0159] Scenario 4: Merging ldg64 and ldg32:

[0160] If the ldg32 address is completely covered by ldg64, and the ldg32 address range is in the lower 32 bits or the higher 32 bits of ldg64, then an ldg64 instruction is generated directly.

[0161] If the ldg32 address and ldg64 are all adjacent, the combined bandwidth is equal to 12 bytes (96 bits), that is, (offset0 + 12 bytes = offset1 + width1), generating an ldg96 instruction.

[0162] Scenario 5: Merging ldg64+ldg64:

[0163] If the address ranges of two ldg64 instructions completely overlap, a single ldg64 instruction will be generated.

[0164] If two ldg64 addresses overlap, the overlap range is 4 bytes (32 bits), the combined bandwidth is 12 bytes (96 bits = 64 bits + 64 bits - 32 bits), offset0 + 12 bytes = offset1 + width1, generating one ldg96 instruction;

[0165] If the ldg64 address is completely adjacent to ldg64, the combined bandwidth is equal to 16 bytes (128 bits), that is, (offset0 + 16 bytes = offset1 + width1), generating one ldg128 instruction.

[0166] Scenario 6: Merging ldg32 and ldg96:

[0167] If the ldg32 address is completely overwritten by ldg96, generate an ldg96 instruction;

[0168] If the ldg32 address and the ldg96 address are adjacent, the combined bandwidth is equal to 16 bytes (128 bits), generating an ldg128 instruction.

[0169] Scenario 7: Merging ldg64 and ldg96:

[0170] If the ldg64 address is completely overwritten by the ldg96, generate an ldg96 instruction.

[0171] If an ldg64 address overlaps with an ldg96 address, and the ldg64 base address offset is less than the ldg96 base address offset by 4 bytes (32 bits) or greater than the ldg96 base address offset by 8 bytes (64 bits), the merging bandwidth is equal to 16 bytes (128 bits). In this case, it is merged into ldg128.

[0172] If ldg64 addresses and ldg96 addresses are adjacent, they cannot be merged.

[0173] Scenario 8: Merging ldg96+ldg96:

[0174] If the address ranges of two ldg96 instructions completely overlap, a single ldg96 instruction will be generated.

[0175] If the address ranges of two ldg96 instructions overlap, the base address offset between one instruction and the other instruction is 4 bytes (32 bits), and the combined bandwidth is 16 bytes (128 bits), thus forming a single ldg128 address;

[0176] If the address ranges of two ldg96 instructions overlap, and the base address offset between one instruction and the other instruction is greater than or equal to 8 bytes, the merging bandwidth is greater than 16 bytes (128 bits), and they cannot be merged.

[0177] If two ldg96 instructions have adjacent address ranges, they cannot be merged.

[0178] Scenario 9: Merging ldg128 and ldgxx, where ldxx instructions represent ldg32 / ldg64 / ldg96 / ldg128 respectively:

[0179] If the address range of the ldg128 instruction covers the address range of the ldgxx instruction, the combined bandwidth is equal to 16 bytes, and it is combined into a single ldg128 instruction.

[0180] If the bandwidth for merging other scenarios is greater than 16 bytes, merging is not possible.

[0181] In some possible implementations, instructions with a width greater than 128 bits / 16 bytes can also be merged. For example, if an ldg128 instruction and an ldg96 instruction have an address offset 32 ​​bits (or 4 bytes) larger than the address offset of the ldg96 instruction, then their merged instruction would be 20 bytes (160 bits). Theoretically, this is not something that can be merged, but in practice, the 20-byte instruction can be replaced by two adjacent ldg128 and ldg32 instructions. The ldg32 instruction has a lower latency than the ldg96 instruction, which can also improve performance.

[0182] The examples or embodiments of the ldg instruction described above are similar to the stg instruction merging logic, and will not be repeated in this application. The instruction merging logic for accessing shared memory and local memory is similar in this application, and will not be repeated in this application.

[0183] Based on the same inventive concept, this application also provides an instruction processing apparatus for implementing the instruction processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more instruction processing apparatus embodiments provided below can be found in the limitations of the instruction processing method described above, and will not be repeated here.

[0184] In one exemplary embodiment, Figure 7 This is a schematic diagram of the structure of an instruction processing apparatus provided in some embodiments of this application, such as... Figure 7 As shown, the instruction processing device 700 includes:

[0185] The acquisition module 701 is used to acquire the first address information of the first memory access instruction and the second address information of the second memory access instruction when the address of the first memory access instruction and the address of the second memory access instruction overlap.

[0186] The determining module 702 is used to determine the merging base address and merging address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the first address information and the second address information.

[0187] The processing module 703 is used to process the first memory access instruction and the second memory access instruction according to the merge base address and merge address offset of the merge instruction.

[0188] In some embodiments, the determining module 702 includes an overlap type determining unit and a merge address determining unit. The overlap type determining unit is used to determine the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information. The merge address determining unit is used to determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the address overlap type.

[0189] In some embodiments, the overlap type determination unit is further configured to determine the address overlap type as a partial address overlap type when the base address in the first address information is less than the base address in the second address information, the end address in the first address information is greater than the base address in the second address information, and the end address in the first address information is less than the end address in the second address information.

[0190] In some embodiments, the overlap type determination unit is further configured to determine the address overlap type as a full-coverage address overlap type when the base address in the first address information is less than or equal to the base address in the second address information and the end address of the first address information is greater than or equal to the end address of the second address information.

[0191] In some embodiments, the merged address determination unit is further configured to determine the base address in the first address information as the merged base address when the address overlap type is a partial address overlap type and the base address in the first address information is less than the base address in the second address information, add the base address in the first address information and the offset, and then subtract the base address in the second address information to obtain the merged address offset.

[0192] In some embodiments, the merging address determination unit is further configured to determine the base address in the first address information as the merging base address and the offset in the first address information as the merging address offset when the address overlap type is a full coverage address overlap type and the base address in the first address information is less than the base address in the second address information.

[0193] In some embodiments, the processing module includes an instruction type determination unit and an instruction processing unit. The instruction type determination unit is used to determine the instruction type of the merge instruction based on the instruction type of the first memory access instruction and the instruction type of the second memory access instruction. The instruction processing unit is used to process the first memory access instruction and the second memory access instruction based on the instruction type of the merge instruction, the merge base address of the merge instruction, and the merge address offset.

[0194] In some embodiments, the instruction processing unit is further configured to, when the instruction type of the merge instruction indicates that data at the merge address offset is to be loaded, read target data from memory according to the merge base address and the merge address offset of the merge instruction, and process the target data according to the first memory access instruction and the second memory access instruction.

[0195] In some embodiments, the instruction processing unit is further configured to, when the instruction type of the merge instruction indicates data for storing the merged address offset, store the merged data, which is the merged data corresponding to the first address information of the first memory access instruction and the merged data corresponding to the second address information of the second memory access instruction, into the memory according to the merge base address and the merged address offset of the merge instruction.

[0196] In some embodiments, the instruction processing unit includes a first storage subunit, a second storage subunit, and a third storage subunit. The first storage subunit is used to store target data read from memory into a target register according to the merge base address and merge address offset of the merge instruction. The second storage subunit is used to store data corresponding to the first address information in the target register into the first register according to the first memory access instruction. The third storage subunit is used to store data corresponding to the second address information in the target register into the second register according to the second memory access instruction.

[0197] In some embodiments, the instruction processing unit includes a fourth storage subunit and a fifth storage subunit. The fourth storage subunit is used to store target data read from memory into a first register according to the merge base address and merge address offset of the merge instruction and according to the first memory access instruction when the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type and the base address in the first address information is less than the base address in the second address information. The fifth storage subunit is used to store the data corresponding to the second address information stored in the first register into a second register according to the second memory access instruction.

[0198] In some embodiments, the instruction processing unit includes a sixth storage subunit and a seventh storage subunit. The sixth storage subunit is used to overwrite the data to be stored corresponding to the first address information and the data to be stored corresponding to the second address information in the fourth register with the writing order of the data to be stored corresponding to the first address information in the third register and the data to be stored corresponding to the second address information in the fourth register, so that the specified register stores the merged data. The seventh storage subunit is used to store the merged data stored in the specified register into memory according to the merge base address and merge address offset of the merge instruction.

[0199] In some embodiments, the instruction processing unit is further configured to store the data to be stored corresponding to the first address information stored in the third register into the memory according to the merge base address and merge address offset of the merge instruction, provided that the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, the base address in the first address information is less than the base address in the second address information, and the write order of the data to be stored corresponding to the first address information is after the write order of the data to be stored corresponding to the second address information.

[0200] In some embodiments, the instruction processing unit is further configured to, when the writing order of the data to be stored corresponding to the first address information is after the writing order of the data to be stored corresponding to the second address information, determine the data to be stored corresponding to the first address information stored in the third register indicated by the first memory access instruction as the merged data, and store the merged data stored in the third register into the memory according to the merge base address and merge address offset of the merge instruction.

[0201] In some embodiments, the instruction processing unit is further configured to, when the writing order of the data to be stored corresponding to the first address information is before the writing order of the data to be stored corresponding to the second address information, overwrite the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction into the third register indicated by the first memory access instruction for storing the data to be stored corresponding to the first address information, and store the merged data stored in the third register into the memory according to the merge base address and merge address offset of the merge instruction.

[0202] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0203] Each module in the aforementioned instruction processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the electronic device, or stored in software within the memory of the electronic device, so that the processor can call and execute the operations corresponding to each module.

[0204] In one exemplary embodiment, a processor is provided for reading a computer program and for executing the computer program to implement the steps of the methods in any of the above embodiments. In some embodiments, the processor is used to read a computer program from memory, and the processor and memory are separately configured. In other embodiments, the memory is included in the processor; for example, the processor is part of the memory.

[0205] For example, when a processor executes a computer program, it performs the following: if the addresses of the first memory access instruction and the second memory access instruction overlap, it obtains the first address information of the first memory access instruction and the second address information of the second memory access instruction; based on the first address information and the second address information, it determines the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction; and processes the first memory access instruction and the second memory access instruction based on the merge base address and merge address offset of the merge instruction.

[0206] In one exemplary embodiment, an electronic device is provided. Figure 8 This application provides a schematic diagram of the structure of an electronic device according to some embodiments. The electronic device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an instruction processing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the electronic device, or external keyboards, touchpads, or mice, etc.

[0207] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0208] For example, in one exemplary embodiment, the electronic device includes a processor 801. Exemplarily, the electronic device includes a processor 801 and a memory 802.

[0209] The electronic device or instruction processing device in any embodiment of this application may include the integration of one or more of the following: server, mobile phone, tablet computer, computer with wireless transceiver function, handheld computer, desktop computer, personal digital assistant, portable media player, smart speaker, navigation device, smartwatch, smart glasses, smart necklace and other wearable devices, pedometer, digital TV, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, vehicle in vehicle networking system, in-vehicle equipment, in-vehicle module, etc.

[0210] In one embodiment, a computer-readable storage medium is provided, wherein a computer program, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0211] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: when the addresses of a first memory access instruction and a second memory access instruction overlap, obtaining first address information of the first memory access instruction and second address information of the second memory access instruction; determining, based on the first address information and the second address information, a merging base address and a merging address offset of a merging instruction between the first memory access instruction and the second memory access instruction; and processing the first memory access instruction and the second memory access instruction based on the merging base address and the merging address offset of the merging instruction.

[0212] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0213] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0214] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An instruction processing method, characterized in that, The method includes: If the addresses of the first memory access instruction and the second memory access instruction overlap, obtain the first address information of the first memory access instruction and the second address information of the second memory access instruction. Based on the first address information and the second address information, determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction; The first memory access instruction and the second memory access instruction are processed according to the merge base address and merge address offset of the merge instruction.

2. The method according to claim 1, characterized in that, The step of determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes: Based on the first address information and the second address information, determine the address overlap type between the first memory access instruction and the second memory access instruction; Based on the address overlap type, determine the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction.

3. The method according to claim 2, characterized in that, The step of determining the address overlap type between the first memory access instruction and the second memory access instruction based on the first address information and the second address information includes: If the base address in the first address information is less than the base address in the second address information, the end address in the first address information is greater than the base address in the second address information, and the end address in the first address information is less than the end address in the second address information, then the address overlap type is determined to be a partial address overlap type. If the base address in the first address information is less than or equal to the base address in the second address information, and the end address of the first address information is greater than or equal to the end address of the second address information, then the address overlap type is determined to be a full-coverage address overlap type.

4. The method according to claim 2 or 3, characterized in that, The step of determining the merge base address and merge address offset of the merge instruction between the first memory access instruction and the second memory access instruction based on the address overlap type includes: When the address overlap type is a partial address overlap type, and the base address in the first address information is less than the base address in the second address information, the base address in the first address information is determined as the merged base address. The base address in the first address information and the offset are added together, and then the base address in the second address information is subtracted to obtain the merged address offset. If the address overlap type is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, then the base address in the first address information is determined as the merged base address, and the offset in the first address information is determined as the merged address offset.

5. The method according to any one of claims 1 to 3, characterized in that, The step of processing the first memory access instruction and the second memory access instruction based on the merge base address and merge address offset of the merge instruction includes: The instruction type of the merge instruction is determined based on the instruction type of the first memory access instruction and the instruction type of the second memory access instruction. Based on the instruction type, the merge base address, and the merge address offset of the merge instruction, the first memory access instruction and the second memory access instruction are processed.

6. The method according to claim 5, characterized in that, The process of processing the first memory access instruction and the second memory access instruction according to the instruction type, the merge base address, and the merge address offset of the merge instruction includes: When the instruction type of the merge instruction indicates that the data at the merge address offset is loaded, the target data is read from the memory according to the merge base address and the merge address offset of the merge instruction, and the target data is processed according to the first memory access instruction and the second memory access instruction; When the instruction type of the merge instruction indicates that the data to be stored at the merge address offset is to be stored, the merged data, which is the merged data corresponding to the first address information of the first memory access instruction and the merged data corresponding to the second address information of the second memory access instruction, is stored in the memory according to the merge base address and the merge address offset of the merge instruction.

7. The method according to claim 6, characterized in that, The step of reading target data from memory according to the merge base address and merge address offset of the merge instruction, and processing the target data according to the first memory access instruction and the second memory access instruction, includes: According to the merge base address and merge address offset of the merge instruction, the target data read from the memory is stored in the target register; According to the first memory access instruction, the data corresponding to the first address information in the target register is stored in the first register; According to the second memory access instruction, the data corresponding to the second address information in the target register is stored in the second register.

8. The method according to claim 6, characterized in that, The step of reading target data from memory according to the merge base address and merge address offset of the merge instruction, and processing the target data according to the first memory access instruction and the second memory access instruction, includes: If the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the target data read from the memory is stored in the first register according to the merge base address and merge address offset of the merge instruction, and according to the first memory access instruction. According to the second memory access instruction, the data corresponding to the second address information stored in the first register is stored in the second register.

9. The method according to claim 6, characterized in that, The step of storing the merged data—which combines the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction—into memory according to the merge base address and merge address offset of the merge instruction includes: According to the writing order of the data to be stored corresponding to the first address information in the third register indicated by the first memory access instruction and the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction, the data to be stored corresponding to the first address information and the data to be stored corresponding to the second address information are overwritten and stored in the designated register so that the designated register stores the merged data. Based on the merge base address and merge address offset of the merge instruction, the merged data stored in the specified register is stored into the memory.

10. The method according to claim 6, characterized in that, The step of storing the merged data—which combines the data to be stored corresponding to the first address information of the first memory access instruction and the data to be stored corresponding to the second address information of the second memory access instruction—into memory according to the merge base address and merge address offset of the merge instruction includes: If the address overlap type between the first memory access instruction and the second memory access instruction is a full-coverage address overlap type, and the base address in the first address information is less than the base address in the second address information, the merged data stored in the third register indicated by the first memory access instruction is stored in the memory according to the merge base address and merge address offset of the merge instruction.

11. The method according to claim 10, characterized in that, The step of storing the merged data stored in the third register indicated by the first memory access instruction into the memory according to the merge base address and merge address offset of the merge instruction includes: If the writing order of the data to be stored corresponding to the first address information is after the writing order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the first address information stored in the third register indicated by the first memory access instruction is determined as the merged data, and the merged data stored in the third register is stored in the memory according to the merge base address and merge address offset of the merge instruction. If the writing order of the data to be stored corresponding to the first address information is before the writing order of the data to be stored corresponding to the second address information, the data to be stored corresponding to the second address information in the fourth register indicated by the second memory access instruction is overwritten and written into the third register indicated by the first memory access instruction for storing the data to be stored corresponding to the first address information. Then, according to the merging base address and merging address offset of the merging instruction, the merged data stored in the third register is stored in the memory.

12. An instruction processing device, characterized in that, The device includes: The acquisition module is used to acquire the first address information of the first memory access instruction and the second address information of the second memory access instruction when the address of the first memory access instruction and the address of the second memory access instruction overlap. The determining module is used to determine the merging base address and merging address offset of the merging instruction between the first memory access instruction and the second memory access instruction based on the first address information and the second address information; The processing module is used to process the first memory access instruction and the second memory access instruction according to the merge base address and merge address offset of the merge instruction.

13. A processor, characterized in that, The processor is used to execute computer programs to implement the steps of the method according to any one of claims 1 to 11.

14. An electronic device, characterized in that, The electronic device includes the processor of claim 13.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

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