100g network-based rapid prototyping method, device and storage medium

Abstract

This application relates to the field of prototyping technology, and discloses a rapid prototyping method, device, and storage medium based on a 100G network. In a NoC using a 2D Torus topology, a data synchronization module is set up for each routing node to capture data communication packets in all directions and the node's internal register status in real time, and cache them locally. Multiple routing nodes are grouped together and share a high-speed 100G network module. Through register configuration, the host dynamically selects specific routing nodes, controls the 100G network module to read the cached data of the selected nodes in a round-robin manner, and encapsulates it into network packets with timestamps, node location, and direction markers. These packets are then transmitted in real time to the host via a 100G high-speed link for parsing, visualization, and reconstruction. This solves the problems of insufficient comprehensive monitoring of on-chip network internal signals and insufficient bandwidth of traditional probes in existing large-scale SoC prototyping.

Description

Technical Field

[0001] This application relates to the field of prototype verification technology, and for example to a rapid prototype verification method, device and storage medium based on a 100G network. Background Technology

[0002] With the rapid development of integrated circuit technology, the complexity of system-on-a-chip (SoC) is increasing exponentially, with the number of integrated functional modules constantly increasing and the interactions between modules becoming increasingly complex. Prototype verification, as a key step in the chip design process, undertakes the important task of verifying the correctness of chip functions and the rationality of performance indicators, directly affecting the chip's R&D cycle and the quality of the final product.

[0003] In large-scale SoC integration, on-chip network (NoC) architecture is widely used to connect different internal functional nodes, enabling data communication and interaction between nodes. The reliability of the NoC architecture design directly impacts the overall chip performance reliability. The parallel and cross-communication of numerous routing nodes introduces deadlock and routing blockage issues into the NoC's routing state. The large number of on-chip network routing nodes and the significant randomness of communication make it difficult to predict the state information of different nodes, requiring extensive communication and state monitoring at different times. Simultaneously, the limited number of probes in prototype verification systems prevents simultaneous acquisition and monitoring of all critical signal lines, creating signal acquisition blind spots during verification. This makes it difficult to comprehensively capture communication details and abnormal states between nodes, thus affecting the completeness and reliability of verification results and posing a significant challenge to chip functional verification.

[0004] Therefore, existing large-scale SoC prototype verification suffers from problems such as difficulty in fully monitoring signals inside the network-on-chip (NoC) and insufficient bandwidth derived by traditional probes.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] The rapid prototyping method, device, and storage medium based on 100G networks provided in this disclosure can solve the problems of difficulty in fully monitoring signals inside the network-on-chip (NoC) and insufficient bandwidth of traditional probes in existing large-scale SoC prototyping.

[0008] This disclosure provides a rapid prototyping method based on a 100G network. This method, applied to a system-on-a-chip (SoC) prototyping system, may include: The 2D Torus on-chip network architecture connects different functional nodes within the SoC to perform data transfer between nodes; Based on the data synchronization module set in each routing node, all data packets sent by the corresponding routing node to other nodes and the status information of the routing node are synchronized, and the data packets and status information are stored in the corresponding buffer. Multiple routing nodes share a 100G network module, and the buffer is interconnected with the 100G network module. By configuring the registers, the 100G network module can select the buffers of one or more specified routing nodes, read the communication information in the buffers, encapsulate the communication information into network packets, and send them to the host for parsing.

[0009] In some embodiments, the above-mentioned synchronization of all data packets sent by the corresponding routing node to other nodes and the status information of the routing node itself, and the storage of the data packets and status information in the corresponding buffer, includes: Based on the data synchronization module, the data buses in the four directions of the routing node are connected, and the status of all registers inside the corresponding routing node is read. Forward the configuration information of the 100G network module, select the current routing node, and open the data path between the routing node and the buffer. In strobed mode, starting from the next complete data packet, all data packets received and sent by the corresponding routing node are synchronized to the buffer.

[0010] In some embodiments, the above-mentioned buffer area includes at least 8 independent cache RAMs, which respectively correspond to the cached data packets received and sent in the four directions of the routing node; When caching data packets, the current period counter value is added to the beginning of the data packet to mark the time when the data packet was generated.

[0011] In some embodiments, when the data synchronization module receives the register status read configuration, it controls the routing node to read all its internal registers and writes the register status data directly to the 100G network module in a bypass manner with the highest priority, and forwards it to the host first.

[0012] In some embodiments, the process of the 100G network module performing data reading includes: Receive configuration parameters sent by the host and forward the configuration information of node selection, node shutdown or register reading to the corresponding routing node; Upon receiving the node selection configuration, a polling method is used to monitor each cache RAM. When the amount of data in the cache RAM is greater than or equal to one data packet, it is read, packaged into a network packet, and sent to the host. If a node is found to be in a closed configuration state, the corresponding node's buffer will be reset after reading the current data packet, and data monitoring will be stopped.

[0013] In some embodiments, the 100G network module adds tagging information to each data packet when packaging network packets; The marking information includes the location identifier of the corresponding routing node, the bus direction corresponding to the data packet, and the transmission type of the data packet, which is either receiving or sending.

[0014] In some embodiments, the above-described prototype verification system includes multiple prototype verification boards, and a single SoC project is divided and distributed to different prototype verification boards; each prototype verification board includes multiple routing nodes and an independent 100G network module, and the 100G network module of each board is connected to the host.

[0015] In some embodiments, the host is equipped with network packet parsing software, which is used to parse the received network packets, display the register data in a list format, and combine the network packets in the order of their corresponding generation time into a timing diagram for visualization.

[0016] This disclosure provides an electronic device that includes at least one processor; and memory that is communicatively connected to at least one processor; The memory stores instructions that can be executed by at least one processor to enable the processor to perform the aforementioned rapid prototyping method based on a 100G network.

[0017] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the aforementioned rapid prototyping verification method based on a 100G network.

[0018] The rapid prototyping method, device, and storage medium based on 100G networks provided in this disclosure can achieve the following technical effects: This disclosure, within a NoC employing a 2D Torus topology, establishes a data synchronization module for each routing node to capture data communication packets in all directions and the node's internal register status in real time, caching them locally. Multiple routing nodes are grouped together, sharing a high-speed 100G network module. Through register configuration, the host dynamically selects specific routing nodes, controlling the 100G network module to read the selected node's cached data in a round-robin manner. This data is then encapsulated into network packets with timestamps, node location, and direction markers, and transmitted in real-time to the host via a 100G high-speed link for parsing, visualization, and reconstruction. This innovatively transforms high-speed Ethernet technology into an ultra-high-bandwidth "virtual logic analyzer channel" in the chip verification system, enabling periodic, configurable, and non-intrusive real-time monitoring of massive communication signals within the complex NoC. This overcomes the absolute limitation of the number of physical probes, allowing verification personnel to observe dynamic behaviors such as network congestion and deadlocks in a panoramic view, greatly improving the efficiency and depth of problem localization, thereby significantly shortening the SoC prototype verification cycle and enhancing the reliability and integrity of system-level verification.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a flowchart illustrating a rapid prototyping method based on a 100G network provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of an on-chip interconnection network with multiple 100G network modules provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a 100G network communication module that supports data synchronization configuration and read / write strobe, provided in an embodiment of this disclosure. Figure 4 This is a schematic diagram of a connection method for configuring and synchronizing routing nodes according to an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a rapid prototyping device based on a 100G network provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more.

[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] To address the aforementioned issues, this disclosure provides a rapid prototyping method, device, and storage medium based on a 100G network.

[0028] The rapid prototyping method, device, and storage medium based on a 100G network provided in this disclosure will be described below with reference to the accompanying drawings.

[0029] Figure 1 This is a flowchart illustrating a rapid prototyping method based on a 100G network provided in an embodiment of this disclosure.

[0030] Combination Figure 1 As shown, a rapid prototyping method for a system-on-a-chip (SoC) prototype verification system may include: S101 connects different functional nodes within the SoC through a 2D Torus on-chip network architecture to perform data transfer between nodes; S102, based on the data synchronization module set in each routing node, synchronizes all data packets sent by the corresponding routing node to other nodes and the status information of the routing node itself, and stores the data packets and status information in the corresponding buffer. Multiple routing nodes share a 100G network module, and the buffer is interconnected with the 100G network module. S103, through register configuration, controls the 100G network module to select the buffer of one or more specified routing nodes, read the communication information in the buffer, encapsulate the communication information into network packets and send them to the host for parsing.

[0031] In some embodiments, the above-mentioned synchronization of all data packets sent by the corresponding routing node to other nodes and the status information of the routing node itself, and the storage of the data packets and status information in the corresponding buffer, includes: Based on the data synchronization module, the data buses in the four directions of the routing node are connected, and the status of all registers inside the corresponding routing node is read. Forward the configuration information of the 100G network module, select the current routing node, and open the data path between the routing node and the buffer. In strobed mode, starting from the next complete data packet, all data packets received and sent by the corresponding routing node are synchronized to the buffer.

[0032] In some embodiments, the above-mentioned buffer area includes at least 8 independent cache RAMs, which respectively correspond to the cached data packets received and sent in the four directions of the routing node; When caching data packets, the current period counter value is added to the beginning of the data packet to mark the time when the data packet was generated.

[0033] In some embodiments, when the data synchronization module receives the register status read configuration, it controls the routing node to read all its internal registers and writes the register status data directly to the 100G network module in a bypass manner with the highest priority, and forwards it to the host first.

[0034] In some embodiments, the process of the 100G network module performing data reading includes: Receive configuration parameters sent by the host and forward the configuration information of node selection, node shutdown or register reading to the corresponding routing node; Upon receiving the node selection configuration, a polling method is used to monitor each cache RAM. When the amount of data in the cache RAM is greater than or equal to one data packet, it is read, packaged into a network packet, and sent to the host. If a node is found to be in a closed configuration state, the corresponding node's buffer will be reset after reading the current data packet, and data monitoring will be stopped.

[0035] In some embodiments, the 100G network module adds tagging information to each data packet when packaging network packets; The marking information includes the location identifier of the corresponding routing node, the bus direction corresponding to the data packet, and the transmission type of the data packet, namely, receiving or sending.

[0036] In some embodiments, the above-described prototype verification system includes multiple prototype verification boards, and a single SoC project is divided and distributed to different prototype verification boards; each prototype verification board includes multiple routing nodes and an independent 100G network module, and the 100G network module of each board is connected to the host.

[0037] In some embodiments, the host is equipped with network packet parsing software, which is used to parse the received network packets, display the register data in a list format, and combine the network packets in the order of their corresponding generation time into a timing diagram for visualization.

[0038] Figure 2 This is a schematic diagram of an on-chip interconnect network with multiple 100G network modules provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of a 100G network communication module that supports data synchronization configuration and read / write strobe, provided in an embodiment of this disclosure. Figure 4 This is a schematic diagram illustrating a connection method for configuring and synchronizing routing nodes according to an embodiment of this disclosure. Figures 2 to 4 ,right Figure 1 The rapid prototyping method based on 100G networks is further described in this paper.

[0039] (1) The data synchronization module synchronizes the data and status signals of the routing nodes. The data synchronization module connects to all data buses in all four directions of the routing node and can read the status of all registers inside the node, such as... Figure 4 As shown, the data synchronization module forwards the configuration information of the 100G network module, selects the current node, and opens the data path between the route and the node cache.

[0040] After receiving the strobe configuration, the routing node will synchronize all received and sent data packets to the node buffer starting from the next complete data packet, waiting for forwarding by the 100G network interface module.

[0041] The node synchronization module contains eight independent buffer RAMs, which respectively buffer received and transmitted data packets in four directions, providing support for data analysis by the host computer. When buffering data packets, a current cycle counter is cached at the beginning of each data packet to mark its generation time.

[0042] After receiving the register status read configuration, the data synchronization module controls the routing node to read all its internal registers and then reads them in a fixed order from the routing node reading unit of the 100G network interface module. Register status reads have the highest priority and are bypassed by directly writing to the node's cache unit, prioritizing forwarding to the host.

[0043] When the data synchronization module receives the strobe-off configuration, it configures the registers of the routing node and shuts down the synchronization bus.

[0044] Preferably, the data synchronization module can be configured with selectable channels, choosing only a portion of the bus routed by the nodes to reduce data uploads and facilitate upper-layer data analysis.

[0045] (2) The 100G network module reads and writes data. The 100G network module receives configuration parameters from the host computer and forwards the node enable / disable and register read configuration information to the corresponding routing nodes through the routing node configuration module, such as... Figure 3 As shown. After receiving the node selection configuration, the 100G network module starts monitoring the node cache module of the corresponding routing node. The routing node reading module adopts a polling method, reading the eight cache RAMs in the cache module in a round-robin fashion. If data is detected in the current cache RAM and the data volume is greater than or equal to one data packet, it starts reading, packs it into a network packet, and sends it to the host; otherwise, it jumps directly to the next cache RAM and starts monitoring again.

[0046] After receiving the node's shutdown configuration, the 100G network module reads the current data packet, resets the current node's cache module, and disables data monitoring of the current node.

[0047] Preferably, when configuring the routing node part of the bus selection on the host side, the routing node reading module only polls the cache RAM corresponding to the selected bus.

[0048] Preferably, when the host computer configures multiple nodes to be selected simultaneously, the routing node reading module reads data from multiple routing nodes using a round-robin method.

[0049] Preferably, when packaging network packets, the 100G network module will mark the location of the network node corresponding to the current data packet, as well as the bus direction and receive / transmit type of the routing node.

[0050] Preferably, the 100G network communication module can be changed to a 200G / 400G network communication module depending on the selected prototype verification board model, thereby improving the interface speed with the host and the number of routing nodes that can be selected simultaneously.

[0051] (3) Multiple routing nodes correspond to a single 100G network interface module The prototype verification process utilizes multiple prototype verification boards, with a single SoC project distributed across different verification boards through project partitioning. Multiple routing nodes share the same 100G network module, such as... Figure 2 As shown, multiple routing nodes and a shared 100G network module are split into the same prototype verification board, and each prototype verification board has an independent 100G network module.

[0052] The 100G network module connects to a host computer, which installs network packet parsing software to parse the currently received data packets. Upon receiving a register data packet, the module lists and displays the registers according to their node location and register type. Upon receiving a data network packet, the module combines the data packets into a timing diagram based on the data validity signal method and the corresponding generation time of the data packet, making it convenient for the user to view.

[0053] It should be further explained that the rapid prototyping verification method based on 100G network provided in this disclosure includes a 2DTorus on-chip network architecture for connecting different functional nodes within the SoC, supporting rapid data transfer between different functional nodes; a data synchronization module for routing nodes, which synchronizes all data sent by the routing node to other nodes, as well as the status information of the routing node itself, and sends it to the buffer; routing nodes in a specified area share a 100G network module, and multiple buffers are interconnected with the 100G network module; through register configuration, the 100G network module reads the buffers of one or more specified routing nodes, reads all communication information of the routing nodes, and sends it to the host in the form of network packets for data parsing.

[0054] This invention addresses the industry problem of insufficient comprehensive monitoring of signals within Network-on-Chip (NoC) during large-scale SoC prototyping, and the severe bandwidth limitations of traditional probes. It proposes an innovative signal extraction and monitoring method: a rapid prototyping method based on a 100G network. The core of its technical solution lies in: in a NoC employing a 2D Torus topology, a data synchronization module is set up for each routing node to capture data communication packets in all directions and the node's internal register status in real time, and cache them locally; multiple routing nodes are grouped together, sharing a high-speed 100G network module; through register configuration, the host dynamically selects specific routing nodes, controlling the 100G network module to read the cached data of the selected nodes in a round-robin manner, encapsulating it into network packets with timestamps, node location, and direction markers, and transmitting them in real time to the host for parsing, visualization, and reconstruction via a 100G high-speed link.

[0055] The technical advantage of this solution lies in its innovative transformation of high-speed Ethernet technology into an ultra-high bandwidth "virtual logic analyzer channel" within the chip verification system. This enables periodic, configurable, and non-intrusive real-time monitoring of massive communication signals within complex NoC (System-on-Chips). This overcomes the absolute limitation on the number of physical probes, allowing verification personnel to observe dynamic behaviors such as network congestion and deadlocks in a panoramic manner. This significantly improves the efficiency and depth of problem localization, thereby significantly shortening the SoC prototype verification cycle and enhancing the reliability and integrity of system-level verification.

[0056] Furthermore, multiple routing nodes share a single 100G network module, enabling real-time monitoring of effective communication data and status change data of any routing node. This provides more periodic signal monitoring methods for the prototype verification process of on-chip interconnect networks, improving the system-level prototype verification rate of on-chip interconnect networks. The effective monitoring of more signals provides visualized monitoring of the system execution process and offers more controllable status displays for congestion and other status issues in on-chip network communication, thus providing effective references for problem optimization.

[0057] This invention achieves efficient extraction of a large number of key signals in the on-chip interconnect network architecture through minimal consumption of logic resources and 100G network communication during the prototype verification process of SoC. It realizes periodic signal variation monitoring equivalent to probe signals, providing more signal monitoring methods for the prototype verification process of on-chip interconnect networks, improving the efficiency of problem localization, and thus improving the system efficiency of SoC prototype verification.

[0058] Combination Figure 5 As shown in the illustration, this disclosure also provides a rapid prototyping device 500 based on a 100G network, including a processor 504 and a memory 501. Optionally, the system may further include a communication interface 502 and a bus 503. The processor 504, communication interface 502, and memory 501 can communicate with each other via the bus 503. The communication interface 502 can be used for information transmission. The processor 504 can call logical instructions in the memory 501 to execute the rapid prototyping method based on a 100G network described in the above embodiments.

[0059] Furthermore, the logic instructions in the aforementioned memory 501 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0060] The memory 501, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 504 executes functional applications and data processing by running the program instructions / modules stored in the memory 501, thereby realizing the rapid prototyping method based on a 100G network in the above embodiments.

[0061] The memory 501 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 501 may include high-speed random access memory and may also include non-volatile memory.

[0062] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured as a rapid prototyping method based on a 100G network.

[0063] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0064] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0065] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0067] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0068] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0069] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0070] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0071] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0072] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0073] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0074] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0075] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0076] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A rapid prototyping method based on a 100G network, characterized in that, A prototype verification system for system-on-a-chip (SoC), the method comprising: The 2D Torus on-chip network architecture connects different functional nodes within the SoC to perform data transfer between nodes; Based on the data synchronization module set in each routing node, all data packets sent by the corresponding routing node to other nodes and the status information of the routing node are synchronized, and the data packets and status information are stored in the corresponding buffer. Multiple routing nodes share a 100G network module, and the buffer is interconnected with the 100G network module. By configuring the registers, the 100G network module can select the buffers of one or more specified routing nodes, read the communication information in the buffers, encapsulate the communication information into network packets, and send them to the host for parsing.

2. The method according to claim 1, characterized in that, The process of synchronizing all data packets sent by the corresponding routing node to other nodes and the status information of the current routing node, and storing the data packets and status information in the corresponding buffer, includes: Based on the data synchronization module, the data buses in the four directions of the routing node are connected, and the status of all registers inside the corresponding routing node is read. Forward the configuration information of the 100G network module, select the current routing node, and open the data path between the routing node and the buffer. In strobed mode, starting from the next complete data packet, all data packets received and sent by the corresponding routing node are synchronized to the buffer.

3. The method according to claim 2, characterized in that, The buffer area includes at least 8 independent cache RAMs, which respectively cache the received data packets and sent data packets in the four directions of the routing node; When caching data packets, the current period counter value is added to the beginning of the data packet to mark the time when the data packet was generated.

4. The method according to claim 2, characterized in that, When the data synchronization module receives the register status read configuration, it controls the routing node to read all its internal registers and writes the register status data directly to the 100G network module in a bypass manner with the highest priority, and forwards it to the host first.

5. The method according to claim 1, characterized in that, The process of the 100G network module performing data reading includes: Receive configuration parameters sent by the host and forward the configuration information of node selection, node shutdown or register reading to the corresponding routing node; Upon receiving the node selection configuration, a polling method is used to monitor each cache RAM. When the amount of data in the cache RAM is greater than or equal to one data packet, it is read, packaged into a network packet, and sent to the host. If a node is found to be closed, the corresponding node's buffer will be reset after reading the current data packet, and data monitoring will be stopped.

6. The method according to claim 5, characterized in that, When packaging network packets, the 100G network module adds tagging information to each data packet. The marking information includes the location identifier of the corresponding routing node, the bus direction corresponding to the data packet, and the transmission type of the data packet, which is either receiving or sending.

7. The method according to claim 1, characterized in that, The prototype verification system includes multiple prototype verification boards. A single SoC project is divided and distributed to different prototype verification boards. Each prototype verification board includes multiple routing nodes and an independent 100G network module. The 100G network module of each board is connected to the host.

8. The method according to claim 1, characterized in that, The host is equipped with network packet parsing software, which is used to parse the received network packets, display the register data in a list format, and combine the network packets in the order of their corresponding generation time into a timing diagram for visualization.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

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