A voltage division offset compensation control circuit and method

Abstract

The application discloses a voltage division offset compensation control circuit and a voltage division offset compensation method. The voltage division offset compensation control circuit comprises: a voltage stabilizing circuit, which is used for sampling an output voltage VO to form a feedback voltage signal, comparing the feedback voltage signal with a reference voltage VREF, and generating an adjustment control signal to adjust the output voltage VO. A compensation circuit is connected with a feedback node of the voltage stabilizing circuit, used for generating a compensation current IX based on the change of the output voltage VO, and injecting the compensation current IX into the feedback node of the voltage stabilizing circuit to offset the voltage division offset caused by the change of the output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages. The application can eliminate the resistance voltage division error caused by the change of the output voltage in the voltage stabilizing circuit, and ensure the high-precision output of the voltage stabilizing circuit.

Description

Technical Field

[0001] This invention relates to the field of analog circuit design, and in particular to a voltage divider offset compensation control circuit and method. Background Technology

[0002] A resistor-based voltage divider control circuit typically consists of two or more resistors connected in series. It achieves proportional voltage division from input voltage to output voltage by fixing the resistance ratio. When an input voltage is applied across the resistor network, the potentials at each voltage divider node are linearly distributed according to the resistance ratio, thus obtaining the required reference voltage.

[0003] However, the output voltage and voltage division ratio are susceptible to factors such as temperature drift, input voltage fluctuations, load changes, and aging. By introducing additional components and feedback mechanisms, the effects of these interference factors on the output voltage and voltage division ratio can be offset, ensuring high accuracy of the output voltage and maintaining the stability of the voltage division ratio. However, this approach requires more components, resulting in a complex layered circuit structure and poor stability under environmental changes, which is not conducive to low power consumption and convenient design. Furthermore, as the output voltage increases, the actual resistor voltage division value changes linearly with the increase of the output voltage, leading to a decrease in accuracy as the output voltage increases. Summary of the Invention

[0004] The purpose of this invention is to achieve a stable resistor voltage divider value in the voltage regulator circuit, and to design a compensation current through a voltage divider offset compensation control circuit when the output voltage changes, so as to ensure that the resistor voltage divider value error is eliminated, and to enable the external voltage regulator circuit to obtain a high-precision output when the output voltage changes.

[0005] To achieve the above objectives, the present invention discloses the following technical solution: A first aspect of the present invention provides a voltage divider offset compensation control circuit, comprising: A voltage regulator circuit is used to divide and sample the output voltage VO to form a feedback voltage signal, and compare the feedback voltage signal with the reference voltage VREF to generate an adjustment control signal to adjust the output voltage VO. A compensation circuit, connected to the feedback node of the voltage regulator circuit, is used to generate a compensation current IX based on the change in the output voltage VO, and inject the compensation current IX into the feedback node of the voltage regulator circuit to counteract the voltage division offset caused by the change in the output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages.

[0006] Optionally, the compensation circuit includes: A reference current generation module is connected to the reference voltage VREF and is used to generate a reference current based on the reference voltage VREF. The first current mirror module is connected to the reference current generation module and is used to perform current mirror copying of the reference current; The compensation current generation module is connected to the first current mirror module and the feedback node of the voltage regulator circuit, respectively, and is used to generate the compensation current IX and inject it into the feedback node of the voltage regulator circuit.

[0007] Optionally, the reference current generation module includes a first MOS transistor M1, a first resistor R1, and a first operational amplifier AMP1; The first end of the first resistor R1 is connected to the source of the first MOSFET M1, and the second end is grounded; The non-inverting input of the first operational amplifier AMP1 is connected to the reference voltage VREF, the inverting input is connected to the first end of the first resistor R1, the output is connected to the gate of the first MOS transistor M1, and the drain of the first MOS transistor M1 is connected to the first current mirror module.

[0008] Optionally, the first current mirror module includes a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4; The sources of the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are all connected to the power supply voltage VDD. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The drains of the third MOSFET M3 and the fourth MOSFET M4 are all connected to the compensation current generation module. The gates of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are all connected and are connected to the source of the second MOS transistor M2.

[0009] Optionally, the compensation current generation module includes: The collector of the first transistor Q1 is connected to the drain of the third MOS transistor M3; The collector of the second transistor Q2 is connected to the drain of the fourth MOS transistor M4, the emitter is grounded, and the base is connected to the emitter of the first transistor Q1. The collector of the third transistor Q3 is connected to the feedback node of the voltage regulator circuit, and its base is connected to the base of the first transistor Q1 and connected to the bias current IBIAS. The fourth transistor Q4 has its collector connected to the reference current IREF, its emitter grounded, and its base connected to the emitter of the third transistor Q3. The fifth MOSFET M5 has its source grounded, its drain connected to the emitter of the first transistor Q1, and its gate connected to the first bias voltage VBIAS1. The sixth MOS transistor M6 has its source grounded, its drain connected to the emitter of the third transistor Q3, and its gate connected to the second bias voltage VBIAS2.

[0010] Optionally, the compensation circuit further includes: The second current mirror module is connected at one end to the compensation current generation module and at the other end to the feedback node of the voltage regulator circuit, and is used to replicate and output the compensation current.

[0011] Optionally, the second current mirror module includes a seventh MOSFET M7 and an eighth MOSFET M8; The sources of the seventh MOSFET M7 and the eighth MOSFET M8 are both connected to the power supply voltage VDD. The drain of the seventh MOSFET M7 is connected to the collector of the third transistor Q3, and the drain of the eighth MOSFET M8 is connected to the feedback node of the voltage regulator circuit. The gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected and are also connected to the source of the seventh MOS transistor M7.

[0012] Optionally, the voltage regulator circuit includes a second resistor R2, a third resistor R3, and a second operational amplifier AMP2; The output voltage VO is grounded through the second resistor R2 and the third resistor R3 in sequence, and the node between the second resistor R2 and the third resistor R3 serves as the feedback node of the voltage regulator circuit. The non-inverting input of the second operational amplifier AMP2 is connected to the reference voltage VREF, the inverting input is connected to the feedback node of the voltage regulator circuit, and the output terminal outputs the adjustment control signal.

[0013] Secondly, the present invention provides a voltage divider offset compensation method, comprising the following steps: The output voltage VO is divided and sampled to obtain the feedback voltage signal; A compensation current IX is generated based on the change in the output voltage VO; The compensation current IX is injected into the feedback node of the voltage regulator circuit to counteract the voltage division offset caused by the change in the output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages. An adjustment control signal is generated based on the feedback voltage signal and the compensation current IX, and the output voltage VO is adjusted according to the adjustment control signal.

[0014] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects: The voltage divider offset compensation control circuit provided in this application embodiment achieves closed-loop voltage regulation and voltage divider offset compensation for the output voltage by separately setting a voltage regulator circuit and a compensation circuit. This scheme can generate a corresponding compensation current according to the change of output voltage VO, thereby offsetting the feedback voltage divider deviation caused by the change of output voltage VO, and thus enabling the feedback signal IX to maintain a stable voltage divider ratio under different output voltages, effectively improving voltage regulation accuracy and system stability.

[0015] Furthermore, by setting a reference current generation module, a first current mirror module, a compensation current generation module, and a second current mirror module in the compensation circuit, a stable reference current based on the reference voltage VREF is achieved, and a compensation current IX that is precisely related to the output voltage VO change is generated accordingly. This structure can dynamically adjust the injected compensation current IX when the feedback node voltage shifts with the output voltage change, so that the feedback voltage division relationship maintains the expected proportional consistency under different operating states, thereby effectively improving the voltage accuracy and stability of the voltage regulator circuit across the entire output range.

[0016] Furthermore, by flexibly changing the implementation method of the compensation current, the error in the resistor voltage division value is stably eliminated when the linear direction of the voltage division ratio of the voltage regulator circuit changes. This design can flexibly adjust the compensation current path according to the linear direction of the voltage division ratio, so that the feedback node can achieve the compensation function in different directions, thereby maintaining a constant voltage division ratio and stable output, and thus improving the accuracy of the voltage regulator circuit during output voltage changes. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0018] Figure 1 This illustrates a typical parallel voltage regulator circuit; Figure 2 The curve showing the relationship between the resistor voltage division ratio and the output voltage is shown. Figure 3 A structural diagram of a voltage divider offset compensation control circuit according to an embodiment of the present invention is shown; Figure 4 A circuit topology diagram of a voltage divider offset compensation control circuit according to an embodiment of the present invention is shown; Figure 5 A circuit topology diagram of a voltage divider offset compensation control circuit according to another embodiment of the present invention is shown; Figure 6 A comparison diagram of the partial voltage coefficients before and after compensation according to an embodiment of the present invention is shown; Figure 7A comparison diagram of voltage accuracy before and after compensation according to an embodiment of the present invention is shown; Figure 8 A flowchart of a voltage divider offset compensation method according to an embodiment of the present invention is shown.

[0019] In the diagram: 1-Voltage regulator circuit, 2-Compensation circuit, 21-Reference current generation module, 22-First current mirror module, 23-Compensation current generation module, 24-Second current mirror module. Detailed Implementation

[0020] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Figure 1 A typical parallel voltage regulator circuit is shown. For example... Figure 1 As shown, the feedback voltage V FB Output voltage V O The voltage divider voltage is also the inverting input voltage of the op-amp, V. FB With reference voltage V REF After differential amplification by operational amplifier AMP3, the output voltage VO is controlled by adjusting the voltage drop across resistor R6 at its output terminal, thereby achieving the desired output voltage V. O Always stable at However, in actual circuits, the equivalent voltage division ratio of a voltage divider network is not strictly constant and will shift with changes in the output voltage VO, causing the feedback voltage VFB to deviate from its theoretical voltage division value, thus affecting the voltage regulation accuracy.

[0022] Figure 2 The curve showing the relationship between the resistor voltage division ratio and the output voltage VO is illustrated. Figure 2 As shown, the horizontal axis represents the output voltage V. O The vertical axis represents the resistor voltage division ratio. Due to process limitations, the resistor voltage division ratio changes linearly as the output voltage increases. Figure 3 The relationship curve in the middle shows that ; in Due to the factors mentioned above, for voltage systems requiring high output accuracy (e.g., ±1% or higher), the higher the output voltage VO, the more pronounced the voltage accuracy deviation usually becomes. For applications with a single output voltage, where the reference voltage VREF corresponds to a unique fixed value, VREF can be adjusted to allow the feedback voltage divider network to achieve matching compensation at that specific output point. This corrects the error caused by the voltage divider offset, enabling the output voltage VO to achieve the expected accuracy.

[0023] However, in multi-output voltage systems, the reference voltage VREF is typically externally programmable to adapt to different target output voltages. Since each output voltage VO corresponds to a different voltage division ratio, the offset generated by the resistor network at different output points also varies. Therefore, simply adjusting the reference voltage VREF can only achieve error compensation for a specific output point and cannot be applied simultaneously across the entire voltage range. In other words, a fixed adjustment amount cannot match multiple different voltage division offset characteristics, causing the system to be unable to maintain high accuracy simultaneously across all output voltage levels.

[0024] Therefore, it is evident that in existing technologies, the voltage division ratio shifts with changes in output voltage, leading to unstable feedback sampling and making it difficult for the voltage regulator circuit to simultaneously achieve consistent voltage accuracy across multiple voltage ranges. To address these issues, this invention proposes a voltage division offset compensation control scheme that can suppress voltage division offset and improve the consistency of multi-voltage outputs.

[0025] Figure 3 A structural block diagram of a voltage divider offset compensation control circuit according to an embodiment of the present invention is shown. Figure 3 As shown, the voltage divider offset compensation control circuit includes a voltage regulator circuit and a compensation circuit. The voltage regulator circuit samples the output voltage VO to form a feedback voltage signal, compares the feedback voltage signal with the reference voltage VREF, and generates an adjustment control signal to adjust the output voltage VO. The compensation circuit is connected to the feedback node of the voltage regulator circuit and generates a compensation current IX based on the change in output voltage VO. This compensation current IX is injected into the feedback node of the voltage regulator circuit to counteract the voltage divider offset caused by the change in output voltage VO, ensuring that the feedback signal maintains a constant voltage division ratio under different output voltages.

[0026] According to the above embodiments, by setting up a voltage regulator circuit and a compensation circuit respectively, closed-loop voltage regulation and voltage division offset compensation of the output voltage VO are achieved. This scheme can generate a corresponding compensation current IX according to the change of output voltage VO, thereby offsetting the feedback voltage division deviation caused by the change of output voltage VO, and thus enabling the feedback signal to maintain a stable voltage division ratio under different output voltages, effectively improving voltage regulation accuracy and system stability.

[0027] In some embodiments, reference Figure 3 The compensation circuit includes a reference current generation module, a first current mirror module, and a compensation current generation module. The reference current generation module is connected to a reference voltage VREF and is used to generate a reference current based on VREF. The first current mirror module is connected to the reference current generation module and is used to mirror the reference current. The compensation current generation module is connected to the first current mirror module and the feedback node of the voltage regulator circuit, respectively, and is used to generate a compensation current IX and inject it into the feedback node of the voltage regulator circuit.

[0028] In this embodiment, the operating sequence of each module in the compensation circuit is clear and they cooperate with each other. The reference current generation module first generates a stable current based on the reference voltage VREF, providing a current reference for the compensation link. This current is replicated with consistent amplitude by the first current mirror module and then sent to the compensation current generation module. The compensation current generation module constructs a compensation current IX related to the output voltage change based on the mirrored current and injects it into the feedback node of the voltage regulator circuit, so that the voltage of this node maintains a predetermined voltage division ratio under different output voltage conditions.

[0029] According to the above embodiments, by setting a reference current generation module, a first current mirror module, a compensation current generation module, and a second current mirror module in the compensation circuit, a stable reference current based on the reference voltage VREF is realized, and a compensation current IX that is precisely related to the change in the output voltage VO is generated accordingly. This structure can dynamically adjust the injected compensation current IX when the feedback node voltage shifts with the change in output voltage, so that the feedback voltage division relationship maintains the expected proportional consistency under different operating states, thereby effectively improving the voltage accuracy and stability of the voltage regulator circuit across the entire output range.

[0030] Figure 4 A circuit topology diagram of a voltage divider offset compensation control circuit according to an embodiment of the present invention is shown. Figure 4 As shown, the voltage regulator circuit includes a second resistor R2, a third resistor R3, and a second operational amplifier AMP2. The output voltage VO is grounded sequentially through the second resistor R2 and the third resistor R3. The node between the second resistor R2 and the third resistor R3 serves as the feedback node of the voltage regulator circuit. The non-inverting input of the second operational amplifier AMP2 is connected to the reference voltage VREF, the inverting input is connected to the feedback node of the voltage regulator circuit, and the output terminal outputs the adjustment control signal.

[0031] In this embodiment, the voltage regulator circuit achieves real-time sampling and closed-loop control of the output voltage through the feedback regulation structure composed of the aforementioned resistor voltage divider and operational amplifier. Specifically, the voltage divider network formed by the second resistor R2 and the third resistor R3 maps the output voltage VO to the feedback node voltage. The second operational amplifier AMP2 then compares the feedback node voltage with the reference voltage VREF and generates an adjustment control signal based on the deviation between the two, thereby driving the subsequent regulation unit to correct the output voltage. In this way, the voltage regulator circuit can adjust the control quantity in a timely manner when the output voltage changes, so as to maintain a stable output of the target voltage.

[0032] In some embodiments, reference Figure 4 The reference current generation module includes a first MOSFET M1, a first resistor R1, and a first operational amplifier AMP1. The first terminal of the first resistor R1 is connected to the source of the first MOSFET M1, and the second terminal is grounded. The non-inverting input of the first operational amplifier AMP1 is connected to the reference voltage VREF, the inverting input is connected to the first terminal of the first resistor R1, the output is connected to the gate of the first MOSFET M1, and the drain of the first MOSFET M1 is connected to the first current mirror module. The first MOSFET M1 is an NMOS transistor.

[0033] In this embodiment, the reference current generation module utilizes the closed-loop structure formed by the operational amplifier and MOSFET to automatically approximate the reference voltage VREF across the first resistor R1, thereby forming a stable reference current in the first resistor R1. By continuously adjusting the conduction state of the first MOSFET M1 through the operational amplifier AMP1, its operating point is kept within the controlled region. This module can maintain the accuracy and stability of the reference current even under power supply voltage fluctuations or changes in downstream load, providing a reliable current reference for subsequent current mirror replication and compensation current generation.

[0034] In some embodiments, reference Figure 4 The first current mirror module includes a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. The sources of all three MOSFETs are connected to the power supply voltage VDD. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The sources of the third MOSFET M3 and the fourth MOSFET M4 are connected to the compensation current generation module. The gates of all three MOSFETs are connected together and share a common connection to the drain of the second MOSFET M2.

[0035] In this embodiment, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 constitute a current mirror structure. All three are PMOS transistors, and their gates are connected together, ensuring the entire module operates under the same bias condition. The second MOSFET M2 serves as the reference branch of the current mirror, receiving the reference current from the first MOSFET M1 at its drain, thus establishing a stable mirror reference within the device. The third MOSFET M3 and the fourth MOSFET M4 replicate the current from the reference branch according to a preset ratio and output it to the compensation current generation module. Through this unified bias and multi-branch replication method, the first current mirror module can maintain good consistency and stability when the operating point changes, providing a reliable current input basis for subsequent compensation current generation.

[0036] In some embodiments, reference Figure 4 The compensation current generation module includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth MOSFET M5, and a sixth MOSFET M6. The collector of the first transistor Q1 is connected to the drain of the third MOSFET M3. The collector of the second transistor Q2 is connected to the drain of the fourth MOSFET M4, its emitter is grounded, and its base is connected to the emitter of the first transistor Q1. The collector of the third transistor Q3 is connected to the feedback node of the voltage regulator circuit, and its base is connected to the base of the first transistor Q1 and connected to a bias current IBIAS. The collector of the fourth transistor Q4 is connected to a reference current IREF, its emitter is grounded, and its base is connected to the emitter of the third transistor Q3. The source of the fifth MOSFET M5 is grounded, its drain is connected to the emitter of the first transistor Q1, and its gate is connected to a first bias voltage VBIAS1. The source of the sixth MOSFET M6 is grounded, its drain is connected to the emitter of the third transistor Q3, and its gate is connected to a second bias voltage VBIAS2.

[0037] In this embodiment, the compensation current generation module forms a current multiplication structure based on transistor characteristics through the current relationship between the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4. The first transistor Q1 and the second transistor Q2 form a pair of current branches to establish a current distribution related to the reference current; the third transistor Q3 and the fourth transistor Q4 form another pair of current branches to generate a compensation current corresponding to the output voltage change under the combined action of the bias current IBIAS and the reference current IREF. The fifth MOSFET M5 and the sixth MOSFET M6 provide stable bias voltages to the emitters of Q1 and Q3, respectively. Both the fifth MOSFET M5 and the sixth MOSFET M6 are NMOS transistors, ensuring that each transistor operates within a suitable operating range, thereby ensuring the consistency of the current multiplication relationship at different operating points. Through this structure, the compensation current generation module can establish a stable current ratio relationship based on the reference current and the reference current, and accurately inject the resulting compensation current into the feedback node of the voltage regulator circuit, providing reliable support for dynamic compensation of voltage divider offset.

[0038] According to the above embodiments, the working principle of the compensation circuit of this application is as follows: Figure 5 The compensation circuit in the middle corresponds to Figure 2 The slope of the relationship curve shown on the left satisfies k=k1<0. When the compensation current IX is injected into the feedback node, the feedback voltage VFB can be expressed as: ; Because the resistance of the third resistor R3 is much smaller than that of the second resistor R2, the feedback voltage V FB It can be simplified to: ; If at this point: ; The voltage division ratio of the resistor will then depend only on the constant c and will no longer shift with changes in the output voltage VO, thus achieving a stable voltage division ratio under different output voltages. Therefore: Due to k1×V O << c, therefore I X It can be simplified to: in, This term is a constant term; it only requires generating VREF through a multiplier. 2 Multiplying this by the constant coefficient yields the required compensation amount.

[0039] Therefore, refer to Figure 4The compensation circuit generates a current V through the first operational amplifier AMP1 and the first resistor R1. REF / R1, this current is injected into the collectors of the first transistor Q1 and the second transistor Q2 via a current mirror. The bases of the first transistor Q1 and the third transistor Q3 are connected to a bias current IBIAS, the fourth transistor Q4 is connected to a fixed current IREF, and the gates of the fifth MOSFET M5 and the sixth MOSFET M6 are connected to bias voltages VBIAS1 and VBIAS2, respectively, thereby generating the output current IOUT. When the above devices are operating in a stable state, we can obtain... Combined with the VBE expression of the transistor Among them, V T For thermal voltage, I C For collector current, I S This is the saturation current. Therefore, the aforementioned relationship can be simplified to: Right now Therefore, the collector current IC3 of the third transistor Q3 corresponds to the product of the input current, and is ultimately output to node VFB through the current mirror to compensate for the voltage division offset of the third resistor R3. Under this relationship, the compensation current can meet the expected voltage division correction requirements and achieve the required linear compensation characteristics simply by satisfying the following equation: Figure 5 A circuit topology diagram of a voltage divider offset compensation control circuit according to another embodiment of the present invention is shown. Figure 5 As shown, the compensation circuit also includes a second current mirror module. One end of the second current mirror module is connected to the compensation current generation module, and the other end is connected to the feedback node of the voltage regulator circuit, used to replicate and output the compensation current.

[0040] In this embodiment, Figure 4 The compensation circuit in the middle corresponds to Figure 2 The slope of the relationship curve shown on the right satisfies k=k2>0. Because... Figure 5 The corresponding compensation behavior needs to achieve a positive slope compensation curve (k = k2 > 0) in the same direction as the output voltage change. After generation, the compensation current needs to be kept isolated from the feedback node to avoid the reverse influence of the feedback node potential change on the compensation current formation path. By adding a second current mirror module after the compensation current generation module, the compensation current can be mirrored and then injected into the feedback node, thereby achieving controllable linear amplification and stable output of the compensation slope, making the overall compensation characteristics more likely to meet the design requirements of a positive slope.

[0041] In some embodiments, the second current mirror module includes a seventh MOSFET M7 and an eighth MOSFET M8. The sources of both the seventh MOSFET M7 and the eighth MOSFET M8 are connected to the power supply voltage VDD. The drain of the seventh MOSFET M7 is connected to the collector of the third transistor Q3, and the drain of the eighth MOSFET M8 is connected to the feedback node of the voltage regulator circuit. The gates of the seventh MOSFET M7 and the eighth MOSFET M8 are connected and share a common connection to the source of the seventh MOSFET M7.

[0042] In this embodiment, the seventh MOS transistor M7 and the eighth MOS transistor M8 form a current mirror structure, and both are PMOS transistors.

[0043] According to the above embodiment, the compensation circuit further includes a second current mirror module, which mirrors and copies the compensation current after the output of the compensation current generation module and outputs it to the feedback node. By introducing this module, the generation process of the compensation current is effectively isolated from the voltage changes of the feedback node, preventing potential fluctuations at the feedback node from interfering with the current generation path of the preceding stage. Simultaneously, the second current mirror module can linearly amplify or reduce the preceding stage current according to a predetermined ratio, ensuring that the compensation current injected into the feedback node adjusts with a stable slope as the output voltage changes, thereby satisfying... Figure 2 The positive slope compensation relationship is shown on the right. With this structure, the circuit not only achieves the compensation function but also further improves the stability and controllability of the compensation characteristics, enabling the overall output to maintain the required voltage division consistency over a wider voltage range.

[0044] Figure 5 Working mechanism of compensation circuit Figure 4 The implementation methods are the same, and the relevant principles have been explained previously, so they will not be repeated here.

[0045] Figure 6 A comparison diagram of the partial voltage coefficients before and after compensation according to an embodiment of the present invention is shown. Figure 7 A comparison graph of voltage accuracy before and after compensation according to an embodiment of the present invention is shown. Figure 6 and Figure 7 As shown, in the actual test, the resistors were configured at a ratio of 1 / 40, and the feedback voltage VFB was measured under different output voltage conditions, thereby obtaining the voltage division coefficient and voltage accuracy data before and after compensation.

[0046] The data before compensation shows that the voltage divider coefficient varies significantly with the output voltage, leading to increased deviation of the feedback voltage VFB and poor overall accuracy when the output voltage distribution is wide. In this case, adjusting only the reference voltage VREF can only guarantee that the accuracy at a specific output voltage point meets the requirements. For example, when using 60V as the adjustment point, high single-point accuracy can be obtained, but the accuracy at other voltage points will gradually decrease with the output voltage offset. However, by adopting the voltage divider offset compensation method of this invention, this offset effect can be effectively suppressed, achieving high-precision overall control across different output voltage ranges, and maintaining relatively consistent output accuracy across the entire voltage range.

[0047] Furthermore, the output terminal OUT of the second operational amplifier AMP2 can be connected to an optocoupler for output control of a secondary-side feedback switching power supply, depending on the application requirements, or it can be directly connected to a resistor node (e.g., Figure 1 As shown in the figure, parallel voltage regulation is achieved. Based on the compensation mechanism of this invention, in a multi-voltage output system, it is only necessary to ensure the reference accuracy corresponding to different VREFs, thereby ensuring that all output voltages VO meet the accuracy requirements across the entire range.

[0048] Figure 8 A voltage divider offset compensation method according to an embodiment of the present invention is shown, comprising the following steps: Step S100: The output voltage VO is sampled by voltage divider to obtain the feedback voltage signal.

[0049] Step S200: Generate compensation current IX based on the change in output voltage VO.

[0050] In step S300, a compensation current IX is injected into the feedback node of the voltage regulator circuit to counteract the voltage division offset caused by the change in output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages.

[0051] In step S400, an adjustment control signal is generated based on the feedback voltage signal and the compensation current IX, and the output voltage VO is adjusted according to the adjustment control signal.

[0052] The specific implementation methods of each step in the above voltage divider offset compensation method refer to the relevant content of the embodiment in the above voltage divider offset compensation circuit, and will not be repeated here.

[0053] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A voltage divider offset compensation control circuit, characterized in that, include: A voltage regulator circuit is used to divide and sample the output voltage VO to form a feedback voltage signal, and compare the feedback voltage signal with the reference voltage VREF to generate an adjustment control signal to adjust the output voltage VO. A compensation circuit, connected to the feedback node of the voltage regulator circuit, is used to generate a compensation current IX based on the change in the output voltage VO, and inject the compensation current IX into the feedback node of the voltage regulator circuit to counteract the voltage division offset caused by the change in the output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages.

2. The voltage divider offset compensation control circuit according to claim 1, characterized in that, The compensation circuit includes: A reference current generation module is connected to the reference voltage VREF and is used to generate a reference current based on the reference voltage VREF. The first current mirror module is connected to the reference current generation module and is used to perform current mirror copying of the reference current; The compensation current generation module is connected to the first current mirror module and the feedback node of the voltage regulator circuit, respectively, and is used to generate the compensation current IX and inject it into the feedback node of the voltage regulator circuit.

3. The voltage divider offset compensation control circuit according to claim 2, characterized in that, The reference current generation module includes a first MOSFET M1, a first resistor R1, and a first operational amplifier AMP1; The first end of the first resistor R1 is connected to the source of the first MOSFET M1, and the second end is grounded; The non-inverting input of the first operational amplifier AMP1 is connected to the reference voltage VREF, the inverting input is connected to the first end of the first resistor R1, the output is connected to the gate of the first MOS transistor M1, and the drain of the first MOS transistor M1 is connected to the first current mirror module.

4. The voltage divider offset compensation control circuit according to claim 3, characterized in that, The first current mirror module includes a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4; The sources of the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are all connected to the power supply voltage VDD. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The drains of the third MOSFET M3 and the fourth MOSFET M4 are all connected to the compensation current generation module. The gates of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are all connected and are connected to the drain of the second MOS transistor M2.

5. The voltage divider offset compensation control circuit according to claim 4, characterized in that, The compensation current generation module includes: The collector of the first transistor Q1 is connected to the drain of the third MOS transistor M3; The collector of the second transistor Q2 is connected to the drain of the fourth MOS transistor M4, the emitter is grounded, and the base is connected to the emitter of the first transistor Q1. The collector of the third transistor Q3 is connected to the feedback node of the voltage regulator circuit, and its base is connected to the base of the first transistor Q1 and connected to the bias current IBIAS. The fourth transistor Q4 has its collector connected to the reference current IREF, its emitter grounded, and its base connected to the emitter of the third transistor Q3. The fifth MOSFET M5 has its source grounded, its drain connected to the emitter of the first transistor Q1, and its gate connected to the first bias voltage VBIAS1. The sixth MOS transistor M6 has its source grounded, its drain connected to the emitter of the third transistor Q3, and its gate connected to the second bias voltage VBIAS2.

6. The voltage divider offset compensation control circuit according to claim 5, characterized in that, The compensation circuit further includes: The second current mirror module is connected at one end to the compensation current generation module and at the other end to the feedback node of the voltage regulator circuit, and is used to replicate and output the compensation current.

7. The voltage divider offset compensation control circuit according to claim 6, characterized in that, The second current mirror module includes a seventh MOSFET M7 and an eighth MOSFET M8; The sources of the seventh MOSFET M7 and the eighth MOSFET M8 are both connected to the power supply voltage VDD. The drain of the seventh MOSFET M7 is connected to the collector of the third transistor Q3, and the drain of the eighth MOSFET M8 is connected to the feedback node of the voltage regulator circuit. The gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected and are also connected to the source of the seventh MOS transistor M7.

8. The voltage divider offset compensation control circuit according to any one of claims 1-7, characterized in that, The voltage regulator circuit includes a second resistor R2, a third resistor R3, and a second operational amplifier AMP2; The output voltage VO is grounded through the second resistor R2 and the third resistor R3 in sequence, and the node between the second resistor R2 and the third resistor R3 serves as the feedback node of the voltage regulator circuit. The non-inverting input of the second operational amplifier AMP2 is connected to the reference voltage VREF, the inverting input is connected to the feedback node of the voltage regulator circuit, and the output terminal outputs the adjustment control signal.

9. A voltage divider offset compensation method, characterized in that, Includes the following steps: The output voltage VO is divided and sampled to obtain the feedback voltage signal; A compensation current IX is generated based on the change in the output voltage VO; The compensation current IX is injected into the feedback node of the voltage regulator circuit to counteract the voltage division offset caused by the change in the output voltage VO, so that the feedback signal maintains a constant voltage division ratio under different output voltages. An adjustment control signal is generated based on the feedback voltage signal and the compensation current IX, and the output voltage VO is adjusted according to the adjustment control signal.

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