Bus encoder and integrated circuit chip
By recognizing bus encoders and integrated circuit chips that use the Tamagawa and BiSS-C protocols through an identification circuit, the problem of damage and management difficulty when changing protocols in existing bus encoders is solved, and flexible bus communication is realized.
Patent Information
- Application Number
- CN202610282708.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-09
- Publication Date
- 2026-06-05
Smart Images
Figure CN122152742A_ABST
Abstract
Description
Technical Field
[0001] This application relates to bus encoder technology, and more particularly to a bus encoder and an integrated circuit chip. Background Technology
[0002] A bus encoder is an intelligent motion sensor that integrates position / speed sensing functions with a fieldbus communication interface. It encapsulates encoder measurement data (such as position, speed, status, etc.) into data frames for transmission via digital bus protocols (such as CANopen, EtherCAT, PROFIBUS, etc.), achieving efficient and reliable communication with the host controller.
[0003] Existing bus encoder products only support one protocol, which is predetermined at the factory. To adapt to various bus protocols, multiple models need to be manufactured and used, increasing management complexity. Moreover, after the encoder is installed on the motor, if the bus protocol needs to be changed, the encoder must be disassembled. Disassembly of the encoder is prone to damage and deformation, leading to decreased accuracy. Summary of the Invention
[0004] This application provides a bus encoder and an integrated circuit chip to support two bus protocols and improve the flexibility of the bus encoder.
[0005] In a first aspect, embodiments of this application provide a bus encoder, including: a main control chip and an identification circuit;
[0006] The identification circuit is connected to the main control chip and is used to receive input signals and output corresponding protocol signals to the main control chip according to whether the input signals include a predetermined timing sequence; wherein, the predetermined timing sequence includes two consecutive low levels, one high level, and one low level.
[0007] The main control chip is used to determine whether the input signal adopts the Tamagawa communication protocol according to the protocol signal, and to process the input signal according to the corresponding communication protocol.
[0008] Optionally, the identification circuit includes: a first identification module and a second identification module;
[0009] The first identification module is used to receive the input signal. If there are two consecutive low levels in the input signal, it continuously outputs a first signal of a first state to the second identification module; otherwise, it outputs a first signal of a second state to the second identification module.
[0010] The second identification module is connected to the first identification module and the main control chip, and is used to output a first state protocol signal to the main control chip if, according to the first signal, two consecutive low levels in the input signal are followed by one high level and one low level; otherwise, it outputs a second state protocol signal to the main control chip.
[0011] Optionally, the first identification module includes: a first identification unit and a first latching unit;
[0012] The first identification unit and the first latch unit are connected and are used to receive the input signal. If the input signal has two consecutive low levels, the first signal of the first state is output to the first latch unit; otherwise, the first signal of the second state is output to the first latch unit.
[0013] The first latch unit is connected to the second identification module and is used to continuously output the first signal of the first state to the second identification module if the first signal of the first state is received, until the reset signal sent by the second identification module is received; otherwise, it outputs the first signal of the second state to the second identification module.
[0014] Optionally, the first identification unit includes: a first delay unit and a first OR gate; wherein,
[0015] The input terminal of the first delay unit receives the input signal, and the output terminal of the first delay unit is connected to the first input terminal of the first OR gate;
[0016] The second input terminal of the first OR gate receives the input signal, and the output terminal of the first OR gate is connected to the first latch unit.
[0017] Optionally, the first latch unit includes: a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein,
[0018] The input terminal of the first transistor receives a high level, the output terminal of the first transistor is connected to the control terminal of the second transistor, and the control terminal of the first transistor receives the reset signal;
[0019] One end of the first resistor is connected to the output of the first OR gate, the other end of the first resistor is connected to the control terminal of the second transistor, one end of the second resistor is connected to the input of the second transistor, the output of the second transistor is connected to one end of the third resistor, the other end of the third resistor is grounded, and the other end of the second resistor is connected to the input of the second transistor.
[0020] The input terminal of the third transistor is connected to one end of the fifth resistor and the control terminal of the second transistor. The other end of the fifth resistor receives a high level. The output terminal of the third transistor is grounded. One end of the fourth resistor is connected to the output terminal of the second transistor. The control terminal of the third transistor is connected to the other end of the fourth resistor.
[0021] Optionally, the second identification module includes: a reset unit, a second identification unit, and a third identification unit;
[0022] The reset unit is used to receive the input signal and the first signal. If the first signal of the first state is received and there are at least two consecutive high levels in the input signal, a reset signal is sent to the first identification module and the second identification unit.
[0023] The second identification unit is configured to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, the second signal of the first state is continuously sent to the third identification unit until the reset signal is received; otherwise, the second signal of the second state is sent to the third identification unit.
[0024] The third identification unit is used to receive the input signal and the second signal. If the second signal of the first state is received, and the input signal includes one high level and at least one low level, then the first state protocol signal is continuously sent to the main control chip; otherwise, the second state protocol signal is sent to the main control chip.
[0025] Optionally, the reset unit includes: a first sub-identification unit, a second sub-identification unit, and an output unit;
[0026] The first sub-identification unit is used to receive the first signal and the input signal. If the first signal of the first state is received and there is a high level in the input signal, then the third signal of the first state is output to the output unit.
[0027] The second sub-identification unit is used to receive the input signal, and if the input signal has at least two consecutive high levels, it outputs a fourth signal of the first state to the output unit.
[0028] The output unit is connected to the first sub-identification unit, the second sub-identification unit, the first identification module, and the second identification unit, and is used to output a reset signal to the first identification module and the second identification unit when receiving the third signal of the first state and the fourth signal of the first state.
[0029] Optionally, the second identification unit includes: a third sub-identification unit and a second latching unit;
[0030] The third sub-identification unit is used to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, then the second signal of the first state is sent to the second latching unit; otherwise, the second signal of the second state is sent to the second latching unit.
[0031] The second latching unit is connected to the third sub-identification unit and the third identification unit, and is used to continuously output the second signal of the first state to the third identification unit if the second signal of the first state is received, until the reset signal is received; otherwise, it outputs the second signal of the second state to the third identification unit.
[0032] Optionally, the third identification unit includes: a fourth sub-identification unit and a third latching unit;
[0033] The fourth sub-identification unit is used to receive the input signal and the second signal. If the second signal of the first state is received, and the input signal includes one high level and at least one low level, then the first state protocol signal is sent to the third latch unit; otherwise, the second state protocol signal is sent to the third latch unit.
[0034] The third latch unit is connected to the fourth sub-identification unit and the main control chip. If the second signal of the first state is received, the latch unit continuously outputs the protocol signal of the first state to the main control chip until it is reset by the main control chip; otherwise, the latch unit outputs the protocol signal of the second state to the main control chip.
[0035] Optionally, the first sub-identification unit includes: a sixth resistor, a first inverter, and a first AND gate; wherein,
[0036] One end of the sixth resistor is connected to the first identification module, the other end of the sixth resistor is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the first AND gate, the second input terminal of the first AND gate receives the input signal, and the output terminal of the first AND gate is connected to the output unit.
[0037] The second sub-identification unit includes: a second delay unit and a second AND gate; wherein,
[0038] The input terminal of the second delay unit receives the input signal, and the output terminal of the second delay unit is connected to the first input terminal of the second AND gate;
[0039] The second input terminal of the second AND gate receives the input signal, and the output terminal of the second AND gate is connected to the output unit;
[0040] The output unit includes: a third AND gate and a seventh resistor; wherein...
[0041] The first input terminal of the third AND gate is connected to the second sub-identification unit, the second input terminal of the third AND gate is connected to the first sub-identification unit, the output terminal of the third AND gate is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the reset terminal of the first identification module and the reset terminal of the second identification module.
[0042] Optionally, the third sub-identification unit includes: an eighth resistor, a second inverter, and a fourth AND gate; wherein,
[0043] One end of the eighth resistor is connected to the first identification module, the other end of the eighth resistor is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first input terminal of the fourth AND gate, the second input terminal of the fourth AND gate receives the input signal, and the output terminal of the fourth AND gate is connected to the output unit.
[0044] The second latch unit includes: a fourth transistor, a fifth transistor, a sixth transistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third inverter; wherein,
[0045] The input terminal of the fourth transistor is connected to the control terminal of the fifth transistor and the output terminal of the sixth transistor. The output terminal of the fourth transistor is grounded, and the control terminal of the fourth transistor receives the reset signal.
[0046] One end of the ninth resistor is connected to the output of the fourth AND gate, the other end of the ninth resistor is connected to the control terminal of the fifth transistor, the input terminal of the fifth transistor is connected to one end of the tenth resistor, the other end of the tenth resistor receives a high level, and the output terminal of the fifth transistor is grounded.
[0047] One end of the eleventh resistor is connected to the input terminal of the fifth transistor, the other end of the eleventh resistor is connected to the control terminal of the sixth transistor and one end of the twelfth resistor, the other end of the twelfth resistor receives a high level, the input terminal of the sixth transistor receives a high level, the output terminal of the sixth transistor is connected to one end of the thirteenth resistor and the input terminal of the third inverter, the other end of the thirteenth resistor is grounded, and the output terminal of the third inverter is connected to the third identification unit.
[0048] Optionally, the fourth sub-identification unit includes: a third delay unit, a second OR gate, and a third OR gate; wherein,
[0049] The input terminal of the third delay unit receives the input signal, and the output terminal of the third delay unit is connected to the first input terminal of the second OR gate;
[0050] The second input terminal of the second OR gate receives the input signal, and the output terminal of the second OR gate is connected to the first input terminal of the third OR gate;
[0051] The second input terminal of the third OR gate is connected to the third sub-identification unit, and the output terminal of the third OR gate is connected to the third latch unit;
[0052] The third latch unit includes: a seventh transistor, an eighth transistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a fifth resistor; wherein,
[0053] One end of the fourteenth resistor is connected to the output terminal of the first identification unit, and the other end of the fourteenth resistor is connected to the control terminal of the eighth transistor, one end of the fifteenth resistor, and the other end of the fifteenth resistor receives a high level.
[0054] The input terminal of the seventh transistor receives a high level, the output terminal of the seventh transistor is connected to one end of the sixteenth resistor and one end of the seventeenth resistor, and the other end of the sixteenth resistor is grounded;
[0055] The other end of the seventeenth resistor is connected to the control terminal of the eighth transistor. The input terminal of the eighth transistor is connected to one end of the eighteenth resistor and the main control chip. The other end of the eighteenth resistor receives a high level, and the output terminal of the eighth transistor is grounded.
[0056] Optionally, the main control chip is used to process the input signal according to the protocol signal under the corresponding Tamagawa protocol or BiSS-C protocol.
[0057] Secondly, embodiments of this application provide an integrated circuit chip, including the bus encoder as described above.
[0058] In the bus encoder and integrated circuit chip provided in this application, based on the timing characteristics of the received signal according to the Tamagawa communication protocol, the identification circuit identifies whether there is a four-bit continuous special timing sequence of low-low-high-low in the input signal. Based on the identification result, it outputs a protocol signal to the main control chip. This protocol signal is used to characterize whether the input signal adopts the Tamagawa communication protocol. The main control chip determines the current bus protocol based on the protocol signal and processes the input signal using the corresponding bus protocol. Thus, the bus encoder can automatically identify and process the Tamagawa communication protocol and other protocols without special timing sequences. It can be applied to two bus protocols. When the bus protocol changes, bus communication can be achieved without replacing the bus encoder, saving maintenance costs and improving the flexibility of bus encoder applications. Attached Figure Description
[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0060] Figure 1 This is a schematic diagram of a bus encoder provided in an embodiment of this application.
[0061] Figure 2 This is a timing diagram illustrating the Tamagawa Protocol command reception in an embodiment of this application.
[0062] Figure 3 This is a schematic diagram of a special timing protocol of the Tamagawa protocol provided in an embodiment of this application.
[0063] Figure 4 This is a timing diagram of a BiSS-C protocol clock provided for an embodiment of this application.
[0064] Figure 5 This is a schematic diagram of the structure of an identification circuit provided in an embodiment of this application.
[0065] Figure 6 This is a schematic diagram of the structure of a first identification module provided in an embodiment of this application.
[0066] Figure 7 This is a schematic diagram of the delay timing of two low-level signals provided in an embodiment of this application.
[0067] Figure 8 This is a schematic diagram of a reset unit provided in an embodiment of this application.
[0068] Figure 9 This is a timing diagram illustrating the delay of a single high-level signal provided in an embodiment of this application.
[0069] Figure 10 This is a schematic diagram of the delay timing of two high-level signals provided in an embodiment of this application.
[0070] Figure 11 This is a schematic diagram of the structure of a second identification unit provided in an embodiment of this application.
[0071] Figure 12 This is a schematic diagram of the structure of an identification circuit provided in an embodiment of this application.
[0072] Figure 13 This is a schematic diagram of the structure of a third identification unit provided in an embodiment of this application.
[0073] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0074] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0075] In this application, a module refers to a functional module or a logical module. It can be in software form, where its function is implemented by a processor executing program code; or it can be in hardware form. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "OR" relationship.
[0076] A bus encoder is an intelligent motion sensor that integrates position / speed sensing functions with a fieldbus communication interface. It uses a digital bus protocol to encapsulate encoder measurement data into data frames for transmission, enabling efficient and reliable communication with a host controller.
[0077] Existing bus encoder products only support one protocol, which is predetermined at the factory. To adapt to various bus protocols, multiple models need to be manufactured and used, increasing management complexity. Moreover, after the encoder is installed on the motor, if the bus protocol needs to be changed, the encoder must be disassembled. Disassembly of the encoder is prone to damage and deformation, leading to decreased accuracy.
[0078] To address the aforementioned technical issues, the bus encoder and integrated circuit chip provided in this application embodiment process the two initial clutch enable signals output by the main controller through an interlock circuit, ensuring that the final output enable signal will not be enabled by both simultaneously, thereby effectively preventing the dual clutches from working at the same time and improving the safety and reliability of the system.
[0079] The technical solutions of this application are illustrated below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0080] Figure 1 This is a schematic diagram of a bus encoder provided in an embodiment of this application. Figure 1 As shown, the bus encoder provided in this application embodiment includes: an identification circuit 100 and a main control chip 200;
[0081] The identification circuit 100 is connected to the main control chip 200 and is used to receive input signals and output corresponding protocol signals to the main control chip 200 according to whether the input signals include a predetermined timing sequence; wherein, the predetermined timing sequence includes two consecutive low levels, one high level and one low level.
[0082] The main control chip 200 is used to determine whether the input signal adopts the Tamagawa communication protocol based on the protocol signal, and to process the input signal according to the corresponding communication protocol.
[0083] For example, the Tamagawa protocol enables communication via a pair of differential data lines. Figure 2 This is a timing diagram illustrating the Tamagawa protocol command reception, provided as an embodiment of this application. Figure 2 As shown, in the specific implementation, the Tamagawa protocol uses UART timing at its core. The transmission timing of each byte is 10 bits. The first bit is the start bit, which is fixed at a low level; the second to fourth bits are the sink code, which is fixed at a low level, a high level, and a low level; the remaining 5 data bits are transmitted according to the actual data; and the 10th bit is the parity bit, which can be a parity bit.
[0084] Figure 3 This is a schematic diagram illustrating a special timing scheme for the Tamagawa protocol, provided as an embodiment of this application. (See diagram below.) Figure 3 As shown, it can be seen that as long as it is the Tamagawa protocol, the timing of each byte of data received by the encoder will definitely have a special timing sequence. The special timing sequence is the timing sequence of bits 1 to 4. Bits 1 and 2 are two low levels (here called the first segment level of the special timing sequence), bit 3 is a high level (here called the second segment level of the special timing sequence), and bit 4 is a low level (here called the third segment level of the special timing sequence).
[0085] Therefore, based on this special timing sequence, the bus encoder can identify two bus protocols: one is the Tamagawa protocol, and the other is a non-Tamagawa protocol that does not exhibit this special timing sequence. The identification circuit 100 identifies whether the input signal includes a predetermined timing sequence (two consecutive low levels, one high level, and one low level), and outputs the corresponding protocol signal to the main control chip 200 based on the identification result. This allows the main control chip 200 to determine whether the input signal uses the Tamagawa communication protocol based on the protocol signal, and then process the input signal according to the corresponding communication protocol.
[0086] In one possible implementation, the non-Tamagawa protocol can be the BiSS-C protocol. The BiSS-C protocol is a synchronous communication protocol that communicates via a clock line and a data line. Figure 4 This is a timing diagram of a BiSS-C protocol clock provided for an embodiment of this application. Figure 4 As shown, the BiSS-C protocol clock timing maintains a high-level and low-level cycle. The last position of the clock signal corresponds to the CDM register data level. After the low level, it enters an idle state and then remains at a constant high level. Therefore, the BiSS-C protocol clock timing does not exhibit any special timing characteristics.
[0087] Based on the timing characteristics of the Tamagawa protocol received signal and the BiSS-C protocol clock, the identification circuit 100 can be used to receive the received signal using the Tamagawa protocol or the clock signal using the BiSS-C protocol, and identify whether the received signal has special timing, thereby determining whether the current signal uses the Tamagawa protocol or the BiSS-C protocol.
[0088] like Figure 1 As shown, when the non-Tamagawa protocol can be replaced by the BiSS-C protocol, the bus encoder can also include an RS485-1 chip and an RS485-2 chip. The RS485-1 chip is used for differential and single-ended level conversion under the Tamagawa protocol, and can also be used for differential and single-ended level conversion of the clock signal under the BiSS-C protocol. The RS485-2 chip is used for differential and single-ended level conversion of the data signal under the BiSS-C protocol.
[0089] In this embodiment, based on the timing characteristics of the Tamagawa communication protocol received signal, the identification circuit 100 identifies whether there is a four-bit continuous special timing sequence of low-low-high-low in the input signal. Based on the identification result, it outputs a protocol signal to the main control chip 200. This protocol signal is used to characterize whether the input signal adopts the Tamagawa communication protocol. The main control chip 200 determines the current bus protocol based on the protocol signal and processes the input signal using the corresponding bus protocol. Thus, the bus encoder can automatically identify the Tamagawa communication protocol and other protocols without special timing sequences and process them accordingly. It can be applied to two bus protocols. When the bus protocol changes, bus communication can be achieved without replacing the bus encoder, saving maintenance costs and improving the flexibility of bus encoder application.
[0090] Figure 5 This is a schematic diagram of an identification circuit provided in an embodiment of this application. Figure 5 As shown, in some embodiments, the identification circuit 100 includes: a first identification module 110 and a second identification module 120;
[0091] The first identification module 110 is used to receive the input signal (RDATA). If there are two consecutive low levels in the input signal, it continuously outputs the first signal (OUTX) of the first state to the second identification module 120; otherwise, it outputs the first signal of the second state to the second identification module 120.
[0092] The second identification module 120 is connected to the first identification module 110 and the main control chip 200. It is used to output a first state protocol signal (OUT) to the main control chip 200 if, according to the first signal, two consecutive low levels in the input signal are followed by a high level and a low level in sequence; otherwise, it outputs a second state protocol signal to the main control chip 200.
[0093] For example, the first identification module 110 is used to identify whether there is a first segment level (two consecutive low levels) with a special timing in the input signal, and outputs a first signal to the second identification module 120 according to the identification result. When the first signal is in a first state, it indicates that there is a first segment level with a special timing in the input signal; when the first signal is in a second state, it indicates that there is no first segment level with a special timing in the input signal.
[0094] For example, the second identification module 120 can further identify whether there are second and third level segments with special timing in the input signal based on the received first signal, and output a protocol signal to the main control chip 200 according to the identification result. When the protocol signal is in the first state, it indicates that there is special timing in the input signal; when the protocol signal is in the second state, it indicates that there is no special timing in the input signal.
[0095] When the first signal is in the second state, it can be determined that there is no special timing in the input signal, the input signal does not use the Tamagawa communication protocol, and the second identification module 120 outputs the protocol signal of the second state to the main control chip 200.
[0096] When the first signal is in the first state, the second identification module 120 identifies whether there are second and third level segments with special timing in the input signal. If there are second and third level segments with special timing, it means that there is a complete special timing in the input signal, and the second identification module 120 outputs the protocol signal of the first state to the main control chip 200; if not, it means that there is no complete special timing in the input signal, and the second identification module 120 outputs the protocol signal of the second state to the main control chip 200.
[0097] For example, the different states of the first signal and the second signal can be characterized by high and low levels.
[0098] Figure 6 This is a schematic diagram of the structure of a first identification module provided in an embodiment of this application. Figure 6 As shown, in some embodiments, the first identification module 110 includes: a first identification unit 111 and a first latching unit 112;
[0099] The first identification unit 111 and the first latch unit 112 are connected and are used to receive input signals. If the input signal has two consecutive low levels, the first signal of the first state is output to the first latch unit 112; otherwise, the first signal of the second state is output to the first latch unit 112.
[0100] The first latch unit 112 is connected to the second identification module 120. If the first signal of the first state is received, the first signal of the first state is continuously output to the second identification module 120 until the reset signal (OUTA) sent by the second identification module 120 is received; otherwise, the first signal of the second state is output to the second identification module 120.
[0101] In a specific implementation, the first identification module 110 may consist of a first identification unit 111 and a first latching unit 112. The first identification unit 111 identifies whether there are two consecutive low levels in the input signal, and outputs a first signal of the first state when there are two consecutive low levels in the input signal. The first latching unit 112 latches the received first signal of the first state and outputs it to the second identification module 120 until it is reset, so that the second identification module 120 can further identify whether the subsequent timing of the input signal is one high level and at least one low level when there are two consecutive low levels in the input signal, thereby realizing the identification of whether there is a special timing of the input signal.
[0102] like Figure 6As shown, in one possible implementation, the first identification unit 111 includes: a first delay unit and a first OR gate U1; wherein,
[0103] The input terminal of the first delay unit receives the input signal, and the output terminal of the first delay unit is connected to the first input terminal of the first OR gate U1.
[0104] The second input terminal of the first OR gate U1 receives the input signal, and the output terminal of the first OR gate U1 is connected to the first latch unit 112.
[0105] Figure 7 This is a timing diagram illustrating the delay of two low-level signals provided in an embodiment of this application. (See diagram below.) Figure 7 As shown, when there is only one low level in the input signal, after the first delay unit, the first input terminal of the first OR gate U1 receives a high level; when there are two low levels in the input signal, after the first delay unit, the first input terminal of the first OR gate U1 receives a low level.
[0106] It is understandable that when there is no low level in the input signal, after the first delay unit, the first input terminal of the first OR gate U1 receives a high level.
[0107] Therefore, when there is no low level in the input signal, the first input terminal of the first OR gate U1 receives a high level, the second input terminal receives a high level, and the first OR gate U1 outputs a high level (the first signal of the second state); when there is only one low level in the input signal, the first input terminal of the first OR gate U1 receives a high level, the second input terminal receives a low level, and the first identification unit 111 outputs a high level (the first signal of the second state); when there are only two low levels in the input signal, both input terminals of the first OR gate U1 receive a low level, and the first identification unit 111 outputs a low level (the first signal of the first state).
[0108] For example, the transmission baud rate of the Tamagawa protocol affects the device selection of the first delay unit, and the delay time of the first delay unit is 1 / 2 of the Tamagawa protocol level period.
[0109] For example, the first delay unit can be an RC delay circuit, consisting of a nineteenth resistor R1 and a first capacitor C1. The delay time t of the first delay unit is t = -R1C1*ln[(Us-U) / Us]), where Us is VCC and U is the capacitor voltage. The selection of the nineteenth resistor R1 and the first capacitor C1 can be determined according to the transmission baud rate of the Tamagawa protocol.
[0110] like Figure 6As shown, in one possible implementation, the first latch unit 112 includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R2, a second resistor R3, a third resistor R4, a fourth resistor R5, and a fifth resistor R7; wherein,
[0111] The input terminal of the first transistor Q1 receives a high level, the output terminal of the first transistor Q1 is connected to the control terminal of the second transistor Q2, and the control terminal of the first transistor Q1 receives a reset signal.
[0112] One end of the first resistor R2 is connected to the output of the first OR gate U1, the other end of the first resistor R2 is connected to the control terminal of the second transistor Q2 and one end of the second resistor R3, the input of the second transistor Q2 receives a high level, the output of the second transistor Q2 is connected to one end of the third resistor R4, the other end of the third resistor R4 is grounded, and the other end of the second resistor R3 is connected to the input of the second transistor Q2.
[0113] The input terminal of the third transistor Q3 is connected to one end of the fifth resistor R7 and the control terminal of the second transistor Q2. The other end of the fifth resistor R7 receives a high level. The output terminal of the third transistor Q3 is grounded. One end of the fourth resistor R5 is connected to the output terminal of the second transistor Q2. The control terminal of the third transistor Q3 is connected to the other end of the fourth resistor R5.
[0114] For example, the first transistor Q1 is a MOS transistor, the second transistor Q2 is a PNP transistor, and the third transistor Q3 is an NPN transistor.
[0115] For example, when the input signal has two consecutive low levels, the first identification unit 111 outputs the first signal (low level) of the first state to the first latch unit 112, the second transistor Q2 is turned on, the control terminal level of the third transistor Q3 is pulled high, the third transistor Q3 is turned on, the OUTX output by the first latch unit 112 is low (the first signal of the first state), and the control terminal level of the second transistor Q2 is pulled low. The second transistor Q2 and the third transistor Q3 remain on, and OUTX remains low, thus realizing latched output.
[0116] When there are no two consecutive low levels in the input signal, the first identification unit 111 outputs the first signal of the second state (high level) to the first latch unit 112, the second transistor Q2 is not turned on, the third transistor Q3 is not turned on, and OUTX is high level (the first signal of the second state).
[0117] For example, when the control terminal of the first transistor Q1 receives a reset signal, the first transistor Q1 is turned on, the control terminal level of the second transistor Q2 is pulled high, the second transistor Q2 is not turned on, the third transistor Q3 is not turned on, and OUTX is high (the first signal of the second state).
[0118] In some embodiments, the second identification module 120 includes: a reset unit 121, a second identification unit 122, and a third identification unit 123;
[0119] The reset unit 121 is used to receive an input signal and a first signal. If the first signal of the first state is received and there are at least two consecutive high levels in the input signal, a reset signal is sent to the first identification module 110 and the second identification unit 122.
[0120] The second identification unit 122 is used to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, the second signal of the first state is continuously sent to the third identification unit 123 until a reset signal is received; otherwise, the second signal of the second state is sent to the third identification unit 123.
[0121] The third identification unit 123 is used to receive the input signal and the second signal. If the second signal of the first state is received and the input signal includes one high level and at least one low level, the first state protocol signal is continuously sent to the main control chip; otherwise, the second state protocol signal is sent to the main control chip.
[0122] In a specific implementation, the second identification unit 122 is used to further determine whether a high level exists after the first segment of the special timing sequence in the input signal. When the input signal does not have two consecutive low levels, the second identification unit 122 receives the first signal of the second state and sends the second signal of the second state to the third identification unit 123; when the input signal has two consecutive low levels, the second identification unit 122 receives the first signal of the first state, and if it identifies that the input signal has a high level, it sends the second signal of the first state to the third identification unit 123, indicating that the input signal has a low-level, low-level, high-level timing sequence; when the input signal has two consecutive low levels, the second identification unit 122 receives the first signal of the first state, and if it identifies that the input signal does not have a high level, it sends the second signal of the second state to the third identification unit 123, indicating that the input signal does not have a special timing sequence.
[0123] Meanwhile, when there are two consecutive low levels in the input signal, if the first signal of the first state of the reset unit 121 detects at least two consecutive high levels in the input signal, it indicates that there is no special timing in the input signal. The reset unit 121 sends a reset signal to the first identification module 110 and the second identification unit 122, so that the first identification module 110 outputs the first signal of the second state and the second identification unit 122 outputs the second signal of the second state.
[0124] When the input signal has two consecutive low levels and at least one high level, the third identification unit 123 receives the second signal of the first state. Based on this, the third identification unit 123 identifies whether the duration of the high level in the input signal meets the requirements. If the duration of the high level is one cycle, the third identification unit 123 continuously sends the protocol signal of the first state to the main control chip, indicating that the input signal has a four-bit special timing sequence of low-low-high-low. If the duration of the high level is two cycles, the third identification unit 123 sends the protocol signal of the second state to the main control chip.
[0125] Figure 8 This is a schematic diagram of a reset unit provided in an embodiment of this application. Figure 8 As shown, in one possible implementation, the reset unit 121 includes: a first sub-identification unit 1211, a second sub-identification unit 1212, and an output unit 1213;
[0126] The first sub-identification unit 1211 is used to receive a first signal and an input signal. If the first signal of the first state is received and there is a high level in the input signal, the third signal of the first state is output to the output unit 1213.
[0127] The second sub-identification unit 1212 is used to receive the input signal. If the input signal has at least two consecutive high levels, it outputs the fourth signal of the first state to the output unit 1213.
[0128] The output unit 1213 is connected to the first sub-identification unit 1211, the second sub-identification unit 1212, the first identification module, and the second identification unit 122, and is used to output a reset signal to the first identification module 110 and the second identification unit 122 when the third signal of the first state and the fourth signal of the first state are received.
[0129] In its implementation, the first sub-identification unit 1211 identifies whether the input signal has a first segment of a special timing level based on the first signal, and identifies whether there is a high level after the first segment of the special timing level in the input signal. Based on the identification result, it outputs a third signal to the output unit 1213. The second sub-identification unit 1212 identifies whether the input signal has at least two consecutive high levels, and outputs a fourth signal to the output unit 1213 based on the identification result. Thus, the output unit 1213 can output a reset signal based on the third and fourth signals when the input signal has a first segment of a special timing level, and there are at least two consecutive high levels after the first segment of the special timing level. At this time, the input signal does not meet the special timing requirement, thereby controlling the first identification module 110 and the second identification unit 122 to reset.
[0130] The specific structure of the reset unit 121 will be described below by way of example.
[0131] In one possible implementation, the first sub-identification unit 1211 includes: a sixth resistor R8, a first inverter U2, and a first AND gate U4; wherein...
[0132] One end of the sixth resistor R8 is connected to the first identification module 110, the other end of the sixth resistor R8 is connected to the input terminal of the first inverter U2, the output terminal of the first inverter U2 is connected to the first input terminal of the first AND gate U4, the second input terminal of the first AND gate U4 receives the input signal, and the output terminal of the first AND gate U4 is connected to the output unit 1213.
[0133] In one possible implementation, the second sub-identification unit 1212 includes: a second delay unit 12121 and a second AND gate U3; wherein...
[0134] The input terminal of the second delay unit 12121 receives the input signal, and the output terminal of the second delay unit 12121 is connected to the first input terminal of the second AND gate U3;
[0135] The second input terminal of the second AND gate U3 receives the input signal, and the output terminal of the second AND gate U3 is connected to the output unit 1213.
[0136] For example, the second delay unit 12121 has a similar structure to the first delay unit, and may specifically include a twentieth resistor R9 and a capacitor C2.
[0137] In one possible implementation, the output unit 1213 includes: a third AND gate U5 and a seventh resistor R10; wherein,
[0138] The first input terminal of the third AND gate U5 is connected to the second sub-identification unit 1212. The second input terminal of the third AND gate U5 is connected to the first sub-identification unit 1211. The output terminal of the third AND gate U5 is connected to one end of the seventh resistor R10. The other end of the seventh resistor R10 is connected to the reset terminal of the first identification module and the reset terminal of the second identification module.
[0139] In the specific implementation, when there is no special timing in the first stage of the input signal, OUTX is always high, the first inverter U2 outputs a low level, the first AND gate U4 outputs a low level (the third signal of the second state), and the third AND gate U5 outputs a low level OUTA.
[0140] Figure 9 This is a timing diagram illustrating the delay of a single high-level signal provided in an embodiment of this application. Figure 10 This is a schematic diagram illustrating the delay timing of two high-level signals provided in an embodiment of this application. (See attached diagram.) Figure 9 , Figure 10 As shown, when there is only one high level in the input signal, after the second delay unit 12121 delays, the second input terminal of the second AND gate U3 becomes low level; when there are at least two high levels in the input signal, after the second delay unit 12121 delays, the second input terminal of the second AND gate U3 becomes high level.
[0141] Therefore, when the input signal has a first level with a specific timing, but at least two high levels follow the first level, OUTX remains low, the first inverter U2 outputs a high level, and the first AND gate U4 outputs a high level (the third signal of the first state). The first input of the second AND gate U3 is high, the second input of the second AND gate U3 becomes high, the second AND gate U3 outputs a high level (the fourth signal of the first state), and the OUTA output of the third AND gate U5 is high (reset signal), thereby resetting the first identification module 110 and the second identification unit 122.
[0142] When the input signal has a special timing sequence with the first segment level and the second terminal level, OUTX remains low, the first inverter U2 outputs a high level, and the first AND gate U4 outputs a high level (the third signal in the first state). The first input terminal of the second AND gate U3 is high, the second input terminal of the second AND gate U3 is low (the fourth signal in the second state), the second AND gate U3 outputs a low level, and the OUTA output of the third AND gate U5 is low.
[0143] Figure 11 This is a schematic diagram of the structure of a second identification unit provided in an embodiment of this application. Figure 11 As shown, in one possible implementation, the second identification unit 122 includes: a third sub-identification unit 1221 and a second latching unit 1222;
[0144] The third sub-identification unit 1221 is used to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, the second signal of the first state is sent to the second latch unit 1222; otherwise, the second signal of the second state is sent to the second latch unit 1222.
[0145] The second latch unit 1222 is connected to the third sub-identification unit 1221 and the third identification unit 123. If the second signal of the first state is received, the second signal of the first state is continuously output to the third identification unit 123 until a reset signal is received; otherwise, the second signal of the second state is output to the third identification unit 123.
[0146] In a specific implementation, the second identification unit 122 can be composed of a third sub-identification unit 1221 and a second latching unit 1222. The third sub-identification unit 1221 identifies whether the input signal has a first segment level with a special timing sequence based on the first signal, and identifies whether the input signal has a high level after the first segment level with the special timing sequence. Based on the identification result, it outputs a second signal to the second latching unit 1222. The second latching unit 1222 latches the received second signal of the first state and outputs it to the third identification unit 123 until it is reset. This allows the third identification unit 123 to further identify whether the duration of the high level of the input signal meets the requirements when the input signal has two consecutive low and high levels, thereby realizing the identification of whether the input signal has a special timing sequence.
[0147] In one possible implementation, the third sub-identification unit 1221 includes: an eighth resistor, a second inverter, and a fourth AND gate; wherein,
[0148] One end of the eighth resistor is connected to the first identification module, the other end of the eighth resistor is connected to the input of the second inverter, the output of the second inverter is connected to the first input of the fourth AND gate, the second input of the fourth AND gate receives the input signal, and the output of the fourth AND gate is connected to the output unit 1213.
[0149] Figure 12 This is a schematic diagram of an identification circuit provided in an embodiment of this application. Figure 12 As shown, the third sub-identification unit 1221 can adopt the same structure as the first sub-identification unit 1211. The third sub-identification unit 1221 and the first sub-identification unit 1211 can be reused, thereby reducing the number of components and reducing the cost and size of the encoder.
[0150] The second latch unit 1222 includes: a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a ninth resistor R11, a tenth resistor R12, an eleventh resistor R13, a twelfth resistor R15, a thirteenth resistor R16, and a third inverter U6; wherein,
[0151] The input terminal of the fourth transistor Q4 is connected to the control terminal of the fifth transistor Q5 and the output terminal of the sixth transistor Q6. The output terminal of the fourth transistor Q4 is grounded, and the control terminal of the fourth transistor Q4 receives a reset signal.
[0152] One end of the ninth resistor R11 is connected to the output of the fourth AND gate, the other end of the ninth resistor R11 is connected to the control terminal of the fifth transistor Q5, the input terminal of the fifth transistor Q5 is connected to one end of the tenth resistor R12, the other end of the tenth resistor R12 receives a high level, and the output terminal of the fifth transistor Q5 is grounded.
[0153] One end of the eleventh resistor R13 is connected to the input terminal of the fifth transistor Q5, the other end of the eleventh resistor R13 is connected to the control terminal of the sixth transistor Q6, one end of the twelfth resistor R15 is connected, the other end of the twelfth resistor R15 receives a high level, the input terminal of the sixth transistor Q6 receives a high level, the output terminal of the sixth transistor Q6 is connected to one end of the thirteenth resistor R16 and the input terminal of the third inverter U6, the other end of the thirteenth resistor R16 is grounded, and the output terminal of the third inverter U6 is connected to the third identification unit 123.
[0154] For example, the fifth transistor Q5 is an NPN transistor, and the sixth transistor Q6 is a PNP transistor.
[0155] For example, when the input signal does not have a special timing in the first stage, the first AND gate U4 outputs a low level. The control terminal of the fifth transistor Q5 is low, so the fifth transistor Q5 is not turned on. The control terminal of the sixth transistor Q6 is high, so the sixth transistor Q6 is not turned on. The output terminal of the sixth transistor Q6 is grounded, and the third inverter U6 outputs a high level.
[0156] For example, when the input signal has a specific timing level in the first segment, the first AND gate U4 outputs a high level. The control terminal of the fifth transistor Q5 is high, so the fifth transistor Q5 is turned on. The control terminal of the sixth transistor Q6 is low, so the sixth transistor Q6 is turned on. The output terminal of the sixth transistor Q6 is high, and the third inverter U6 outputs a low level.
[0157] Figure 13 This is a schematic diagram of the structure of a third identification unit provided in an embodiment of this application. Figure 13 As shown, in one possible implementation, the third identification unit 123 includes: a fourth sub-identification unit 1231 and a third latching unit 1232;
[0158] The fourth sub-identification unit 1231 is used to receive the input signal and the second signal. If the second signal of the first state is received and the input signal includes one high level and at least one low level, the first state protocol signal is sent to the third latch unit 1232; otherwise, the second state protocol signal is sent to the third latch unit 1232.
[0159] The third latch unit 1232 and the fourth sub-identification unit 1231 are connected to the main control chip. If the second signal of the first state is received, the first state protocol signal is continuously output to the main control chip until it is reset by the main control chip; otherwise, the second state protocol signal is output to the main control chip.
[0160] In its implementation, the fourth sub-identification unit 1231 identifies whether the input signal has a first segment level and a high level with a special timing sequence based on the second signal, and identifies whether the duration of the high level meets the requirements. Based on the identification result, it outputs a protocol signal to the third latching unit 1232. The second sub-identification unit 1212 latches the received protocol signal of the first state to the main control chip until it is reset by the RESET signal output by the main control chip, so that the main control chip processes the input signal according to the Tamagawa protocol under the action of the protocol signal of the first state.
[0161] The specific structure of the third identification unit is illustrated below.
[0162] In one possible implementation, the fourth sub-identification unit 1231 includes: a third delay unit, a second OR gate U7, and a third OR gate U8; wherein...
[0163] The input terminal of the third delay unit receives the input signal, and the output terminal of the third delay unit is connected to the first input terminal of the second OR gate U7.
[0164] The second input terminal of the second OR gate U7 receives the input signal, and the output terminal of the second OR gate U7 is connected to the first input terminal of the third OR gate U8.
[0165] The second input terminal of the third OR gate U8 is connected to the third sub-identification unit 1221, and the output terminal of the third OR gate U8 is connected to the third latch unit 1232.
[0166] like Figure 12 As shown, for example, the third delay unit can adopt the same structure as the second delay unit 12121. The third sub-identification unit 1221 and the second delay unit 12121 can be reused, thereby reducing the number of components and reducing the cost and size of the encoder.
[0167] For example, during the high level of the input signal, the second input terminal of the second OR gate U7 is high, the second OR gate U7 outputs a high level, the first input terminal of the third OR gate U8 is high, and the third OR gate U8 outputs a high level.
[0168] For example, when the input signal has only one high level, when the input signal just changes from the high level to the low level, after the delay by the third delay unit, the first input terminal of the second OR gate U7 is at a low level, the second input terminal of the second OR gate U7 is at a low level, and the output of the second OR gate U7 is low.
[0169] When at least two bits of the input signal are high, when the input signal just changes from high to low, after a delay by the third delay unit, the first input of the second OR gate U7 is high, the second input of the second OR gate U7 is low, and the output of the second OR gate U7 is high.
[0170] For example, only when the input signal has a first segment level of special timing, and the input signal has only one high level after the first segment level of special timing, both inputs of the third OR gate U8 are low, and the third OR gate U8 outputs a low level (the protocol signal of the first state); in other cases, the third OR gate U8 outputs a high level (the protocol signal of the second state).
[0171] In one possible implementation, the third latch unit 1232 includes: a seventh transistor Q7, an eighth transistor Q8, a fourteenth resistor R17, a fifteenth resistor R18, a sixteenth resistor R19, a seventeenth resistor R20, an eighteenth resistor R21, and a fifth resistor R7; wherein,
[0172] One end of the fourteenth resistor R17 is connected to the output terminal of the first OR gate U1, and the other end of the fourteenth resistor R17 is connected to the control terminal of the eighth transistor Q8, one end of the fifteenth resistor R18, and the other end of the fifteenth resistor R18 receives a high level.
[0173] The input terminal of the seventh transistor Q7 receives a high level, and the output terminal of the seventh transistor Q7 is connected to one end of the sixteenth resistor R19 and one end of the seventeenth resistor R20. The other end of the sixteenth resistor R19 is grounded.
[0174] The other end of the seventeenth resistor R20 is connected to the control terminal of the eighth transistor Q8. The input terminal of the eighth transistor Q8 is connected to one end of the eighteenth resistor R21 and the main control chip. The other end of the eighteenth resistor R21 receives a high level, and the output terminal of the eighth transistor Q8 is grounded.
[0175] For example, the seventh transistor Q7 is a PNP transistor, and the eighth transistor Q8 is an NPN transistor.
[0176] For example, when the input signal has a special timing, the third OR gate U8 outputs a low level, the control terminal of the seventh transistor Q7 is low, the seventh transistor Q7 is turned on, the control terminal of the eighth transistor Q8 is pulled high, the eighth transistor Q8 is turned on, the OUT output of the third latch unit 1232 is low (the protocol signal of the first state), and the control terminal of the seventh transistor Q7 is pulled low. The seventh transistor Q7 and the eighth transistor Q8 remain turned on, and OUT remains low, thus realizing latched output.
[0177] When there is no special timing for the input signal, when the output of the third OR gate U8 is high, the control terminal of the seventh transistor Q7 is high and the seventh transistor Q7 is not turned on, the control terminal of the eighth transistor Q8 is low and the eighth transistor Q8 is not turned on, and the OUT output of the third latch unit 1232 is high (the protocol signal of the second state).
[0178] This application also provides an integrated circuit chip, including the bus encoder as described above.
[0179] This integrated circuit chip can directly report multi-dimensional data such as position, speed, temperature, and fault status through two bus protocols, supporting predictive maintenance and advanced control algorithms.
[0180] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0181] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A bus encoder, characterized in that, include: Main control chip and identification circuit; The identification circuit is connected to the main control chip and is used to receive input signals and output corresponding protocol signals to the main control chip according to whether the input signals include a predetermined timing sequence; wherein, the predetermined timing sequence includes two consecutive low levels, one high level, and one low level. The main control chip is used to determine whether the input signal adopts the Tamagawa communication protocol according to the protocol signal, and to process the input signal according to the corresponding communication protocol.
2. The bus encoder according to claim 1, characterized in that, The identification circuit includes: a first identification module and a second identification module; The first identification module is used to receive the input signal. If there are two consecutive low levels in the input signal, it continuously outputs a first signal of a first state to the second identification module; otherwise, it outputs a first signal of a second state to the second identification module. The second identification module is connected to the first identification module and the main control chip, and is used to output a first state protocol signal to the main control chip if, according to the first signal, two consecutive low levels in the input signal are followed by one high level and one low level; otherwise, it outputs a second state protocol signal to the main control chip.
3. The bus encoder according to claim 2, characterized in that, The first identification module includes: a first identification unit and a first latching unit; The first identification unit and the first latch unit are connected and are used to receive the input signal. If the input signal has two consecutive low levels, the first signal of the first state is output to the first latch unit; otherwise, the first signal of the second state is output to the first latch unit. The first latch unit is connected to the second identification module and is used to continuously output the first signal of the first state to the second identification module if the first signal of the first state is received, until the reset signal sent by the second identification module is received; otherwise, it outputs the first signal of the second state to the second identification module.
4. The bus encoder according to claim 3, characterized in that, The first identification unit includes: a first delay unit and a first OR gate (U1); wherein, The input terminal of the first delay unit receives the input signal, and the output terminal of the first delay unit is connected to the first input terminal of the first OR gate (U1); The second input terminal of the first OR gate (U1) receives the input signal, and the output terminal of the first OR gate (U1) is connected to the first latch unit.
5. The bus encoder according to claim 4, characterized in that, The first latch unit includes: a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a first resistor (R2), a second resistor (R3), a third resistor (R4), a fourth resistor (R5), and a fifth resistor (R7); wherein, The input terminal of the first transistor (Q1) receives a high level, the output terminal of the first transistor (Q1) is connected to the control terminal of the second transistor (Q1), and the control terminal of the first transistor (Q1) receives the reset signal; One end of the first resistor (R2) is connected to the output terminal of the first OR gate (U1), the other end of the first resistor (R2) is connected to the control terminal of the second transistor (Q2), one end of the second resistor (R3) is connected, the input terminal of the second transistor (Q2) receives a high level, the output terminal of the second transistor (Q2) is connected to one end of the third resistor (R4), the other end of the third resistor (R4) is grounded, and the other end of the second resistor (R3) is connected to the input terminal of the second transistor (Q2). The input terminal of the third transistor (Q3) is connected to one end of the fifth resistor (R7) and the control terminal of the second transistor (Q3). The other end of the fifth resistor (R7) receives a high level. The output terminal of the third transistor (Q3) is grounded. One end of the fourth resistor (R5) is connected to the output terminal of the second transistor (Q2). The control terminal of the third transistor (Q3) is connected to the other end of the fourth resistor (R5).
6. The bus encoder according to claim 3, characterized in that, The second identification module includes: a reset unit, a second identification unit, and a third identification unit; The reset unit is used to receive the input signal and the first signal. If the first signal of the first state is received and there are at least two consecutive high levels in the input signal, a reset signal is sent to the first identification module and the second identification unit. The second identification unit is configured to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, the second signal of the first state is continuously sent to the third identification unit until the reset signal is received; otherwise, the second signal of the second state is sent to the third identification unit. The third identification unit is used to receive the input signal and the second signal. If the second signal of the first state is received, and the input signal includes one high level and at least one low level, then the first state protocol signal is continuously sent to the main control chip; otherwise, the second state protocol signal is sent to the main control chip.
7. The bus encoder according to claim 6, characterized in that, The reset unit includes: a first sub-identification unit, a second sub-identification unit, and an output unit; The first sub-identification unit is used to receive the first signal and the input signal. If the first signal of the first state is received and there is a high level in the input signal, then the third signal of the first state is output to the output unit. The second sub-identification unit is used to receive the input signal, and if the input signal has at least two consecutive high levels, it outputs a fourth signal of the first state to the output unit. The output unit is connected to the first sub-identification unit, the second sub-identification unit, the first identification module, and the second identification unit, and is used to output a reset signal to the first identification module and the second identification unit when receiving the third signal of the first state and the fourth signal of the first state.
8. The bus encoder according to claim 7, characterized in that, The second identification unit includes: a third sub-identification unit and a second latching unit; The third sub-identification unit is used to receive the input signal and the first signal. If the first signal of the first state is received and there is a high level in the input signal, then the second signal of the first state is sent to the second latching unit; otherwise, the second signal of the second state is sent to the second latching unit. The second latching unit is connected to the third sub-identification unit and the third identification unit, and is used to continuously output the second signal of the first state to the third identification unit if the second signal of the first state is received, until the reset signal is received; otherwise, it outputs the second signal of the second state to the third identification unit.
9. The bus encoder according to claim 8, characterized in that, The third identification unit includes: a fourth sub-identification unit and a third latching unit; The fourth sub-identification unit is used to receive the input signal and the second signal. If the second signal of the first state is received, and the input signal includes one high level and at least one low level, then the first state protocol signal is sent to the third latch unit; otherwise, the second state protocol signal is sent to the third latch unit. The third latch unit is connected to the fourth sub-identification unit and the main control chip. If the second signal of the first state is received, the latch unit continuously outputs the protocol signal of the first state to the main control chip until it is reset by the main control chip; otherwise, the latch unit outputs the protocol signal of the second state to the main control chip.
10. The bus encoder according to claim 7, characterized in that, The first sub-identification unit includes: a sixth resistor (R8), a first inverter (U2), and a first AND gate (U4); wherein, One end of the sixth resistor (R8) is connected to the first identification module, the other end of the sixth resistor (R8) is connected to the input terminal of the first inverter (U2), the output terminal of the first inverter (U2) is connected to the first input terminal of the first AND gate (U4), the second input terminal of the first AND gate (U4) receives the input signal, and the output terminal of the first AND gate (U4) is connected to the output unit. The second sub-identification unit includes: a second delay unit and a second AND gate (U3); wherein, The input terminal of the second delay unit receives the input signal, and the output terminal of the second delay unit is connected to the first input terminal of the second AND gate (U3); The second input terminal of the second AND gate (U3) receives the input signal, and the output terminal of the second AND gate (U3) is connected to the output unit; The output unit includes: a third AND gate (U5) and a seventh resistor (R10); wherein, The first input terminal of the third AND gate (U5) is connected to the second sub-identification unit, the second input terminal of the third AND gate (U5) is connected to the first sub-identification unit, the output terminal of the third AND gate (U5) is connected to one end of the seventh resistor (R10), and the other end of the seventh resistor (R10) is connected to the reset terminal of the first identification module and the reset terminal of the second identification module.
11. The bus encoder according to claim 8, characterized in that, The third sub-identification unit includes: an eighth resistor (R9), a second inverter (U2), and a fourth AND gate (U4); wherein, One end of the eighth resistor (R9) is connected to the first identification module, the other end of the eighth resistor (R9) is connected to the input terminal of the second inverter (U2), the output terminal of the second inverter (U2) is connected to the first input terminal of the fourth AND gate (U4), the second input terminal of the fourth AND gate (U4) receives the input signal, and the output terminal of the fourth AND gate (U4) is connected to the output unit. The second latch unit includes: a fourth transistor (Q4), a fifth transistor (Q5), a sixth transistor (Q6), a ninth resistor (R11), a tenth resistor (R12), an eleventh resistor (R13), a twelfth resistor (R15), a thirteenth resistor (R16), and a third inverter (U6); wherein, The input terminal of the fourth transistor (Q4) is connected to the control terminal of the fifth transistor (Q5) and the output terminal of the sixth transistor (Q6). The output terminal of the fourth transistor (Q4) is grounded, and the control terminal of the fourth transistor (Q4) receives the reset signal. One end of the ninth resistor (R11) is connected to the output of the fourth AND gate (U4), the other end of the ninth resistor (R11) is connected to the control terminal of the fifth transistor (Q5), the input terminal of the fifth transistor (Q5) is connected to one end of the tenth resistor (R12), the other end of the tenth resistor (R12) receives a high level, and the output terminal of the fifth transistor (Q5) is grounded. One end of the eleventh resistor (R13) is connected to the input terminal of the fifth transistor (Q5), the other end of the eleventh resistor (R13) is connected to the control terminal of the sixth transistor (Q6) and one end of the twelfth resistor (R15), the other end of the twelfth resistor (R15) receives a high level, the input terminal of the sixth transistor (Q6) receives a high level, the output terminal of the sixth transistor (Q6) is connected to one end of the thirteenth resistor (R16) and the input terminal of the third inverter (U6), the other end of the thirteenth resistor (R16) is grounded, and the output terminal of the third inverter (U6) is connected to the third identification unit.
12. The bus encoder according to claim 9, characterized in that, The fourth sub-identification unit includes: a third delay unit, a second OR gate (U7), and a third OR gate (U8); wherein, The input terminal of the third delay unit receives the input signal, and the output terminal of the third delay unit is connected to the first input terminal of the second OR gate (U7); The second input terminal of the second OR gate (U7) receives the input signal, and the output terminal of the second OR gate (U7) is connected to the first input terminal of the third OR gate (U8); The second input terminal of the third OR gate (U8) is connected to the third sub-identification unit, and the output terminal of the third OR gate (U8) is connected to the third latch unit; The third latch unit includes: a seventh transistor (Q7), an eighth transistor (Q8), a fourteenth resistor (R17), a fifteenth resistor (R18), a sixteenth resistor (R19), a seventeenth resistor (R20), an eighteenth resistor (R21), and a fifth resistor (R7); wherein, One end of the fourteenth resistor (R17) is connected to the output terminal of the first identification unit, and the other end of the fourteenth resistor (R17) is connected to the control terminal of the eighth transistor (Q8), one end of the fifteenth resistor (R18), and the other end of the fifteenth resistor (R18) receives a high level. The input terminal of the seventh transistor (Q7) receives a high level, the output terminal of the seventh transistor (Q7) is connected to one end of the sixteenth resistor (R19) and one end of the seventeenth resistor (R20), and the other end of the sixteenth resistor (R19) is grounded; The other end of the seventeenth resistor (R20) is connected to the control terminal of the eighth transistor (Q8). The input terminal of the eighth transistor (Q8) is connected to one end of the eighteenth resistor (R21) and the main control chip. The other end of the eighteenth resistor (R21) receives a high level, and the output terminal of the eighth transistor (Q8) is grounded.
13. The bus encoder according to any one of claims 1-12, characterized in that, The main control chip is used to process the input signal according to the protocol signal under the corresponding Tamagawa protocol or BiSS-C protocol.
14. An integrated circuit chip, characterized in that, Includes the bus encoder as described in any one of claims 1-13.