Processor global multi-mode unlocking method, processor, medium and program product

Abstract

The embodiment of the present disclosure discloses a processor global multi-mode unlocking method, a processor, a medium and a program product. The method comprises the following steps: setting a timer, which is used to record the duration of the microinstruction execution stagnation in the processor when the reorder unit is not empty; setting multiple unlocking modes and the exclusive threshold of each unlocking mode; triggering the corresponding unlocking mode to perform the unlocking operation when the duration is greater than the exclusive threshold of any unlocking mode and less than the maximum upper limit; determining the unlocking success when there is a new microinstruction submission, and resetting the timer; triggering a fatal error alarm when the duration is greater than or equal to the maximum upper limit. The method can break through the scene limitation of the module-level unlocking through the unlocking mechanism of globalization, multi-mode and supporting mixed calls, efficiently solve the microinstruction submission blocking problem caused by cross-module or global resources, and reduce the hardware redundancy and improve the adaptation ability to new abnormal scenes.

Description

Technical Field

[0001] This disclosure relates to the field of on-chip locking technology, and in particular to a processor global multi-mode unlocking method, processor, medium and program product. Background Technology

[0002] To improve performance, modern processors employ techniques such as out-of-order execution and speculative execution. Microinstructions must undergo multiple stages, including fetch, decode, issue, and execute, before retiring. However, in fixed-point, floating-point, and memory access modules, microinstructions may become trapped in deadlocks / livelocks due to resource preemption, data dependencies, or abnormal loops, preventing normal microinstruction retiring and thus blocking the entire execution pipeline. Existing technologies primarily employ module-level unlocking mechanisms. For specific abnormal scenarios in each module (such as the oldest instruction in a fixed-point module timeout failing to retiring, or memory access module memory port preemption), dedicated monitoring logic (such as counters or state machines) triggers corresponding unlocking operations (such as forced execution or reset arbitration) to resolve the problem of localized microinstruction retiring.

[0003] However, module-level unlocking only applies to the internal logic of a single module and cannot handle abnormal scenarios involving multi-module collaboration or global resources (such as ROB queue order-preserving submission rules), making it difficult to solve cross-module or global microinstruction submission blocking problems. Moreover, each type of livelock scenario caused by resource contention requires separate design of monitoring and unlocking logic. As processor architecture complexity increases and hardware redundancy increases significantly, it becomes difficult to adapt to new microinstruction submission abnormal scenarios. Summary of the Invention

[0004] In view of this, the present disclosure provides a processor global multi-mode unlocking method, processor, medium and program product, which can overcome the limitations of module-level unlocking scenarios through a global, multi-mode unlocking mechanism that supports mixed calls, efficiently solve the micro-instruction submission blocking problem caused by cross-module or global resources, and at the same time reduce hardware redundancy and improve adaptability to new abnormal scenarios.

[0005] In a first aspect, embodiments of this disclosure provide a processor global multi-mode unlocking method, employing the following technical solution: Set a timer to record the duration of the processor's internal microinstruction execution pause when the reordering unit is not empty; Set multiple unlock modes and a unique threshold for each unlock mode; When the duration is greater than the exclusive threshold of any unlock mode but less than the maximum limit, the corresponding unlock mode is triggered to perform the unlock operation; When a new microinstruction is submitted, the unlock is determined to be successful, and the timer is reset; A fatal error alarm is triggered when the duration is greater than or equal to the maximum limit.

[0006] Optionally, the unlocking mode includes at least one of the following: forced oldest microinstruction execution mode, order-preserving execution mode, stop-speculation mode, and redirection mode.

[0007] Optionally, the setting of multiple unlocking modes and a specific threshold for each unlocking mode includes: During the testing phase, the unlocking cost level and resolution capability boundary of each unlocking mode are evaluated, and a threshold encoding range for each unlocking mode is set based on the unlocking cost level and the resolution capability boundary. Construct a silicon-back-hanging scenario library and test the resolution rate and false trigger rate of each unlocking mode for all scenarios in the silicon-back-hanging scenario library under different threshold codes within the corresponding threshold coding range. Based on the resolution rate and false trigger rate, the optimal threshold code is determined from the threshold code range of each unlocking mode; Based on the optimal threshold encoding for each unlocking mode, obtain the initial exclusive threshold for each unlocking mode.

[0008] Optionally, the setting of multiple unlocking modes and a specific threshold for each unlocking mode further includes: During the application phase, after triggering any unlocking mode to perform an unlocking operation, the optimal threshold code of the unlocking mode is dynamically updated based on the unlocking result. Based on the optimal threshold encoding after the unlock mode update, update the exclusive threshold of the unlock mode.

[0009] Optionally, the processor global multi-mode unlocking method further includes: During the testing phase, the hardware fault tolerance limits and system recovery costs of the processor under different post-silicon hang-up scenarios were evaluated. Based on the hardware fault tolerance limit and the system recovery cost, a threshold encoding range for the fatal error alarm mechanism is set. The fatal error alarm mechanism was tested under different threshold encodings within the corresponding threshold encoding range to measure the interception rate of extreme unrecoverable hang-up scenarios and the false interception rate of unlockable and recoverable scenarios in the silicon hang-up scenario library. Based on the interception rate and the false interception rate, the optimal threshold code is determined from the threshold coding range of the fatal error alarm mechanism; Based on the optimal threshold encoding of the aforementioned fatal error alarm mechanism, the initial maximum upper limit is obtained.

[0010] Optionally, the processor global multi-mode unlocking method further includes: During the application phase, the duration of unresolved stall events that could not be recovered after all unlocking modes were triggered was statistically analyzed, as well as the effective interception rate of system reset and business interruption loss after the fatal error alarm mechanism was triggered. Based on the duration of the unresolved stall event, the effective interception rate, and the service interruption loss, the optimal threshold code of the fatal error alarm mechanism is dynamically updated; The maximum upper limit is updated based on the optimal threshold encoding updated by the aforementioned fatal error alarm mechanism.

[0011] Optionally, the specific threshold of the unlocking mode is equal to the product between the optimal threshold code of the unlocking mode and the global time base; The maximum upper limit is equal to the product of the optimal threshold number of the fatal error alarm mechanism and the global time base.

[0012] Optionally, the processor global multi-mode unlocking method further includes: Configure each bit field of the unlock configuration register based on the functional control requirements of each unlock mode; The bit field includes an enable control field, a global time base selection field, a mode combination control field, and a threshold coding selection field. Each bit in the enable control field is an enable bit for an unlock mode, used to enable or disable the corresponding unlock mode; The global time base selection field occupies independent bits and is used to dynamically switch the global time base; Each bit in the mode combination control field corresponds to a combination unlocking mode, which is used to authorize the mixed use of two unlocking modes; The bits in the threshold encoding selection field are used to select the optimal threshold encoding within the threshold encoding range for each unlocking mode and the fatal error alarm mechanism.

[0013] Optionally, the processor global multi-mode unlocking method further includes: When the triggered unlock mode is the forced oldest microinstruction execution mode, a pulse-type forced ready signal is sent to all execution units of the microinstruction; When each execution unit receives the forced ready signal, it searches and locates the entry in its internal launch queue that corresponds to the oldest uncommitted microinstruction in the reordering unit. The oldest microinstruction located is ignored if it was originally in a ready state, and is forced to be executed once in the execution pipeline; When the forced execution is successful, the oldest microinstruction completes execution and sends a completion signal to the reordering unit. After the reordering unit submits, the timer is reset. If forced execution fails, the forced oldest microinstruction execution mode is terminated, and the system waits for other unlocking modes or triggers a fatal error alarm.

[0014] Optionally, the processor global multi-mode unlocking method further includes: When the unlocking mode is the order-preserving execution mode, a level-based order-preserving execution signal is sent to all execution units and decoding units of the microinstruction. When the decoding unit receives the in-order execution signal, it performs microinstruction rate limiting; Upon receiving the in-order execution signal, each execution unit ceases to execute out-of-order scheduling. When the microinstruction already issued to the execution unit is the oldest uncommitted microinstruction in the reordering unit, the processor resources are temporarily transferred to the oldest microinstruction and an attempt is made to commit it. When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the order-preserving execution mode ends, and the system waits for another unlocking mode or triggers a fatal error alarm.

[0015] Optionally, the processor global multi-mode unlocking method further includes: When the triggered unlocking mode is the stop-speculation mode, a level-based no-speculation optimization signal is sent to the microinstruction decoding unit; When the decoding unit receives a no-speculation-optimization signal, it disables the speculative optimization function and attempts to submit the oldest microinstruction in the reordering unit. When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the Stop Speculation mode ends and waits for another unlock mode or triggers a fatal error alarm.

[0016] Optionally, the processor global multi-mode unlocking method further includes: When the triggered unlocking mode is the redirection mode, a synchronization flushing signal is sent to the reordering unit; When the reordering unit receives the synchronization flush signal, it performs a global synchronization refresh, clearing all unsubmitted micro-instructions in the pipeline. The processor's program counter is redirected to the original macro instruction address corresponding to the oldest microinstruction in the reordering unit; Starting from the original macro instruction address after redirection, the processor re-fetches, decodes, issues, and executes the instruction; When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the redirection mode ends and waits for another unlock mode or triggers a fatal error alarm.

[0017] Secondly, embodiments of this disclosure also provide a processor, the processor including a reordering unit, a timer, and a livelock detection unit; The reordering unit is used to send a high-level counting enable signal to the timer when it is not empty; The timer is used to record the duration of the pause in the execution of microinstructions inside the processor when the high-level counting enable signal is received. The livelock detection unit is used to trigger the corresponding unlocking mode to perform an unlocking operation when the duration is greater than the exclusive threshold of any unlocking mode but less than the maximum upper limit. The reordering unit is also used to determine that unlocking is successful when a new microinstruction is submitted, and to send a pulse signal to the timer. The timer is also used to reset upon receiving the pulse signal; The livelock detection unit is also used to trigger a fatal error alarm when the duration is greater than or equal to the maximum upper limit.

[0018] Optionally, the processor further includes an unlock configuration register; The unlock configuration register is used to store the global time base, the optimal threshold code for each unlock mode, and the fatal error alarm mechanism; The timer is used to read the global time base, the optimal threshold code for each unlock mode, and the fatal error alarm mechanism from the unlock configuration register; Based on the global time base, the optimal threshold encoding for each unlocking mode and the fatal error alarm mechanism, obtain the specific threshold and the maximum upper limit for each unlocking mode; The duration is compared in parallel with the specific threshold for each unlocking mode and the maximum upper limit; Based on the comparison results, generate and output the corresponding event signals; The livelock detection unit is used to determine and execute the triggered unlocking mode or fatal error alarm mechanism based on the received event signal.

[0019] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform any of the processor-global multi-mode unlocking methods described above.

[0020] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to execute any of the processor global multi-mode unlocking methods described above.

[0021] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0022] The processor global multi-mode unlocking method provided in this disclosure can accurately capture the execution blocking state at the global level of the processor by starting a timer to monitor the microinstruction execution stagnation duration when the reordering unit is not empty. It also sets multiple unlocking modes and dedicated thresholds, triggering appropriate unlocking operations based on differences in stagnation duration. This overcomes the limitation of module-level unlocking, which only addresses specific problems, and provides a reliable solution to deadlock problems that cannot be fixed by engineering changes (ECO) in the post-silicon stage. Furthermore, this solution offers both flexibility and security advantages. The threshold-triggered mechanism allows multiple unlocking modes to be executed simultaneously or in stages, enabling mixed deployment and on-demand triggering. It can quickly restore processor operation through targeted unlocking operations when the stagnation duration does not reach the dangerous threshold, and can promptly reset the timer after a new microinstruction is successfully submitted, ensuring a closed-loop effectiveness of the unlocking operation. The setting of the maximum upper limit threshold can trigger a fatal error alarm when the stagnation duration exceeds the safe range, preventing secondary damage to the processor from invalid unlocking operations. This achieves full-process control of accurate unlocking, effect verification, and risk mitigation, significantly improving the processor's operational stability and fault tolerance in complex post-silicon application scenarios. In summary, this method implements a general unlocking scheme for global, uncertain deadlocks in silicon-based systems, effectively solving the technical pain point that traditional module-level unlocking mechanisms cannot cover cross-module abnormal scenarios.

[0023] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic flowchart illustrating the processor global multi-mode unlocking method provided in this embodiment of the disclosure; Figure 2 A simplified diagram of the processor framework provided in this disclosure embodiment; Figure 3 A flowchart illustrating the unlocking mode-specific threshold acquisition method provided in this embodiment of the disclosure; Figure 4 A flowchart illustrating the unlock mode-specific threshold update method provided in this embodiment of the disclosure; Figure 5 A flowchart illustrating the method for unlocking the forced oldest microinstruction execution mode provided in this embodiment of the disclosure; Figure 6 A flowchart illustrating the order-preserving execution mode unlocking method provided in this embodiment of the disclosure; Figure 7 A flowchart illustrating the method for unlocking the stop-speculation mode provided in this embodiment of the disclosure; Figure 8 A flowchart illustrating the redirection mode unlocking method provided in this embodiment of the disclosure; Figure 9 A flowchart illustrating the maximum upper limit acquisition method provided in this embodiment of the disclosure; Figure 10 A flowchart illustrating the maximum upper limit update method provided in this embodiment of the disclosure; Figure 11 A schematic block diagram of a processor provided for embodiments of this disclosure; Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0029] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0030] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0031] Reference Figure 1 This disclosure provides a processor global multi-mode unlocking method, including the following steps: S1: Set a timer to record the duration of the processor's internal microinstruction execution pause when the reordering unit is not empty; S2: Set multiple unlocking modes and exclusive thresholds for each unlocking mode; S3: When the duration exceeds the exclusive threshold of any unlock mode but is less than the maximum limit, the corresponding unlock mode is triggered to perform the unlock operation; S4: When a new micro-instruction is submitted, the unlock is determined to be successful, and the timer is reset; S5: When the duration is greater than or equal to the maximum limit, a fatal error alarm is triggered.

[0032] The processor global multi-mode unlocking method disclosed herein can accurately capture the execution blocking state at the global level of the processor by starting a timer to monitor the microinstruction execution stall duration when the reordering unit is not empty. At the same time, it can set multiple unlocking modes and exclusive thresholds, and can trigger an appropriate unlocking operation according to the difference in stall duration. This breaks through the limitation of module-level unlocking which is only for specific problems, and provides a reliable solution to the deadlock problem that cannot be fixed by engineering change (ECO) in the post-silicon stage.

[0033] Furthermore, this solution offers the dual advantages of flexibility and security. The threshold-triggered mechanism allows multiple unlocking modes to be executed simultaneously or in stages, enabling hybrid deployment and on-demand triggering. This allows for rapid processor recovery through targeted unlocking operations when the stagnation time does not reach the dangerous threshold, and timely timer reset after successful submission of new microinstructions, ensuring a closed-loop effectiveness of the unlocking operation. The maximum upper limit threshold setting triggers a fatal error alarm when the stagnation time exceeds the safe range, preventing secondary damage to the processor from invalid unlocking operations. This achieves full-process control of precise unlocking, effect verification, and risk mitigation, significantly improving the processor's operational stability and fault tolerance in complex post-silicon application scenarios.

[0034] In summary, this method implements a general unlocking scheme for global, uncertain deadlocks in silicon-based systems, effectively solving the technical pain point that traditional module-level unlocking mechanisms cannot cover cross-module abnormal scenarios.

[0035] In S1, refer to Figure 2The schematic diagram of the processor framework shown includes an Instruction Fetch Unit (IFU), an Instruction Decode Unit (IDU), a Rename Unit, a Re-Order Buffer (ROB), and an Execution Unit (EU). The Execution Unit includes an Integer Execution Unit (IEU), a Floating-Point Unit (FPU), and a Load-Store Unit (LSU). These components work together to complete instruction fetching, decoding, execution, and commit, and are equipped with a stall monitoring and unlocking mechanism to ensure operational stability. The instruction fetch unit retrieves the instruction code from memory. The decoding unit breaks down the instruction code into microinstructions and issues them to the renaming unit. After receiving the microinstructions, the renaming unit queries the renaming mapping table to map the architecture registers in the microinstructions to physical registers. At the same time, it allocates new physical registers for the target architecture registers, thereby eliminating false dependencies between instructions and improving the out-of-order execution efficiency of the execution units. After completing the register renaming, the renaming unit forwards the microinstructions to the reordering unit. After receiving the microinstructions, the reordering unit distributes them to the corresponding fixed-point, floating-point, or memory-access execution units according to the microinstruction type, and records the instruction information in the reordering unit. Each execution unit executes the microinstructions out of order, and after execution, it feeds back the result information to the reordering unit. The reordering unit then strictly submits the execution results to the architecture registers or memory in the original instruction order. The reordering unit is the core buffer and control unit in the out-of-order execution architecture of the processor. Its function is to temporarily store the decoded and dispatched microinstructions that have not been executed, as well as the microinstructions that have been executed but have not yet been committed. It also completes the final commit (retire) of instructions and writes back the results in the original program instruction order. At the same time, it is responsible for the accurate rollback of abnormal instructions, thereby ensuring the semantic correctness of the program in the out-of-order execution mode.

[0036] The processor also includes a timer, using a watchdog timer (WDT) as the core timing component. This timer is equipped with an independent counting clock source and a configurable counting period, and is used to accurately record the duration of microinstruction execution pauses inside the processor when the reordering unit is not empty.

[0037] The reordering unit and the timer are linked via hardware level signals. When there are uncommitted microinstructions in the reordering unit (i.e., the reordering unit is not empty), a high-level count enable signal is continuously output to the timer's enable port. Upon receiving this high-level signal, the timer first checks if any instructions have been committed. If so, it resets the count. If no instructions have been committed, it further checks whether the processor is in a sleep-stall or wait-for-stall state. Sleep-stall refers to a scenario where the processor suspends instruction commits by actively entering a low-power sleep state, which is a normal power management behavior and not an abnormal stagnation. Wait-for-stall refers to a transitional state where the processor has detected a potential stagnation risk but has not yet entered a formal stagnation (e.g., waiting for data return due to cache miss). If either of these states is present, the timer maintains its count; if neither of these states is present, the count is incremented by 1, thus accurately accumulating the stagnation duration when the reordering unit is not empty and no valid instructions have been committed. When the reordering unit is empty (no uncommitted microinstructions), the reordering unit outputs a low-level signal. When the timer receives the low level, it stops counting and maintains the current count value until it receives a high-level enable signal again, at which point it restarts counting. This enables precise monitoring of the duration of microinstruction pause when the reordering unit is not empty.

[0038] In S2, refer to Figure 3 The flowchart illustrating the method for obtaining the unlock mode-specific thresholds shows the following steps: "Setting multiple unlock modes and their respective thresholds" S21: During the testing phase, evaluate the unlocking cost level and resolution capability boundary of each unlocking mode, and set the threshold coding range for each unlocking mode based on the unlocking cost level and resolution capability boundary. S22: Construct a silicon-based dead-end scenario library and test the resolution rate and false trigger rate of each unlocking mode for all scenarios in the silicon-based dead-end scenario library under different threshold codes within the corresponding threshold coding range. S23: Based on the resolution rate and false trigger rate, determine the optimal threshold code from the threshold coding range of each unlocking mode; S24: Based on the optimal threshold encoding for each unlocking mode, obtain the initial exclusive threshold for each unlocking mode.

[0039] In S21, several unlocking modes are configured, including at least one of the following: Unlock forceOldest Ready, Unlock In order execute, Unlock NoSpec-Optimize, and Unlock Redirect. Based on pre-production engineering samples and simulation platforms, the unlocking cost and capability are evaluated for each unlocking mode. The unlocking cost level is a grading standard that measures the resource overhead and performance loss to the processor after the unlocking mode is executed. It is divided into two dimensions: hardware resource overhead and performance loss. For example, the force oldest microinstruction execution mode only releases local register resources, and its cost level is low; the redirection mode requires redirecting the instruction flow and refreshing the pipeline, and its cost level is high. The resolution capability boundary is used to define the range of post-silicon deadlock scenarios that each unlocking mode can effectively resolve. It is determined by traversing typical cases (such as ready signal deadlock, resource contention deadlock, etc.) in the post-silicon deadlock scenario library. Based on the evaluation results, threshold coding ranges are defined for unlocking modes with different cost levels and capability boundaries. For example, the forced oldest microinstruction execution mode, the order-preserving execution mode, and the stop-speculation mode correspond to short-term stagnation triggers, so the threshold coding range for these three unlocking modes is set to (0~31). The redirection mode corresponds to long-term stagnation triggers and needs to be used later, so its threshold coding range is set to (0~63). This method ensures that the low-cost, narrow-boundary mode threshold range is smaller and earlier, while the high-cost, wide-boundary fallback mode threshold range is larger and later, avoiding the mis-triggering of high-cost modes by low-risk stagnation.

[0040] In S22, all hang cases from pre-production stress tests, edge scenario simulations, and customer feedback rehearsals are collected and categorized by hang type (ready signal deadlock, speculative execution rollback deadlock, timing race hang, etc.), triggering conditions (load type, number of threads, instruction sequence), and severity level (critical, normal). These cases are then tagged, for example, [ready signal deadlock] - [single-thread] - [floating-point instruction] - [normal]. Based on the collected information, a post-silicon hang scenario library is constructed. For each unlocking mode, tests are conducted at each preset threshold encoding range. At each encoding range, the hang case matching the scenario library is repeatedly triggered M times (e.g., 100 times). Simultaneously, N instruction sequences (e.g., 10,000) are run in normal execution scenarios. The resolution rate (the percentage of times the hang is successfully unlocked) and the false trigger rate (the percentage of times the unlock is falsely triggered in normal scenarios) are calculated. For example, when testing the redirection mode, with a threshold encoding of 20, the resolution rate for resource contention deadlock cases is 98%, and the false trigger rate in ordinary computing scenarios is 0.08%.

[0041] In S23, quantitative screening criteria are set, such as "resolution rate ≥ 99% and false trigger rate ≤ 0.1%", and test data for each unlocking mode within the threshold coding range are screened. The lowest threshold code that meets the screening criteria is selected as the optimal threshold code to balance unlocking timeliness and system stability. If no threshold code within the threshold coding range of a certain mode fully meets the criteria, the threshold code with the best combined resolution rate and false trigger rate is selected. For example, the forced oldest micro-instruction execution mode has a resolution rate of 98.5% and a false trigger rate of 0.05% when the threshold code is 12, which is better than the threshold codes of other levels within the range. Therefore, the threshold code of 12 is determined to be the optimal threshold code.

[0042] In S24, the global time base (e.g., 1.28μs / level) is obtained. The specific threshold of the unlock mode is equal to the product of the optimal threshold code of the unlock mode and the global time base. For example, if the optimal threshold code for the forced oldest microinstruction execution mode is 12 and the time base is 1.28μs, then its initial specific threshold is 15.36μs, meaning that when the microinstruction stagnation time reaches 15.36μs, the unlock mode is triggered. The global time base has multiple value levels. The current value level of the global time base is determined based on the processor's operating scenario and stagnation monitoring requirements. For example, in high-performance computing scenarios, a small time base level (e.g., 1.28μs) is selected to achieve accurate and fast monitoring of short-term stagnation; in low-power or latency-insensitive scenarios, a large time base level (e.g., 1.31ms) is selected to reduce the hardware computational overhead of WDT and balance monitoring accuracy and system resource consumption.

[0043] Reference Figure 4 The flowchart illustrating the unlock mode-specific threshold update method further includes the following steps: "Setting multiple unlock modes and their respective thresholds": S25: During the application phase, after triggering any unlock mode to perform an unlock operation, the optimal threshold code of the unlock mode is dynamically updated based on the unlock result. S26: Update the exclusive threshold for the unlock mode based on the optimal threshold encoding after the unlock mode update.

[0044] In S25, during the mass production and application phase of the chip, an unlocking result log module is configured for the livelock detection unit to record the execution result after each unlocking mode is triggered, including three states: "unlock successful," "unlock failed," and "false trigger in normal scenario." Among them, the latter two states are abnormal states. When a certain unlocking mode has a preset number of abnormal results (such as 3 consecutive unlock failures or 5 consecutive false triggers in normal scenario), the use of the current optimal threshold code for that mode is suspended. Based on the latest operating data, all threshold codes within its threshold code range are re-traversed, and the real-time resolution rate and false trigger rate of each threshold code in the current actual business scenario are calculated. Then, according to the screening criteria of "resolution rate ≥ 99% and false trigger rate ≤ 0.1%", the optimal threshold code that meets the requirements is selected to complete the update, ensuring that the new code adapts to the stagnation characteristics of the current scenario.

[0045] In S26, based on the updated optimal threshold code from step S25 and combined with the global time base stored in the unlock configuration register, the new exclusive threshold for this unlocking mode is calculated using the formula: New Exclusive Threshold = Updated Optimal Threshold Code × Global Time Base.

[0046] Through a comprehensive design that includes tiered evaluation during the testing phase, quantitative screening of optimal coding, and dynamic iterative updating of thresholds during the application phase, the system accurately matches the cost level and resolution capability boundary of the unlocking mode in the early stages, ensuring that the initial threshold balances unlocking timeliness and low false trigger rate. Furthermore, it optimizes threshold parameters in real time based on unlocking results during actual operation, enabling the unlocking mechanism to continuously adapt to the stagnation characteristics of business scenarios. This effectively improves the resolution rate of post-silicon hang-up scenarios, reduces the risk of false triggering of normal instructions, and minimizes invalid calls to high-cost unlocking modes, thus ensuring the stability and performance efficiency of processor operation.

[0047] Based on the functional control requirements of each unlocking mode, the bit fields of the unlocking configuration register are configured. This requires identifying the core parameters that the register needs to carry, including the optimal threshold code and enable state, and reserving an independent bit field for the fatal error alarm mechanism. The bit width is divided according to the parameter value range, such as allocating 1 bit for the enable state. The mapping relationship and read / write permissions of each bit field are clarified. The initial optimal threshold code and default enable state determined in the testing phase are written into the corresponding bit fields to complete the initialization configuration of the unlocking configuration register. The bit fields include an enable control field, a global time base selection field, a mode combination control field, and a threshold code selection field. Each bit in the enable control field is an enable bit for a specific unlocking mode, used to use or disable the corresponding unlocking mode. The global time base selection field occupies independent bits and is used to dynamically switch the global time base. Each bit in the mode combination control field corresponds to a combined unlocking mode, used to authorize the mixed use of two unlocking modes. The bits in the threshold code selection field are used to select the optimal threshold code within the threshold code range of each unlocking mode. Referring to the bit allocation table for unlocking the configuration register, in the register bit field allocation of the processor microarchitecture, bits 29 to 63 of the register are used for unlocking. A portion of the bit allocation table is as follows: Based on the bit allocation table, bits 0-3 are independent enable bits for four unlocking modes. When a bit is configured to 1, the corresponding unlocking mode is activated. If the microinstruction pause duration reaches the threshold specific to that mode, the unlocking operation is triggered. When configured to 0, even if the pause duration exceeds the threshold, the unlocking mode will not be triggered. Bit 4 is the global time base selection bit, used to switch the time unit (ms or μs) for threshold calculation. Bits 5-9, 10-14, and 15-19 are all 5 bits, corresponding to a value range of 0-31, which are the threshold encoding ranges for the forced oldest microinstruction execution mode, the order-preserving execution mode, and the stop-speculation mode, respectively. Bits 20-25, a total of 6 bits, corresponding to a value range of 0-63, are the threshold encoding range for the redirection mode. Bits 26-28 are configuration bits for the mixed use of multiple unlocking mechanisms, used to define the linkage execution logic of different unlocking modes, and can reserve other idle bits for expanding the configuration requirements of more combined unlocking modes. Note that when a new optimal threshold code is obtained, it needs to be written to the corresponding bit field of the unlock configuration register to overwrite the original value, so that the timer can perform a comparison operation based on the updated value in subsequent stagnation monitoring and output an accurate event trigger signal.

[0048] In S3, refer to Figure 2The processor also includes an unlock configuration register and a livelock detection unit. The unlock configuration register adopts a hardware register architecture, with read-write isolation of each bit field achieved through hardware logic to ensure the stability of configuration parameters such as the global time base and optimal threshold code. The timer integrates a multi-channel parallel counting unit, which synchronously reads the global time base (ms / μs selectable) and the optimal threshold code for each unlock mode from the unlock configuration register via the AXI bus interface. A hardware multiplier performs real-time calculation of "dedicated threshold = global time base × optimal threshold code", and the calculation result is stored in the threshold cache unit inside the timer. When the timer detects a microinstruction pause (no microinstruction submission), it starts timing and obtains the pause duration. The multi-channel comparator inside the timer performs a parallel hardware comparison of the pause duration with the dedicated threshold for each unlock mode. The comparison result is implemented in the form of a corresponding event signal, such as a level signal (high level indicates that the threshold has been reached, low level indicates that it has not been reached) output to the signal decoding module of the livelock detection unit. The livelock detection unit identifies the enabled state of the triggered unlock mode through the decoding module (effective when the enable bit is 1), and drives the corresponding hardware execution unit to complete the unlock operation.

[0049] Reference Figure 5 The flowchart illustrates the method for unlocking the forced oldest microinstruction execution mode. The method includes the following steps: S31: When the triggered unlock mode is the forced oldest microinstruction execution mode, a pulse-type forced ready signal is sent to all execution units of the microinstruction; S32: When each execution unit receives the forced ready signal, it searches for and locates the entry corresponding to the oldest uncommitted microinstruction in the internal issue queue. S33: Ignore the original ready state of the oldest microinstruction located and force it to be executed once in the execution pipeline; S34: When forced execution is successful, the oldest microinstruction completes execution and sends a completion signal to the reordering unit. After the reordering unit submits, the timer is reset. S35: When forced execution fails, terminate the forced oldest microinstruction execution mode and wait for other unlock modes or trigger a fatal error alarm.

[0050] In S31-S35, the forced execution mode of the oldest microinstruction is a hardware unlocking mechanism designed for processor post-silicon livelock scenarios. It is specifically used to break typical deadlocks caused by Ready signal blocking and microinstruction scheduling obstruction. This mode is triggered when the timer value reaches the threshold specific to this mode, the corresponding enable bit in the unlock configuration register is set to 1, and there are uncommitted microinstructions in the reordering buffer. The core logic is to ignore the original ready state of the oldest uncommitted microinstruction and force it into the execution pipeline for execution, thereby breaking the resource preemption deadlock and restoring normal pipeline flow.

[0051] When this mode is triggered, the hardware module completes the unlocking operation according to the following steps: The livelock detection unit sends a single-clock-cycle pulse-type ForceReady signal to all execution units of the microinstruction (including fixed-point arithmetic units, floating-point arithmetic units, and memory access units) through its internal hardware signal drive circuit. This signal is active high, ensuring that each execution unit receives the trigger instruction synchronously within the same clock cycle. After receiving the ForceReady signal, each execution unit starts its internal commit instruction pointer (RetPtr) comparison logic. Through the hardware address mapping circuit, it searches for and locates the entry in its own issue queue that corresponds to the oldest uncommitted microinstruction in the reordering unit, ensuring the uniqueness and accuracy of the microinstruction to be executed. In other words, the hardware circuit compares the commit instruction pointer of the microinstruction in the execution unit's issue queue bit by bit with the commit instruction pointer of the oldest uncommitted microinstruction in the reordering unit to accurately locate the target microinstruction. After the execution unit locates the target microinstruction, its internal ready state control hardware ignores the original ready signal state of the microinstruction and forcibly sends the microinstruction into the execution pipeline through a hardware switching circuit. It also locks other scheduling requests in the pipeline to prevent interference from other microinstructions during the forced execution process. If the forced execution is successful, after the target microinstruction completes its computation, the execution unit sends an execution completion signal to the reordering unit via the result feedback bus. Upon receiving the signal, the reordering unit triggers the microinstruction submission process. Simultaneously, it resets the timer via a dedicated control signal, clearing the duration of the microinstruction execution pause, and the unlocking process ends normally. If the forced execution fails (e.g., core computing resources are still occupied, or there is an unrecoverable hardware failure), the execution unit sends an execution failure level signal to the livelock detection unit. Upon receiving the signal, the livelock detection unit immediately shuts down the hardware driver circuit for the current mode, ending the unlocking attempt for that mode. The system continues to maintain a pause monitoring state, waiting for the timer to trigger another unlocking mode or a fatal error alarm.

[0052] This forced oldest microinstruction execution mode can accurately resolve livelock scenarios caused by unset ready signals and prolonged microinstruction delays in the issue queue. By forcibly scheduling the oldest unsubmitted microinstruction for execution, it breaks the deadlock of resource preemption and quickly restores the processor pipeline's instruction scheduling and execution capabilities. Furthermore, this mode only performs a single forced scheduling of the oldest microinstruction, without interfering with the execution of other normal microinstructions, resulting in low hardware overhead and fast unlocking response. When this mode fails, the system can seamlessly switch to other unlocking modes to continue attempting, or trigger an alarm mechanism after all unlocking modes have failed and the stall duration has reached the maximum limit for fatal error alarms.

[0053] Reference Figure 6 The flowchart illustrates the unlocking method for the order-preserving execution mode. The unlocking method for the order-preserving execution mode includes the following steps: S36: When the triggered unlock mode is the order-preserving execution mode, send a level-based order-preserving execution signal to all execution units and decoding units of the microinstruction; S37: When the decoding unit receives the in-order execution signal, it performs microinstruction current limiting; S38: Upon receiving the in-order execution signal, each execution unit stops executing out-of-order scheduling; S39: When the microinstruction already issued to the execution unit is the oldest uncommitted microinstruction in the reordering unit, the processor resources are temporarily transferred to the oldest microinstruction and an attempt is made to commit it; S310: When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit. The timer is reset after the reordering unit submits the signal. S311: When the attempt fails, end the order-preserving execution mode and wait for another unlock mode or trigger a fatal error alarm.

[0054] In S36-S311, the order-preserving execution mode is a hardware unlocking mechanism designed for livelock scenarios caused by multi-threaded resource preemption and competition for microinstruction resources within the same thread. It specifically addresses the issues of unfair multi-threaded arbitration and execution stagnation caused by competition for resources between new and old microinstructions within the same thread. Its core logic is to force the execution unit to stop out-of-order scheduling and the decoding unit to implement differentiated rate limiting, prioritizing the allocation of processor resources to the oldest uncommitted microinstruction in the reordering unit. This breaks the deadlock of resource contention and restores the normal execution and commit of instructions.

[0055] When the pre-order execution mode is triggered, the hardware module completes the unlocking operation according to the following steps: The livelock detection unit sends a high-level active level inorder execution signal (InorderExecute) to all execution units and decoding units of the microinstruction through its internal hardware signal drive circuit. This signal remains active until the end of the unlocking process, ensuring that the relevant hardware units maintain the pre-order execution state. After receiving the inorder execution signal, the decoding unit starts its internal thread identification and rate limiting control logic: For the decoding channel that is in the same thread as the oldest unsubmitted microinstruction in the reordering unit, it uses a hardware counter and gating circuit to limit it to decoding and issuing only one microinstruction at a time, preventing resource contention caused by multiple instructions being issued in parallel; for the decoding channel that is in a different thread from the oldest microinstruction, it directly disables the issue enable through a hardware switch, stopping the delivery of any new microinstructions to the execution pipeline. After receiving the inorder execution signal, each execution unit immediately disables the hardware enable of its internal out-of-order scheduler and suspends the out-of-order execution logic based on instruction priority. The execution unit initiates the instruction submission pointer comparison circuit to verify in real time whether the microinstructions issued to the unit are the oldest unsubmitted microinstructions in the reordering unit. Only when the pointers match is the microinstruction allowed to occupy computing resources for execution. At this time, the resource allocation strategy is adjusted, temporarily allocating core processor resources such as computing units, memory bandwidth, and register ports to the thread containing the oldest microinstruction, while restricting resource requests from other threads. Once the oldest microinstruction passes the pointer matching verification, the execution unit immediately starts the computation process. If the computation is completed, the execution unit sends an execution completion signal to the reordering unit through the result feedback bus. The reordering unit triggers the submission process for that microinstruction. After submission, a dedicated control signal resets the timer, clearing the count value to zero, and the unlocking process ends normally. If the oldest microinstruction fails to execute or submit due to reasons such as continuous occupation of core resources or hardware logic abnormalities, the execution unit sends a failure level signal to the livelock detection unit. The livelock detection unit then shuts down the output of the in-order execution signal, ending the current in-order execution mode. The system continues to maintain a stagnant monitoring state, waiting for the timer to trigger other unlocking modes or trigger a fatal error alarm.

[0056] This order-preserving execution mode can accurately resolve two typical livelock scenarios: first, the failure of a thread to preempt resources due to unfair arbitration in a multi-threaded environment; and second, the execution stagnation caused by the competition for resources between new and old microinstructions within the same thread. Through a three-layer hardware control logic of "decoding rate limiting + disabling out-of-order execution + dedicated resource transfer," it forcibly locks the execution focus on the oldest uncommitted microinstruction, avoiding execution deadlock caused by resource dispersion. Furthermore, this mode only adjusts the resource allocation strategy during the unlocking period; after unlocking, the hardware unit automatically restores the default scheduling logic, without affecting the processor's normal high-performance operation.

[0057] Reference Figure 7The flowchart illustrating the method for unlocking the Stop Speculation mode is shown. The method for unlocking the Stop Speculation mode includes the following steps: S312: When the triggered unlocking mode is the stop-speculation mode, a level-based no-speculation optimization signal is sent to the microinstruction decoding unit; S313: When the decoding unit receives a no-speculation optimization signal, it disables the speculative optimization function and attempts to submit the oldest microinstruction in the reordering unit. S314: When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit. The timer is reset after the reordering unit submits the signal. S315: When the attempt fails, end the stop-speculation mode and wait for another unlock mode or trigger a fatal error alarm.

[0058] In S312-S315, the Stop Speculation Mode is a hardware unlocking mechanism designed for livelock scenarios caused by abnormal speculative optimization operations in the processor. It specifically addresses the stalling problem caused by repeated execution of instruction micro-operations resulting in continuous resync faults. Its core logic is to disable the speculative optimization function of the decoding unit to avoid repeated instruction resynchronization caused by speculative operations in abnormal scenarios, while prioritizing the submission of the oldest micro-instruction in the reordering unit to break the cyclical stalling deadlock.

[0059] When the stop-speculation mode is triggered, the hardware module completes the unlocking operation in the following orderly manner: The livelock detection unit sends a high-level active level no-speculation optimization signal (NoSpecOpt) to the processor's decoding unit through its internal hardware signal drive circuit. This signal remains active until the end of the unlocking process, ensuring that the decoding unit stably maintains a non-speculation working state. The decoding unit integrates a speculative function control module. Upon receiving the no-speculation optimization signal, it immediately disables all speculative optimization logic through a hardware switch, such as disabling core speculative operations like instruction fusion. This stops the hardware logic that merges two independent instructions into one micro-operation, forcibly restoring the working mode of decoding and generating micro-operations independently for each instruction, thus preventing repeated triggering of resynchronization faults caused by instruction fusion anomalies. While disabling the speculative optimization function, the decoding unit obtains information about the oldest uncommitted micro-instruction in the reordering unit through the hardware interface with the reordering unit and initiates a dedicated commit process: it locates the decoding entry corresponding to the oldest micro-instruction by comparing the instruction commit pointer, prioritizes the allocation of decoding resources to complete subsequent auxiliary processing, and pushes it to the execution unit for execution. If the oldest microinstruction is successfully executed, the execution unit sends an execution completion signal to the reordering unit via the result feedback bus. Upon receiving the signal, the reordering unit immediately triggers the commit process for that microinstruction. After committing, it resets the timer via a dedicated control signal, clearing the count value to zero, and the current unlocking process ends normally. If the execution or commit attempt of the oldest microinstruction fails due to hardware failure, continuous occupation of core resources, or other reasons, the decoding unit sends a failure level signal to the livelock detection unit. Upon receiving the signal, the livelock detection unit immediately stops outputting the no-speculation optimization signal, disables the hardware logic of the dedicated commit process, and ends the current stop-speculation mode. The system will continue to maintain a stagnation monitoring state, waiting for the timer to trigger other unlocking modes, or triggering a subsequent alarm mechanism when all unlocking modes have failed and the stagnation time reaches the fatal error alarm limit.

[0060] This stop-speculation mode is highly effective in resolving specific livelock scenarios, particularly in situations where repeated execution of instruction micro-operations leads to continuous resynchronization failures. For example, after instruction fusion is implemented within the core using fuses, when an exception occurs, the abnormal instruction cannot be accurately located. Instructions that should be split and resynchronized continue to fuse due to incorrect conditions, leading to repeated resynchronization until livelock occurs. By forcibly disabling speculative optimization, the loop stagnation caused by abnormal speculative behavior can be eliminated, while prioritizing the submission of the oldest micro-instruction to quickly restore the normal timing of instruction execution. Furthermore, this mode only temporarily disables speculative functionality during unlocking; after unlocking, the decoding unit automatically reverts to the default speculative optimization logic, without causing long-term impact on the processor's normal operating performance.

[0061] Reference Figure 8The flowchart illustrates the redirection mode unlocking method, which includes the following steps: S316: When the triggered unlocking mode is redirection mode, send a synchronization flushing signal to the reordering unit; S317: When the reordering unit receives the synchronization flush signal, it performs a global synchronization refresh, clearing all uncommitted micro-instructions in the pipeline. S318: Redirects the processor's program counter to the address of the original macro instruction corresponding to the oldest microinstruction in the reordering unit; S319: Starting from the original macro instruction address after redirection, the processor fetches, decodes, issues, and executes the instruction again; S320: When the oldest microinstruction is successfully committed, a completion signal is sent to the reordering unit. The timer is reset after the reordering unit commits. S321: When the attempt fails, end the redirection mode and wait for another unlock mode or trigger a fatal error alarm.

[0062] In S316-S321, the redirection mode is a hardware unlocking mechanism designed for livelock scenarios caused by specific execution modes or timing-related anomalies in the processor. It specifically addresses the problem of continuous stalling caused by encountering specific abnormal modes or timing-related extreme scenarios during core execution. Its core logic is to clear the abnormal instruction state by globally synchronizing the pipeline flushing, redirecting the program counter to the original macro instruction address corresponding to the oldest microinstruction for re-execution, and avoiding the abnormal mode with an initialized execution state, thus restoring normal core operation.

[0063] When the redirection mode is triggered, the hardware module completes the unlocking operation in the following order: First, the livelock detection unit sends a high-level active sync flush signal (SyncFlushSignal) to the reordering unit through its internal hardware signal drive circuit. This signal continues until the global flush is complete, ensuring that the reordering unit stably executes the flushing action. Upon receiving the sync flush signal, the reordering unit immediately initiates the global synchronous refresh hardware logic, sending flush instructions to all pipeline stages (fetch, decode, issue, execute, write-back) within the processor via a dedicated control bus. This clears all uncommitted microinstructions and related status information in the pipeline, including microinstructions to be executed in the issue queue of the execution unit, temporary cache data in the decoding unit, and unconfirmed mapping relationships in the register renaming table. Simultaneously, the state of each hardware unit is reset to the initial ready state. After completing the global synchronization flush, the reordering unit extracts the address of the original macro instruction corresponding to the oldest uncommitted microinstruction stored in its internal address resolution module. Through the program counter (PC) redirection hardware circuit, it forcibly updates the processor's program counter pointer to this original macro instruction address, achieving precise redirection of the instruction execution entry point. After program counter redirection, a hardware reset signal triggers the processor to start a new round of instruction execution, starting from the redirected original macro instruction address and sequentially performing fetch, decode, issue, and execute operations. During this process, priority is given to allocating execution resources for the microinstruction corresponding to the original macro instruction. If, after redirection, the original macro instruction corresponding to the oldest microinstruction successfully completes the fetch, decode, and execute process, the execution unit sends an execution completion signal to the reordering unit via the result feedback bus. Upon receiving the signal, the reordering unit immediately triggers the commit process for that microinstruction. After committing, it resets the timer via a dedicated control signal, clearing the count value to zero, and the unlocking process ends normally. If, due to underlying hardware failure, abnormal redirection address, or other reasons, the original macro instruction fetch fails or execution is still unsuccessful, the reordering unit sends a failure level signal to the livelock detection unit. Upon receiving the signal, the livelock detection unit immediately stops outputting the synchronous flushing signal, disables the redirection-related hardware logic, and ends the current redirection mode. The system will continue to maintain a stagnant monitoring state, waiting for the timer to trigger other unlocking modes, or triggering a subsequent alarm mechanism when all unlocking modes have failed and the stagnant time reaches the fatal error alarm limit.

[0064] This redirection mode is highly effective in resolving two typical livelock scenarios: first, persistent stalls caused by encountering specific exception patterns during core execution. Global flushing clears the exception instruction state, essentially "initializing" the instruction execution flow, significantly reducing the probability of encountering the same exception pattern again; second, hangs caused by timing-related extreme scenarios. During re-execution, the timing state can be reset to avoid original timing conflicts, thus unlocking the program. Furthermore, both the global flush and redirection operations are executed in parallel via hardware circuitry, resulting in fast response times and rapid interruption of loop stalls. After redirection, only the original macro instruction corresponding to the oldest microinstruction and subsequent instructions are re-executed, without affecting the execution results of already submitted instructions, ensuring program consistency. After unlocking, the processor automatically resumes normal execution logic, preventing long-term performance degradation of the core's normal operation.

[0065] In S4, during the hardware interaction process in redirection mode, when the reordering unit detects a new microinstruction submission, it determines that the unlocking operation is successful and immediately sends a single-clock-cycle pulse reset signal to the timer via the internal hardware control circuit. Upon receiving this pulse signal, the timer immediately triggers the internal counter clearing logic, resetting the timing value to its initial state. This confirms that the unlocking process has ended normally and restores the ability to monitor subsequent instruction execution pauses.

[0066] In S5, refer to Figure 9 The flowchart illustrating the method for obtaining the maximum upper limit shows the following steps: S51: During the testing phase, evaluate the processor's hardware fault tolerance limits and system recovery costs under different post-silicon hang-up scenarios; S52: Based on hardware fault tolerance limits and system recovery costs, set the threshold encoding range for the fatal error alarm mechanism; S53: Test the fatal error alarm mechanism under different threshold codes within the corresponding threshold coding range, and measure the interception rate of extreme unrecoverable hang-up scenarios and the false interception rate of unlockable and recoverable scenarios in the silicon hang-up scenario library. S54: Based on the interception rate and false interception rate, determine the optimal threshold code from the threshold coding range of the fatal error alarm mechanism; S55: Optimal threshold encoding based on the fatal error alarm mechanism to obtain the initial maximum upper limit.

[0067] In S51-S55, the hardware fault tolerance limit refers to the longest pause time that each unlocking mode can successfully recover in all unlockable deadlock scenarios. If the pause time exceeds this value, the unlocking mode will fail to recover. During evaluation, the testing team built a full hardware test platform including unlock configuration registers and timers, imported a post-silicon deadlock scenario library covering four typical livelock scenarios, gradually applied pressure to each scenario, recorded the unlocking response under different pause times, and took the longest effective unlocking time of all unlockable scenarios as the hardware fault tolerance limit. System recovery cost refers to the quantified value of performance loss, increased power consumption, and service interruption risk caused by the unlocking process. During evaluation, power consumption and performance loss data during the unlocking process were collected using a power meter and performance counter. Combined with the clock cycle proportion of the unlocking process, the recovery cost under different scenarios was calculated to determine the longest pause time corresponding to the maximum acceptable recovery cost of the system.

[0068] Using hardware fault tolerance limits as the upper limit benchmark, ensure that the maximum value of the threshold coding range is not less than the longest effective unlocking time for all unlockable scenarios to avoid premature alarm triggering; using system recovery cost as a constraint, exclude codes corresponding to excessively long stagnation times that exceed reasonable recovery costs to prevent invalid waiting. For example, if the longest effective unlocking time in hardware corresponds to a count value of 40 under the global time base (1ms), and the maximum acceptable recovery cost of the system corresponds to 60ms, then the threshold coding range is set to 32~63 (corresponding to a duration of 32ms~63ms), which both reserves sufficient unlocking attempt time and controls recovery costs.

[0069] Keeping the test platform configuration unchanged and the global time base fixed, the threshold encoding is set to each value within the range in turn. Extreme unrecoverable hangup scenarios and unlockable recovery scenarios in the scenario library are triggered in a loop. The alarm triggering situation is recorded. The interception rate of extreme unrecoverable scenarios (number of scenarios that trigger alarms / total number of extreme scenarios) and the false interception rate of unlockable scenarios (number of unlockable scenarios that falsely trigger alarms / total number of unlockable scenarios) under each encoding value are calculated to form a three-dimensional test data table. The error is reduced by repeated testing.

[0070] A weighted scoring method is adopted, with the weights of interception rate and false interception rate set according to application requirements (e.g., interception rate weight 0.6, false interception rate weight 0.4 when security is prioritized). A comprehensive score is calculated for each encoding value (comprehensive score = interception rate × weight + (1 - false interception rate) × weight). The encoding with the highest comprehensive score is selected as the optimal threshold encoding. If the scores are the same, the encoding with the shorter corresponding duration is preferred to reduce recovery costs. Finally, a hardware multiplier is used to calculate the maximum upper limit, which is equal to the product of the optimal threshold number of the fatal error alarm mechanism and the global time base.

[0071] Reference Figure 10The flowchart illustrates the method for dynamically updating the maximum upper limit. The method includes the following steps: S56: During the application phase, the duration of unresolved stall events that cannot be recovered after all unlocking modes are triggered is statistically analyzed, as well as the effective interception rate of system reset and business interruption loss after the fatal error alarm mechanism is triggered. S57: Dynamically update the optimal threshold code for the fatal error alarm mechanism based on the duration of unresolved stall events, effective interception rate, and business interruption losses; S58: Update the maximum upper limit based on the optimal threshold code updated by the fatal error alarm mechanism.

[0072] In S57-S58, a hardware event monitoring module and a log recording unit are embedded in the business systems where the processor is actually deployed. These modules track two core types of data in real time: first, unresolved stall events that cannot be recovered after all unlocking modes have been triggered, accurately calculating their actual duration and archiving them by type of hang; second, the operational status after the fatal error alarm mechanism is triggered, calculating the effective interception rate (number of successfully intercepted unrecoverable hangs / total number of alarms), and quantifying the business interruption losses caused by each alarm reset (such as transaction failures, service latency, etc.) in conjunction with business logs. Data collection is batch exported and backed up at fixed intervals (e.g., weekly) to ensure data timeliness and integrity.

[0073] The optimal threshold code is dynamically updated based on statistical data. If the majority of unresolved stagnation times are lower than the current maximum limit, it indicates threshold redundancy, and the code value can be lowered to shorten the invalid waiting time. If the unlocking mode fails to complete the attempt due to premature alarm triggering, the code value is increased to allow more time for unlocking. Simultaneously, the threshold is adjusted based on the effective interception rate and business interruption loss. When the effective interception rate is lower than the preset target, security is prioritized, and the threshold is appropriately relaxed. When business interruption loss is too high, the threshold is prioritized to reduce unnecessary alarms. Using the weighted scoring method from the testing phase, the unresolved stagnation time coverage, effective interception rate, and business interruption loss optimization rate are incorporated into the scoring indicators. The comprehensive score of each code value is recalculated, a new optimal threshold code is selected, and then a new maximum limit is calculated.

[0074] To further support the fatal error alarm mechanism, the bits in the threshold encoding selection field can also be used to select the optimal threshold code within the threshold encoding range of the fatal error alarm mechanism. Specifically, the threshold encoding selection field needs to be divided into bits of corresponding width to represent the threshold encoding range of the fatal error alarm mechanism. The optimal threshold code is converted into a binary value, and this value is used to configure the combination of values ​​for this bit range to complete the selection of the optimal threshold code. The timer module extends a dedicated counting channel to synchronously read the global time base in the unlock configuration register and the optimal threshold code of the fatal error alarm mechanism. The maximum upper limit for alarm triggering is calculated through a hardware multiplier, and the stagnation duration is compared with this maximum upper limit through an independent comparator. When the comparison result shows that the stagnation duration exceeds the maximum upper limit, the timer outputs a dedicated alarm event signal (high-level pulse signal) to the livelock detection unit. After receiving the signal, the livelock detection unit triggers the fatal error alarm hardware module, sends a non-maskable interrupt (NMI) to the processor core through the interrupt controller, drives the alarm indicator hardware circuit to light up, and writes the alarm log to the on-chip non-volatile memory unit to achieve rapid response and fault tracing of fatal errors.

[0075] In summary, this patent abandons the limitations of traditional module-level unlocking schemes and innovatively proposes four global unlocking modes and a hybrid usage strategy to solve the problem of uncertain deadlocks. By reusing watchdog timers or other counters to monitor the livelock status, and relying on layered unlocking logic such as forced execution of the oldest microinstruction, order-preserving exclusive resource execution, stopping speculative operations, and global flush redirection, it not only achieves targeted solutions for typical scenarios such as instruction hang-ups in the issue queue and module resource contention, but also supports flexible adaptation to equivalent implementation methods such as matching the oldest instruction in the execution unit. It has strong versatility and compatibility, and significantly improves the stability and fault tolerance of the processor after silicon operation.

[0076] Reference Figure 11 The present disclosure provides a processor, the processor 1 including a reordering unit 11, a timer 12 and a livelock detection unit 13; The reordering unit 11 is used to send a high-level counting enable signal to the timer 12 when it is not empty; Timer 12 is used to record the duration of the pause in the execution of microinstructions inside the processor when a high-level count enable signal is received. The livelock detection unit 13 is used to trigger the corresponding unlocking mode to perform the unlocking operation when the duration is greater than the exclusive threshold of any unlocking mode but less than the maximum limit. The reordering unit 11 is also used to determine that the unlocking is successful when a new microinstruction is submitted, and to send a pulse signal to the timer 12. Timer 12 is also used to reset when a pulse signal is received; The livelock detection unit 13 is also used to trigger a fatal error alarm when the duration is greater than or equal to the maximum limit.

[0077] Furthermore, the processor also includes unlocking configuration register 14; Unlock configuration register 14 to store the global time base, the optimal threshold code for each unlock mode and fatal error alarm mechanism; Timer 12 is used to read the global time base, the optimal threshold code for each unlock mode, and the fatal error alarm mechanism from the unlock configuration register 14; Based on the optimal threshold encoding of the global time base, each unlocking mode, and the fatal error alarm mechanism, obtain the exclusive threshold and maximum limit for each unlocking mode; The duration is compared in parallel with the specific threshold and maximum limit for each unlock mode; Based on the comparison results, generate and output the corresponding event signals; The livelock detection unit 13 is used to determine and execute the triggered unlocking mode or fatal error alarm mechanism based on the received event signal.

[0078] Furthermore, the processor also includes an instruction fetch unit 15, a decoding unit 16, a renaming unit 17, and an execution unit 18. The execution unit 18 includes a fixed-point execution unit, a floating-point execution unit, and a memory access execution unit. The instruction fetch unit 15 fetches instruction codes from memory, and the decoding unit 16 breaks down the instruction codes into microinstructions and issues them to the renaming unit 17. After receiving the microinstructions, the renaming unit 17 queries the renaming mapping table to map the architecture registers in the microinstructions to physical registers, and simultaneously allocates new physical registers for the target architecture registers, thereby eliminating inter-instruction errors. The pseudo-dependency improves the out-of-order execution efficiency of the execution unit; after the register renaming is completed, the renaming unit 17 forwards the microinstruction to the reordering unit 11; after receiving the microinstruction, the reordering unit 11 distributes it to the corresponding fixed-point, floating-point or memory access execution unit according to the microinstruction type, and records the instruction information in the reordering unit 11; each execution unit performs out-of-order execution of the microinstruction, and after the execution is completed, it feeds back the result information to the reordering unit 11, which strictly submits the execution result to the architecture register or memory in the original order of the instructions.

[0079] When a certain unlocking mode is triggered, the livelock detection unit 13 sends a signal to the corresponding execution unit 18, decoding unit 16, or reordering unit 11. Using this signal as a trigger, the corresponding unit begins the unlocking operation. For example, the livelock detection unit 13 sends a pulse-type forced ready signal to all execution units 18 of the microinstruction, causing these execution units 18 to begin the unlocking operation of the forced oldest microinstruction execution mode; the livelock detection unit 13 sends a level-type sequential execution signal to all execution units 18 and decoding unit 16 of the microinstruction, causing these execution units 18 and decoding unit 16 to begin the unlocking operation of the order-preserving execution mode; the livelock detection unit 13 sends a level-type no-speculation optimization signal to the microinstruction decoding unit 16, causing the decoding unit 16 to begin the unlocking operation of the stop-speculation mode; the livelock detection unit 13 sends a synchronization flush signal to the reordering unit 11, causing the reordering unit 11 to begin the unlocking operation of the redirection mode.

[0080] The various variations and specific examples of the processor global multi-mode unlocking method provided above are also applicable to the processor provided in this disclosure. Through the foregoing detailed description of the processor global multi-mode unlocking method, those skilled in the art can clearly understand the implementation method of the processor. For the sake of brevity, they will not be described in detail here.

[0081] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0082] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the processor global multi-mode unlocking method described in the foregoing embodiments of this disclosure.

[0083] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0084] like Figure 12This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 12 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0085] like Figure 12 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0086] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 12 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0087] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the processor-global multi-mode unlocking method of embodiments of this disclosure are performed.

[0088] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0089] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the processor global multi-mode unlocking method described in the foregoing embodiments of the present disclosure are performed.

[0090] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0091] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0092] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0093] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0094] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0095] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0096] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0097] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0098] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A processor global multi-mode unlocking method, characterized in that, include: Set a timer to record the duration of the processor's internal microinstruction execution pause when the reordering unit is not empty; Set multiple unlock modes and a unique threshold for each unlock mode; When the duration is greater than the exclusive threshold of any unlock mode but less than the maximum limit, the corresponding unlock mode is triggered to perform the unlock operation; When a new microinstruction is submitted, the unlock is determined to be successful, and the timer is reset; A fatal error alarm is triggered when the duration is greater than or equal to the maximum limit.

2. The processor global multi-mode unlocking method according to claim 1, characterized in that, The unlocking mode includes at least one of the following: forced oldest microinstruction execution mode, order-preserving execution mode, stop speculation mode, and redirection mode.

3. The processor global multi-mode unlocking method according to claim 2, characterized in that, The settings include multiple unlock modes and a specific threshold for each unlock mode, including: During the testing phase, the unlocking cost level and resolution capability boundary of each unlocking mode are evaluated, and a threshold encoding range for each unlocking mode is set based on the unlocking cost level and the resolution capability boundary. Construct a silicon-back-hanging scenario library and test the resolution rate and false trigger rate of each unlocking mode for all scenarios in the silicon-back-hanging scenario library under different threshold codes within the corresponding threshold coding range. Based on the resolution rate and false trigger rate, the optimal threshold code is determined from the threshold code range of each unlocking mode; Based on the optimal threshold encoding for each unlocking mode, obtain the initial exclusive threshold for each unlocking mode.

4. The processor global multi-mode unlocking method according to claim 3, characterized in that, The setting of multiple unlocking modes and a specific threshold for each unlocking mode further includes: During the application phase, after triggering any unlocking mode to perform an unlocking operation, the optimal threshold code of the unlocking mode is dynamically updated based on the unlocking result. Based on the optimal threshold encoding after the unlock mode update, update the exclusive threshold of the unlock mode.

5. The processor global multi-mode unlocking method according to claim 4, characterized in that, Also includes: During the testing phase, the hardware fault tolerance limits and system recovery costs of the processor under different post-silicon hang-up scenarios were evaluated. Based on the hardware fault tolerance limit and the system recovery cost, a threshold encoding range for the fatal error alarm mechanism is set. The fatal error alarm mechanism was tested under different threshold encodings within the corresponding threshold encoding range to measure the interception rate of extreme unrecoverable hang-up scenarios and the false interception rate of unlockable and recoverable scenarios in the silicon hang-up scenario library. Based on the interception rate and the false interception rate, the optimal threshold code is determined from the threshold coding range of the fatal error alarm mechanism; Based on the optimal threshold encoding of the aforementioned fatal error alarm mechanism, the initial maximum upper limit is obtained.

6. The processor global multi-mode unlocking method according to claim 5, characterized in that, Also includes: During the application phase, the duration of unresolved stall events that could not be recovered after all unlocking modes were triggered was statistically analyzed, as well as the effective interception rate of system reset and business interruption loss after the fatal error alarm mechanism was triggered. Based on the duration of the unresolved stall event, the effective interception rate, and the service interruption loss, the optimal threshold code of the fatal error alarm mechanism is dynamically updated; The maximum upper limit is updated based on the optimal threshold encoding updated by the aforementioned fatal error alarm mechanism.

7. The processor global multi-mode unlocking method according to claim 6, characterized in that, The specific threshold of the unlocking mode is equal to the product between the optimal threshold code of the unlocking mode and the global time base; The maximum upper limit is equal to the product of the optimal threshold number of the fatal error alarm mechanism and the global time base.

8. The processor global multi-mode unlocking method according to claim 7, characterized in that, Also includes: Configure each bit field of the unlock configuration register based on the functional control requirements of each unlock mode; The bit field includes an enable control field, a global time base selection field, a mode combination control field, and a threshold coding selection field. Each bit in the enable control field is an enable bit for an unlock mode, used to enable or disable the corresponding unlock mode; The global time base selection field occupies independent bits and is used to dynamically switch the global time base; Each bit in the mode combination control field corresponds to a combination unlocking mode, which is used to authorize the mixed use of two unlocking modes; The bits in the threshold encoding selection field are used to select the optimal threshold encoding within the threshold encoding range for each unlocking mode and the fatal error alarm mechanism.

9. The processor global multi-mode unlocking method according to claim 2, characterized in that, Also includes: When the triggered unlock mode is the forced oldest microinstruction execution mode, a pulse-type forced ready signal is sent to all execution units of the microinstruction; When each execution unit receives the forced ready signal, it searches and locates the entry in its internal launch queue that corresponds to the oldest uncommitted microinstruction in the reordering unit. The oldest microinstruction located is ignored if it was originally in a ready state, and is forced to be executed once in the execution pipeline; When the forced execution is successful, the oldest microinstruction completes execution and sends a completion signal to the reordering unit. After the reordering unit submits, the timer is reset. If forced execution fails, the forced oldest microinstruction execution mode is terminated, and the system waits for other unlocking modes or triggers a fatal error alarm.

10. The processor global multi-mode unlocking method according to claim 2, characterized in that, Also includes: When the unlocking mode is the order-preserving execution mode, a level-based order-preserving execution signal is sent to all execution units and decoding units of the microinstruction. When the decoding unit receives the in-order execution signal, it performs microinstruction rate limiting; Upon receiving the in-order execution signal, each execution unit ceases to execute out-of-order scheduling. When the microinstruction already issued to the execution unit is the oldest uncommitted microinstruction in the reordering unit, the processor resources are temporarily transferred to the oldest microinstruction and an attempt is made to commit it. When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the order-preserving execution mode ends, and the system waits for another unlocking mode or triggers a fatal error alarm.

11. The processor global multi-mode unlocking method according to claim 2, characterized in that, Also includes: When the triggered unlocking mode is the stop-speculation mode, a level-based no-speculation optimization signal is sent to the microinstruction decoding unit; When the decoding unit receives a no-speculation-optimization signal, it disables the speculative optimization function and attempts to submit the oldest microinstruction in the reordering unit. When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the Stop Speculation mode ends and waits for another unlock mode or triggers a fatal error alarm.

12. The processor global multi-mode unlocking method according to claim 2, characterized in that, Also includes: When the triggered unlocking mode is the redirection mode, a synchronization flushing signal is sent to the reordering unit; When the reordering unit receives the synchronization flush signal, it performs a global synchronization refresh, clearing all unsubmitted micro-instructions in the pipeline. The processor's program counter is redirected to the original macro instruction address corresponding to the oldest microinstruction in the reordering unit; Starting from the original macro instruction address after redirection, the processor re-fetches, decodes, issues, and executes the instruction; When the oldest microinstruction is successfully submitted, a completion signal is sent to the reordering unit, and the timer is reset after the reordering unit submits. If the attempt fails, the redirection mode ends and waits for another unlock mode or triggers a fatal error alarm.

13. A processor, characterized in that, The processor includes a reordering unit, a timer, and a livelock detection unit; The reordering unit is used to send a high-level counting enable signal to the timer when it is not empty; The timer is used to record the duration of the pause in the execution of microinstructions inside the processor when the high-level counting enable signal is received. The livelock detection unit is used to trigger the corresponding unlocking mode to perform an unlocking operation when the duration is greater than the exclusive threshold of any unlocking mode and less than the maximum upper limit. The reordering unit is also used to determine that unlocking is successful when a new microinstruction is submitted, and to send a pulse signal to the timer. The timer is also used to reset upon receiving the pulse signal; The livelock detection unit is also used to trigger a fatal error alarm when the duration is greater than or equal to the maximum upper limit.

14. The processor according to claim 13, characterized in that, The processor also includes an unlock configuration register; The unlock configuration register is used to store the global time base, the optimal threshold code for each unlock mode and the fatal error alarm mechanism; The timer is used to read the global time base, the optimal threshold code for each unlock mode, and the fatal error alarm mechanism from the unlock configuration register; Based on the global time base, the optimal threshold encoding for each unlocking mode and the fatal error alarm mechanism, obtain the specific threshold and the maximum upper limit for each unlocking mode; The duration is compared in parallel with the specific threshold for each unlocking mode and the maximum upper limit; Based on the comparison results, generate and output the corresponding event signals; The livelock detection unit is used to determine and execute the triggered unlocking mode or fatal error alarm mechanism based on the received event signal.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the processor global multimode unlocking method according to any one of claims 1-12.

16. A computer program product comprising computer instructions, characterized in that, When executed by the processor, the computer instructions implement the steps of the processor global multi-mode unlocking method according to any one of claims 1-12.

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