Test structures and methods of forming the same

Abstract

A test structure and a method for forming the same, wherein the structure comprises: a plurality of first electrode layers on a second region, the plurality of first electrode layers are electrically connected with a first lead, each first electrode layer comprises a plurality of first metal lines and a plurality of second metal lines connected with each other, the first metal lines are parallel to a first direction, the second metal lines are parallel to a second direction, and one second metal line is connected with one first metal line at both ends; and a plurality of second electrode layers on the second region, the plurality of second electrode layers and the plurality of first electrode layers are separated from each other, each second electrode layer comprises a plurality of third metal lines and a plurality of fourth metal lines connected with each other, the third metal lines are parallel to the first direction, the fourth metal lines are parallel to the second direction, and one fourth metal line is connected with one third metal line at both ends, so that the time-dependent breakdown performance of the dielectric layer in the first direction and the second direction can be monitored simultaneously.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a test structure and its formation method. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, integrated circuit chips are developing towards higher device density and higher integration.

[0003] As the size of Ultra Large Scale Integrated Circuit (ULSI) chips continues to shrink, the size of the gate dielectric layer in MOS semiconductor devices is also constantly shrinking to achieve higher performance. When a constant voltage is applied to the device, causing it to accumulate charge, the dielectric layer will break down after a period of time, especially the inter-metal dielectric (IMD) layer. The time elapsed during this breakdown is called the lifetime under that condition, also known as time-dependent dielectric breakdown (TDDB). In the back-end of line (BEOL) process, TDDB performance is one of the key factors in evaluating the stability of the inter-metal dielectric layer and the semiconductor device. To improve device reliability, TDDB performance needs to be considered and tested in the back-end of line process.

[0004] However, the existing test structures for the breakdown performance of metallic dielectric layers over time need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a test structure and a method for forming the same, so as to improve the accuracy of testing.

[0006] To solve the above technical problems, the present invention provides a test structure, comprising: a substrate, the substrate including a first region, a second region, and a third region arranged along a first direction and mutually independent, the second region being located between the first region and the third region; a first lead-out terminal located on the first region; and a plurality of first electrode layers located on the second region, the plurality of first electrode layers being electrically connected to the first lead-out terminal, each first electrode layer including a plurality of first metal lines and a plurality of second metal lines interconnected, the first metal lines being parallel to the first direction, the second metal lines being parallel to a second direction, the first direction and the second direction being parallel to the substrate surface and perpendicular to each other, and a first... Two metal wires are connected at both ends to a first metal wire; a plurality of second electrode layers are located on the second region, the plurality of second electrode layers and the plurality of first electrode layers are mutually independent, each second electrode layer includes a plurality of third metal wires and a plurality of fourth metal wires connected to each other, the third metal wires are parallel to a first direction, the fourth metal wires are parallel to a second direction, a fourth metal wire is connected at both ends to a third metal wire, the second metal wires and the fourth metal wires are arranged at intervals along the first direction, the first metal wires and the third metal wires are arranged at intervals along the second direction; a second lead is located on the third region, the second lead is electrically connected to the plurality of second electrode layers.

[0007] Optionally, the test structure further includes: a first dielectric layer located on the surface of the substrate, and a plurality of first electrode layers and a plurality of second electrode layers located within the first dielectric layer.

[0008] Optionally, the test structure further includes: a plurality of third electrode layers located on the second region, wherein the plurality of third electrode layers are located on different layers from the plurality of first electrode layers, and the third electrode layers correspond one-to-one with the first electrode layers; each third electrode layer includes a plurality of fifth metal lines and a plurality of sixth metal lines interconnected with each other; the fifth metal lines are parallel to the first direction, the sixth metal lines are parallel to the second direction, and each of the sixth metal lines is connected at both ends to a fifth metal line; the first electrode layer has a first projection on the substrate surface, and the third electrode layer has a third projection on the substrate surface, wherein the first projection and the third projection at least partially overlap; and a plurality of first conductive plugs located between the third electrode layer and the corresponding first electrode layer to electrically connect the third electrode layer to the corresponding first electrode layer.

[0009] Optionally, a plurality of first conductive plugs located between the fifth metal wire and the first metal wire are arranged along the first direction; a plurality of first conductive plugs located between the sixth metal wire and the second metal wire are arranged along the second direction.

[0010] Optionally, the third electrode layer is located on the first electrode layer; the test structure further includes: a second dielectric layer located on the surface of a plurality of first electrode layers, a plurality of second electrode layers and a first dielectric layer, and a plurality of first conductive plugs and a plurality of third electrode layers located within the second dielectric layer.

[0011] Optionally, the first electrode layer is located on the third electrode layer; a plurality of the first conductive plugs are located within the first dielectric layer; the test structure further includes: a second dielectric layer located between the substrate surface and the first dielectric layer, and a plurality of the third electrode layers are located within the second dielectric layer.

[0012] Optionally, the test structure further includes: a plurality of fourth electrode layers located on the second region, wherein the plurality of fourth electrode layers are discrete from the plurality of third electrode layers and each of the fourth electrode layers corresponds to a second electrode layer; each of the fourth electrode layers includes a plurality of seventh metal lines and a plurality of eighth metal lines interconnected thereto; the seventh metal lines are parallel to the first direction and the eighth metal lines are parallel to the second direction; each of the eighth metal lines is connected at both ends to a seventh metal line; the sixth metal lines and the eighth metal lines are spaced apart along the first direction; the fifth metal lines and the seventh metal lines are spaced apart along the second direction; the fourth electrode layer has a fourth projection on the substrate surface; the second electrode layer has a second projection on the substrate surface; the second projection and the fourth projection at least partially overlap; and a plurality of second conductive plugs located between the fourth electrode layer and the corresponding second electrode layer to electrically connect the fourth electrode layer to the corresponding second electrode layer.

[0013] Optionally, the first conductive plug and the second conductive plug are arranged at intervals in the first direction or at intervals in the second direction; there is a first spacing between adjacent first electrode layers and second electrode layers, and a second spacing between adjacent first conductive plugs and second conductive plugs, the second spacing being greater than the first spacing; there is a third spacing between two adjacent first conductive plugs, and a fourth spacing between two adjacent second conductive plugs, the third spacing being greater than the second spacing, and the fourth spacing being greater than the second spacing.

[0014] Optionally, a plurality of second conductive plugs located between the seventh metal wire and the third metal wire are arranged along the first direction; a plurality of second conductive plugs located between the eighth metal wire and the fourth metal wire are arranged along the second direction.

[0015] Optionally, the test structure is a zigzag interdigitated structure, wherein the first electrode layer has a first line end and a second line end opposite to each other in the first direction, and the second electrode layer has a third line end and a fourth line end opposite to each other in the first direction; the first lead-out end, the second lead-out end, the first electrode layer, and the second electrode layer are located in the same layer; the substrate further includes a first lead-out region and a second lead-out region, wherein the first lead-out region is located between the first region and the second region, and the second lead-out region is located between the second region and the third region; the first line end further extends to the first lead-out region to be electrically connected to the first lead-out end, and the third line end further extends to the second lead-out region to be electrically connected to the second lead-out end.

[0016] Optionally, in each of the first electrode layers, the number of the first metal lines is greater than or equal to 2, and the number of the second metal lines is greater than or equal to 1; in each of the second electrode layers, the number of the third metal lines is greater than or equal to 2, and the number of the fourth metal lines is greater than or equal to 1.

[0017] Optionally, the test structure is a U-shaped structure, with the first electrode layer and the second electrode layer arranged concentrically around each other. The first electrode layer includes two first metal lines arranged along the second direction and two second metal lines arranged along the first direction. The second electrode layer includes two third metal lines arranged along the second direction and two fourth metal lines arranged along the first direction.

[0018] Optionally, the first lead-out terminal and the first electrode layer are located on different layers; the second lead-out terminal and the second electrode layer are located on different layers; the substrate further includes a first lead-out region and a second lead-out region, the first lead-out region being located between the first region and the second region, and the second lead-out region being located between the second region and the third region; the test structure further includes: a first auxiliary lead-out region located on the first lead-out region and the second region, the first auxiliary lead-out region being connected to the first lead-out terminal; a plurality of third conductive plugs located between the first auxiliary lead-out region and the first electrode layer, so that the first auxiliary lead-out region is electrically connected to each of the first electrode layers; a second auxiliary lead-out region located on the second lead-out region and the second region, the second auxiliary lead-out region being connected to the second lead-out terminal; and a plurality of fourth conductive plugs located between the second auxiliary lead-out region and the second electrode layer, so that the second auxiliary lead-out region is electrically connected to each of the second electrode layers.

[0019] Optionally, the test structure is a spiral zigzag structure, with a first electrode layer and a second electrode layer forming a test unit. Each test unit has a winding center, and the first electrode layer and the second electrode layer are wound around the winding center in the same direction in a spiral zigzag manner. The centers of different test units are different. In each test unit, the first electrode layer has a first end and a second end opposite to each other, the second end is located inside the first electrode layer, and the first end is electrically connected to the first lead-out end. The second electrode layer has a third end and a fourth end opposite to each other, the fourth end is located inside the second electrode layer, and the third end is electrically connected to the second lead-out end.

[0020] Optionally, the number of test units is greater than or equal to one; a plurality of test units are arranged in an array along the first direction, and along the second direction, two adjacent test units are mirror images of each other.

[0021] Optionally, the substrate further includes a first lead-out region and a second lead-out region, the first lead-out region being located between the first region and the second region, and the second lead-out region being located between the second region and the third region; the test structure further includes: a plurality of first auxiliary lead-out regions located on the first lead-out region and the second region, the plurality of first auxiliary lead-out regions being parallel to the first direction and electrically connected to the first lead-out terminal; a plurality of second auxiliary lead-out regions located on the second lead-out region and the second region, the plurality of second auxiliary lead-out regions being parallel to the first direction and electrically connected to the second lead-out terminal, and the first auxiliary lead-out regions and the second auxiliary lead-out regions being arranged at intervals along the second direction; each test structure is located between a first auxiliary lead-out region and a second auxiliary lead-out region, and the first electrode layer of the test structure is electrically connected to the first auxiliary lead-out region, and the second electrode layer of the test structure is electrically connected to the second auxiliary lead-out region.

[0022] Optionally, the number of first electrode layers is greater than or equal to 1; the number of second electrode layers is greater than or equal to 1; in each first electrode layer, the number of first metal lines is greater than or equal to 1, and the number of second metal lines is greater than or equal to 1; in each second electrode layer, the number of third metal lines is greater than or equal to 1, and the number of fourth metal lines is greater than or equal to 1.

[0023] Accordingly, the technical solution of the present invention also provides a method for forming a test structure, comprising: providing a substrate, the substrate comprising a first region, a second region, and a third region arranged along a first direction and mutually separate, the second region being located between the first region and the third region; forming a first lead-out terminal on the first region; forming a plurality of first electrode layers on the second region, the plurality of first electrode layers being electrically connected to the first lead-out terminal, each first electrode layer comprising a plurality of first metal lines and a plurality of second metal lines interconnected, the first metal lines being parallel to the first direction, the second metal lines being parallel to a second direction, the first direction and the second direction being parallel to the surface of the substrate and perpendicular to each other, wherein a first... Two metal wires are connected at both ends to a first metal wire; a plurality of second electrode layers are formed on the second region, the plurality of second electrode layers and the plurality of first electrode layers are mutually independent, each second electrode layer includes a plurality of third metal wires and a plurality of fourth metal wires connected to each other, the third metal wires are parallel to a first direction, the fourth metal wires are parallel to a second direction, a fourth metal wire is connected at both ends to a third metal wire, the second metal wires and the fourth metal wires are arranged at intervals along the first direction, and the first metal wires and the third metal wires are arranged at intervals along the second direction; a second lead is formed on the third region, and the second lead is electrically connected to the plurality of second electrode layers.

[0024] Optionally, the method further includes: forming a plurality of third electrode layers on the second region, wherein the plurality of third electrode layers are located on different layers from the plurality of first electrode layers, and the third electrode layers correspond one-to-one with the first electrode layers; each third electrode layer includes a plurality of fifth metal lines and a plurality of sixth metal lines interconnected with each other; the fifth metal lines are parallel to the first direction, the sixth metal lines are parallel to the second direction, and each of the fifth metal lines is connected at both ends to a sixth metal line; the first electrode layer has a first projection on the substrate surface, and the third electrode layer has a third projection on the substrate surface, wherein the first projection and the third projection at least partially overlap; and forming a plurality of first conductive plugs between the third electrode layer and the corresponding first electrode layer to electrically connect the third electrode layer to the corresponding first electrode layer.

[0025] Optionally, the third electrode layer is located on the first electrode layer; the method of forming a plurality of first conductive plugs, the first electrode layer, the second electrode layer and the third electrode layer includes: forming a first dielectric layer on the substrate; forming a plurality of first electrode layers and a plurality of second electrode layers within the first dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer, the plurality of first electrode layers and the plurality of second electrode layers; and forming a plurality of first conductive plugs and a plurality of third electrode layers within the second dielectric layer.

[0026] Optionally, the first electrode layer is located on the third electrode layer; the method of forming a plurality of first conductive plugs, a first electrode layer, a second electrode layer and a third electrode layer includes: forming a second dielectric layer on the substrate; forming the third electrode layer in the second dielectric layer; forming a first dielectric layer on the surface of the second dielectric layer and the plurality of third electrode layers; and forming a plurality of first conductive plugs, a plurality of first electrode layers and a plurality of second electrode layers in the first dielectric layer.

[0027] Optionally, the method further includes: forming a plurality of third electrode layers while simultaneously forming a plurality of fourth electrode layers on the second region, wherein the plurality of fourth electrode layers are discrete from the plurality of third electrode layers and each fourth electrode layer corresponds to a second electrode layer; each fourth electrode layer includes a plurality of seventh metal lines and a plurality of eighth metal lines interconnected with each other; the seventh metal lines are parallel to the first direction and the eighth metal lines are parallel to the second direction; each eighth metal line is connected at both ends to a seventh metal line; the sixth metal lines and the eighth metal lines are spaced apart along the first direction; the fifth metal lines and the seventh metal lines are spaced apart along the second direction; the fourth electrode layer has a fourth projection on the substrate surface; the second electrode layer has a second projection on the substrate surface; the second projection and the fourth projection at least partially overlap; and forming a plurality of second conductive plugs between the fourth electrode layer and the corresponding second electrode layer to electrically connect the fourth electrode layer to the corresponding second electrode layer.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the test structure provided by the present invention, the time-dependent breakdown performance of the dielectric layer between the first electrode layer and the second electrode layer can be tested by applying a voltage between the first lead and the second lead. Since each first electrode layer includes a plurality of interconnected first metal lines and a plurality of interconnected second metal lines, and each second electrode layer includes a plurality of interconnected third metal lines and a plurality of interconnected fourth metal lines, the second metal lines and the fourth metal lines are arranged at intervals along the first direction, and the first metal lines and the third metal lines are arranged at intervals along the second direction, the time-dependent breakdown performance of the dielectric layer in the first direction and the second direction can be monitored simultaneously using the test structure, thereby improving the chip integration and the accuracy of the time-dependent breakdown performance of the dielectric layer.

[0030] Furthermore, the test structure also includes: a plurality of third electrode layers located on the second region, wherein the plurality of third electrode layers and the plurality of first electrode layers are located on different layers, and a plurality of first conductive plugs located between the third electrode layers and the corresponding first electrode layers, so that the third electrode layers are electrically connected to the corresponding first electrode layers. The test structure can measure the time-dependent breakdown performance of the dielectric layer between the conductive plugs (i.e., the plurality of first conductive plugs) and the metal wire (i.e., the second electrode layer).

[0031] Furthermore, the test structure also includes: a plurality of fourth electrode layers located on the second region, and a plurality of second conductive plugs located between the fourth electrode layers and the corresponding second electrode layers, so that the fourth electrode layers are electrically connected to the corresponding second electrode layers. The test structure can also measure the time-dependent breakdown performance of the dielectric layer between the conductive plugs (i.e., a plurality of first conductive plugs) and the conductive plugs (i.e., a plurality of second conductive plugs).

[0032] In the method for forming the test structure provided by the present invention, the time-delay breakdown performance of the dielectric layer between the first electrode layer and the second electrode layer can be tested by applying a voltage between the first lead and the second lead. Since each first electrode layer includes a plurality of interconnected first metal lines and a plurality of interconnected second metal lines, and each second electrode layer includes a plurality of interconnected third metal lines and a plurality of interconnected fourth metal lines, the second metal lines and the fourth metal lines are arranged at intervals along the first direction, and the first metal lines and the third metal lines are arranged at intervals along the second direction, the time-delay breakdown performance of the dielectric layer in the first direction and the second direction can be monitored simultaneously using the test structure, thereby improving the chip integration and the accuracy of the time-delay breakdown performance of the dielectric layer. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a test structure;

[0034] Figure 2 This is a schematic diagram of the test structure according to an embodiment of the present invention;

[0035] Figures 3 to 6 This is a schematic diagram of the test structure according to another embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the test structure according to another embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of the test structure according to another embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the test structure according to another embodiment of the present invention. Detailed Implementation

[0039] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0040] As described in the background section, existing test structures for the time-dependent breakdown performance of metallic dielectric layers need further improvement. A test structure will now be described and analyzed.

[0041] Figure 1 This is a schematic diagram of a test structure.

[0042] Please refer to Figure 1 The test structure includes: a substrate (not shown in the figure), the substrate comprising a first region I, a first gap region g1, a second region II, a second gap region g2, and a third region III arranged along a first direction X, wherein the first region I and the third region III are respectively located on both sides of the second region II, the first gap region g1 is located between the first region I and the second region II, and the second gap region g2 is located between the second region II and the third region III; a first lead terminal 101 located on the first region I; a second lead terminal 102 located on the second region II; and a plurality of first electrodes located on the first gap region g1 and the second region II. Layer 103, a plurality of first electrode layers 103 extending along the first direction and arranged along the second direction, the first direction X and the second direction Y being parallel to the substrate surface and perpendicular to each other, the plurality of first electrode layers 103 being connected to the first lead terminal 101; a plurality of second electrode layers 104 located on the second region II and the second gap region g2, the plurality of second electrode layers 104 extending along the first direction X and arranged along the second direction Y, the plurality of second electrode layers 104 being connected to the second lead terminal 102, each of the second electrode layers 104 on the second region II being located between adjacent first electrode layers 103.

[0043] In the above test structure, the test structure is placed along the first direction X, that is, several first electrode layers 103 and several second electrode layers 104 extend along the first direction X. The breakdown performance of the metal dielectric layer over time is tested by applying a breakdown voltage between the first lead end 101 and the second lead end 102.

[0044] However, due to limitations imposed by the equipment and process during photolithography, the exposure capability of photoresist is only high in a certain direction. Therefore, for metal line patterns of the same design size, different placement orientations on the substrate result in different actual metal line sizes, leading to different breakdown voltages of the dielectric layer between adjacent metal lines. The aforementioned test structure can only be used to monitor the time-dependent breakdown performance of the dielectric layer between metal lines extending along the first direction X (i.e., in the second direction), but cannot monitor the time-dependent breakdown performance of the dielectric layer between metal lines extending along the second direction Y (i.e., in the first direction).

[0045] To address the aforementioned issues, in another embodiment, test structures in different orientations are simultaneously placed on the chip to monitor the time-dependent breakdown performance of the metal dielectric layers in different orientations.

[0046] However, this method wastes chip area and testing resources, hindering cost reduction. Therefore, there is an urgent need for a test structure that can simultaneously monitor the time-dependent breakdown performance of metal dielectric layers in different directions.

[0047] To address the aforementioned issues, this invention provides a test structure and its formation method. By applying a voltage between the first lead and the second lead, the time-dependent breakdown performance of the dielectric layer between the first electrode layer and the second electrode layer can be tested. Since each first electrode layer includes a plurality of interconnected first metal lines and a plurality of interconnected second metal lines, and each second electrode layer includes a plurality of interconnected third metal lines and a plurality of interconnected fourth metal lines, with the second metal lines and the fourth metal lines arranged at intervals along the first direction and the first metal lines and the third metal lines arranged at intervals along the second direction, the test structure can simultaneously monitor the time-dependent breakdown performance of the dielectric layer in both the first and second directions. This facilitates improved chip integration and enhances the accuracy of the time-dependent breakdown performance of the dielectric layer.

[0048] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figure 2 This is a schematic diagram of the test structure according to an embodiment of the present invention.

[0050] Please refer to Figure 2The test structure includes: a substrate 200, comprising a first region I, a second region II, and a third region III arranged along a first direction X and mutually independent, the second region II being located between the first region I and the third region III; a first lead-out terminal 201 located on the first region I; and a plurality of first electrode layers 211 located on the second region II, the plurality of first electrode layers 211 being electrically connected to the first lead-out terminal 201, each of the first electrode layers 211 including a plurality of first metal lines 2111 and a plurality of second metal lines 2112 interconnected, the first metal lines 2111 being parallel to the first direction X, the second metal lines 2112 being parallel to the second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 200 and perpendicular to each other, and each end of a second metal line 2112 being connected to a first metal line 2112. Lines 2111 are connected; a plurality of second electrode layers 212 are located on the second region II, the plurality of second electrode layers 212 and the plurality of first electrode layers 211 are mutually separate, each second electrode layer 212 includes a plurality of third metal lines 2123 and a plurality of fourth metal lines 2124 connected to each other, the third metal lines 2123 are parallel to the first direction X, the fourth metal lines 2124 are parallel to the second direction Y, each of the two ends of a fourth metal line 2124 is connected to a third metal line 2123, the second metal lines 2112 and the fourth metal lines 2124 are arranged at intervals along the first direction X, and the first metal lines 2111 and the third metal lines 2123 are arranged at intervals along the second direction Y; a second lead-out terminal 202 is located on the third region III, the second lead-out terminal 202 is electrically connected to the plurality of second electrode layers 212.

[0051] Here, by applying a voltage between the first lead-out terminal 201 and the second lead-out terminal 202, the time-delay breakdown performance of the dielectric layer between the first electrode layer 211 and the second electrode layer 212 can be tested. Since each first electrode layer 211 includes a plurality of interconnected first metal lines 2111 and a plurality of interconnected second metal lines 2112, and each second electrode layer 212 includes a plurality of interconnected third metal lines 2123 and a plurality of interconnected fourth metal lines 2124, the second metal lines 2112 and the fourth metal lines 2124 are arranged at intervals along the first direction X, and the first metal lines 2111 and the third metal lines 2123 are arranged at intervals along the second direction Y, the time-delay breakdown performance of the dielectric layer in the first direction X and the second direction Y can be monitored simultaneously using the test structure, which is beneficial to improving the chip integration and the accuracy of the time-delay breakdown performance of the dielectric layer.

[0052] Each of the first electrode layers 211 has a first width, each of the second electrode layers 212 has a second width, and there is a first spacing between adjacent first electrode layers 211 and second electrode layers 212.

[0053] In this embodiment, the first width, the second width, and the first spacing are all minimum dimensions specified by predetermined design rules to meet the requirements of a certain voltage (U) range. For example, when U≤2.75V, the first width is 0.05μm, the second width is 0.05μm, and the first spacing is 0.05μm. In other embodiments, the sizes of the first width, the second width, and the first spacing can be set according to actual process requirements or actual measurement needs.

[0054] In this embodiment, the test structure is a zigzag interdigitated structure. The first electrode layer 211 has opposing first line ends 211i and second line ends 211ii in the first direction X. The second electrode layer 212 has opposing third line ends 212iii and fourth line ends 212iv in the first direction X. The first lead-out end 201, the second lead-out end 202, the first electrode layer 211, and the second electrode layer 212 are located in the same layer. In other embodiments, the test structure may also be a U-shaped structure, a spiral zigzag structure, or other shapes.

[0055] In this embodiment, the substrate 200 further includes a first lead-out region g1 and a second lead-out region g2. The first lead-out region g1 is located between the first region I and the second region II, and the second lead-out region g2 is located between the second region II and the third region III.

[0056] In this embodiment, the first lead-out terminal 201, the second lead-out terminal 202, the first electrode layer 211, and the second electrode layer 212 are located in the same layer.

[0057] In this embodiment, the first wire end 211i extends to the first lead-out area g1 to be electrically connected to the first lead-out end 201, and the third wire end 212iii extends to the second lead-out area g2 to be electrically connected to the second lead-out end 202.

[0058] The number of the first electrode layer 211 is greater than or equal to 1; the number of the second electrode layer 212 is greater than or equal to 1.

[0059] In each of the first electrode layers 211, the number of the first metal wires 2111 is greater than or equal to 1, and the number of the second metal wires 2112 is greater than or equal to 1; in each of the second electrode layers 212, the number of the third metal wires 2123 is greater than or equal to 1, and the number of the fourth metal wires 2124 is greater than or equal to 1.

[0060] In this embodiment, in each of the first electrode layers 211, the number of the first metal wires 2111 is greater than or equal to 2, and the number of the second metal wires 2112 is greater than or equal to 1; in each of the second electrode layers 212, the number of the third metal wires 2123 is greater than or equal to 2, and the number of the fourth metal wires 2124 is greater than or equal to 1.

[0061] In this embodiment, the test structure further includes: a first dielectric layer (not shown in the figure) located on the surface of the substrate 200, and a plurality of first electrode layers 211 and a plurality of second electrode layers 212 located within the first dielectric layer.

[0062] Accordingly, one embodiment of the present invention also provides a method for forming the above-described test structure; please refer to [further details]. Figure 2 The system includes: providing a substrate 200, the substrate 200 including a first region I, a second region II, and a third region III arranged along a first direction X and mutually separate, the second region II being located between the first region I and the third region III; forming a first lead-out terminal 201 on the first region I; forming a plurality of first electrode layers 211 on the second region, the plurality of first electrode layers 211 being electrically connected to the first lead-out terminal 201, each first electrode layer 211 including a plurality of first metal lines 2111 and a plurality of second metal lines 2112 interconnected, the first metal lines 2111 being parallel to the first direction X, the second metal lines 2112 being parallel to a second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 200 and perpendicular to each other, and each end of a second metal line 2112 being connected to a first metal line 211. 1. A plurality of second electrode layers 212 are formed on the second region II. The plurality of second electrode layers 212 and the plurality of first electrode layers 211 are mutually separate. Each second electrode layer 212 includes a plurality of third metal lines 2123 and a plurality of fourth metal lines 2124 that are interconnected. The third metal lines 2123 are parallel to the first direction X, and the fourth metal lines 2124 are parallel to the second direction Y. Each end of a fourth metal line 2124 is connected to a third metal line 2123. The second metal lines 2112 and the fourth metal lines 2124 are arranged at intervals along the first direction X, and the first metal lines 2111 and the third metal lines 2123 are arranged at intervals along the second direction Y. A second lead-out terminal 202 is formed on the third region III. The second lead-out terminal 202 is electrically connected to the plurality of second electrode layers 212.

[0063] In this embodiment, the test structure is a zigzag interdigitated structure. The first electrode layer 211 has a first line end 211i and a second line end 211ii in the first direction X. The second electrode layer 212 has a third line end 212iii and a fourth line end 212iv in the first direction X. The first lead-out end 201, the second lead-out end 202, the first electrode layer 211 and the second electrode layer 212 are located in the same layer.

[0064] In this embodiment, the method for forming the first lead-out terminal 201, the second lead-out terminal 202, the first electrode layer 211, and the second electrode layer 212 includes: forming a first dielectric layer (not shown in the figure) on the surface of the substrate 200; and forming the first lead-out terminal 201, the second lead-out terminal 202, the first electrode layer 211, and the second electrode layer 212 within the first dielectric layer.

[0065] It should be noted that the test structure in the above embodiment is used to measure the time-dependent breakdown performance of the dielectric layer between the first electrode layer 211 and the second electrode layer 212 (i.e., between metal wires).

[0066] In another embodiment, the test structure can also measure the time-dependent breakdown performance of the metal wire and conductive plug, and / or the dielectric layer between conductive plugs. Please refer to [reference needed]. Figures 3 to 6 .

[0067] Figures 3 to 6 This is a schematic diagram of the test structure according to another embodiment of the present invention.

[0068] Please refer to Figures 3 to 6 , Figure 3 This is a top view of the test structure. Figure 4 for Figure 3 The top view of the first electrode layer, second electrode layer, first lead-out terminal, and second lead-out terminal is omitted. Figure 5 for Figure 3 A cross-sectional view of the structure along the FF1 direction. Figure 6 for Figure 3A cross-sectional view along the EE1 direction is shown in the diagram. The test structure includes: a substrate 300, comprising a first region I, a second region II, and a third region III arranged along a first direction X and mutually independent, with the second region II located between the first region I and the third region III; a first lead-out terminal 301 located on the first region I; and a plurality of first electrode layers 311 located on the second region II, electrically connected to the first lead-out terminal 301. Each first electrode layer 311 includes a plurality of interconnected first metal lines 3111 and a plurality of second metal lines 3112. The first metal lines 3111 are parallel to the first direction X, and the second metal lines 3112 are parallel to the second direction Y. The first direction X and the second direction Y are parallel to the surface of the substrate 300 and perpendicular to each other. Each second metal line 3112 has two ends... A first metal line 3111 is connected to the second electrode layer 312 located on the second region II. The second electrode layer 312 and the first electrode layer 311 are separate from each other. Each second electrode layer 312 includes a number of third metal lines 3123 and a number of fourth metal lines 3124 connected to each other. The third metal lines 3123 are parallel to the first direction X, and the fourth metal lines 3124 are parallel to the second direction Y. Each end of a fourth metal line 3124 is connected to a third metal line 3123. The second metal lines 3112 and the fourth metal lines 3124 are arranged at intervals along the first direction X, and the first metal lines 3111 and the third metal lines 3123 are arranged at intervals along the second direction Y. A second lead-out terminal 302 is located on the third region III and is electrically connected to the second electrode layer 312.

[0069] The main difference between this embodiment and the previous embodiment is that the test structure also includes the following structure.

[0070] For details, please continue to refer to [the website / information]. Figures 3 to 6The test structure further includes: a plurality of third electrode layers 313 located on the second region II, wherein the plurality of third electrode layers 313 are located on different layers from the plurality of first electrode layers 311, and the third electrode layers 313 correspond one-to-one with the first electrode layers 311. Each third electrode layer 313 includes a plurality of fifth metal lines 3135 and a plurality of sixth metal lines 3136 interconnected with each other. The fifth metal lines 3135 are parallel to the first direction X, and the sixth metal lines 3136 are parallel to the second direction Y. Each of the sixth metal lines 3136 is connected at both ends to a fifth metal line 3135. The first electrode layer 311 has a first projection on the surface of the substrate 300, and the third electrode layer 313 has a third projection on the surface of the substrate 300. The first projection and the third projection at least partially overlap. A plurality of first conductive plugs 331 are located between the third electrode layer 313 and the corresponding first electrode layer 311 to electrically connect the third electrode layer 313 to the corresponding first electrode layer 311.

[0071] Here, several first conductive plugs 331, the first electrode layer 311 and the third electrode layer 313 are all connected to the first lead-out terminal 301, and the second electrode layer 312 is connected to the second lead-out terminal 301. The test structure can measure the time-dependent breakdown performance of the dielectric layer between the conductive plugs (i.e., several first conductive plugs 331) and the metal wire (i.e., the second electrode layer 312).

[0072] In this embodiment, the first projection and the third projection completely overlap. In another embodiment, the first projection and the third projection may partially overlap.

[0073] In this embodiment, a plurality of first conductive plugs 331 located between the fifth metal wire 3135 and the first metal wire 3111 are arranged along the first direction X; a plurality of first conductive plugs 331 located between the sixth metal wire 3136 and the second metal wire 3112 are arranged along the second direction Y.

[0074] In this embodiment, the first electrode layer 311 is located on the third electrode layer 313; a plurality of first conductive plugs 331 are located within the first dielectric layer.

[0075] In this embodiment, the test structure further includes: a second dielectric layer (not shown in the figure) located between the surface of the substrate 300 and the first dielectric layer, and a plurality of the third electrode layers 313 located within the second dielectric layer.

[0076] In another embodiment, the third electrode layer is located on the first electrode layer; the test structure further includes: a second dielectric layer located on the surface of a plurality of first electrode layers, a plurality of second electrode layers and a first dielectric layer, and a plurality of first conductive plugs and a plurality of third electrode layers located within the second dielectric layer.

[0077] In this embodiment, the test structure further includes: a plurality of fourth electrode layers 314 located on the second region II, wherein the plurality of fourth electrode layers 314 are separate from the plurality of third electrode layers 313, and the fourth electrode layers 314 correspond one-to-one with the second electrode layers 312. Each fourth electrode layer 314 includes a plurality of seventh metal lines 3147 and a plurality of eighth metal lines 3148 interconnected with each other. The seventh metal lines 3147 are parallel to the first direction X, and the eighth metal lines 3148 are parallel to the second direction Y. Each eighth metal line 3148 is connected at both ends to a seventh metal line 3147. The sixth metal line 3136 and the eighth metal line 3148 are arranged at intervals along the first direction X, the fifth metal line 3135 and the seventh metal line 3147 are arranged at intervals along the second direction Y, the fourth electrode layer 314 has a fourth projection on the surface of the substrate 300, and the second electrode layer 312 has a second projection on the surface of the substrate 300, the second projection and the fourth projection at least partially overlap; a plurality of second conductive plugs 332 are located between the fourth electrode layer 314 and the corresponding second electrode layer 312 to electrically connect the fourth electrode layer 314 and the corresponding second electrode layer 312.

[0078] Here, a plurality of first conductive plugs 331, the first electrode layer 311 and the third electrode layer 313 are all connected to the first lead-out terminal 301, and a plurality of second conductive plugs 332, the second electrode layer 312 and the fourth electrode layer 314 are all connected to the second lead-out terminal 301. The test structure can also measure the time-dependent breakdown performance of the dielectric layer between the conductive plugs (i.e., the plurality of first conductive plugs 331) and the conductive plugs (i.e., the plurality of second conductive plugs 332).

[0079] In this embodiment, the second projection and the fourth projection completely overlap. In another embodiment, the second projection and the fourth projection may partially overlap.

[0080] In another embodiment, the fourth electrode layers and the second conductive plugs may not be included.

[0081] In this embodiment, a plurality of second conductive plugs 332 are located within the first dielectric layer; a plurality of fourth electrode layers 314 are located within the second dielectric layer. In another embodiment, a plurality of second conductive plugs and a plurality of fourth electrode layers are located within the second dielectric layer.

[0082] In this embodiment, the first conductive plug 331 and the second conductive plug 332 are arranged at intervals in the first direction X, or at intervals in the second direction Y. In another embodiment, this is not a limitation.

[0083] Each of the first electrode layers 311 has a first width, and each of the second electrode layers 312 has a second width; there is a first gap between adjacent first electrode layers 311 and second electrode layers 312, and there is a second gap between adjacent first conductive plugs 331 and second conductive plugs 332, the second gap being greater than the first gap.

[0084] In this embodiment, the first width, the second width, the first spacing, and the second spacing are all minimum dimensions specified by predetermined design rules to meet the requirements of a certain voltage (U) range. For example, when U≤2.75V, the first width is 0.05μm, the second width is 0.05μm, the first spacing is 0.05μm, and the second spacing is 0.08μm. In other embodiments, the sizes of the first width, the second width, the first spacing, and the second spacing can be set according to actual process requirements or actual measurement needs.

[0085] There is a third gap between two adjacent first conductive plugs 331 and a fourth gap between two adjacent second conductive plugs 332.

[0086] In this embodiment, the minimum size required to meet a certain voltage (U) range as specified by predetermined design rules is used as the preset size. Both the third and fourth spacings are not less than the preset size; that is, when U ≤ 2.75V, the third spacing is greater than or equal to 0.1μm, and the fourth spacing is greater than or equal to 0.1μm. In other embodiments, the sizes of the third and fourth spacings can be set according to actual process requirements or actual measurement needs.

[0087] In this embodiment, a plurality of second conductive plugs 332 located between the seventh metal line 3147 and the third metal line 3123 are arranged along the first direction X; a plurality of second conductive plugs 332 located between the eighth metal line 3148 and the fourth metal line 3124 are arranged along the second direction Y.

[0088] In this embodiment, the test structure further includes: a third lead-out terminal 303 located on the first lead-out region I, with a plurality of third electrode layers 313 electrically connected to the third lead-out terminal 303; and a fourth lead-out terminal 304 located on the second lead-out region II, with a plurality of fourth electrode layers 314 electrically connected to the fourth lead-out terminal 304.

[0089] Specifically, the surface of the third lead 303 also has a plurality of fifth conductive plugs 335, and the first lead 301 is located on the surface of the plurality of fifth conductive plugs 335 so that the third lead 303 is electrically connected to the first lead 301; the surface of the fourth lead 304 also has a plurality of sixth conductive plugs 336, and the second lead 302 is located on the surface of the plurality of sixth conductive plugs 336 so that the fourth lead 304 and the second lead 302 are electrically connected.

[0090] Accordingly, one embodiment of the present invention also provides a method for forming the above-described test structure; please refer to [further details]. Figures 3 to 6 The system includes: providing a substrate 300, the substrate 300 including a first region I, a second region II, and a third region III arranged along a first direction X and mutually separate, the second region II being located between the first region I and the third region III; forming a first lead-out terminal 301 on the first region I; forming a plurality of first electrode layers 311 on the second region, the plurality of first electrode layers 311 being electrically connected to the first lead-out terminal 301, each first electrode layer 311 including a plurality of first metal lines 3111 and a plurality of second metal lines 3112 interconnected, the first metal lines 3111 being parallel to the first direction X, the second metal lines 3112 being parallel to a second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 300 and perpendicular to each other, and each end of a second metal line 3112 being connected to a first metal line 311. 1. A plurality of second electrode layers 312 are formed on the second region II. The plurality of second electrode layers 312 and the plurality of first electrode layers 311 are mutually separate. Each second electrode layer 312 includes a plurality of third metal lines 3123 and a plurality of fourth metal lines 3124 that are interconnected. The third metal lines 3123 are parallel to the first direction X, and the fourth metal lines 3124 are parallel to the second direction Y. Each end of a fourth metal line 3124 is connected to a third metal line 3123. The second metal lines 3112 and the fourth metal lines 3124 are arranged at intervals along the first direction X, and the first metal lines 3111 and the third metal lines 3123 are arranged at intervals along the second direction Y. A second lead-out terminal 302 is formed on the third region III. The second lead-out terminal 302 is electrically connected to the plurality of second electrode layers 312.

[0091] In this embodiment, a plurality of third electrode layers 313 are formed on the second region II. The plurality of third electrode layers 313 are located on different layers from the plurality of first electrode layers 311, and the third electrode layers 313 correspond one-to-one with the first electrode layers 311. Each third electrode layer 313 includes a plurality of fifth metal lines 3135 and a plurality of sixth metal lines 3136 that are interconnected. The fifth metal lines 3135 are parallel to the first direction X, and the sixth metal lines 3136 are parallel to the second direction Y. Each of the sixth metal lines 3136 is connected to a fifth metal line 3135 at both ends. The first electrode layer 311 has a first projection on the surface of the substrate 300, and the third electrode layer 313 has a third projection on the surface of the substrate 200. The first projection and the third projection at least partially overlap. A plurality of first conductive plugs 331 are formed between the third electrode layer 313 and the corresponding first electrode layer 311 to make the third electrode layer 313 electrically connected to the corresponding first electrode layer 311.

[0092] In this embodiment, the first electrode layer 311 is located on the third electrode layer 313.

[0093] In this embodiment, the method for forming a plurality of first conductive plugs 331, first electrode layers 311, second electrode layers 312 and third electrode layers 313 includes: forming a second dielectric layer (not shown in the figure) on the substrate 300; forming the third electrode layers 313 within the second dielectric layer; forming a first dielectric layer (not shown in the figure) on the surface of the second dielectric layer and the plurality of third electrode layers 313; and forming a plurality of first conductive plugs 331, a plurality of first electrode layers 311 and a plurality of second electrode layers 312 within the first dielectric layer.

[0094] In another embodiment, the third electrode layer is located on the first electrode layer; the method of forming a plurality of first conductive plugs, the first electrode layer, the second electrode layer and the third electrode layer includes: forming a first dielectric layer on the substrate; forming a plurality of first electrode layers and a plurality of second electrode layers within the first dielectric layer; forming a second dielectric layer on the surface of the plurality of first dielectric layers, the plurality of first electrode layers and the second electrode layers; and forming a plurality of first conductive plugs and a plurality of third electrode layers within the second dielectric layer.

[0095] In this embodiment, the method for forming a plurality of first conductive plugs 331, first electrode layer 311 and second electrode layer 312 in the first dielectric layer includes a damascus process or a double damascus process.

[0096] In this embodiment, while forming a plurality of third electrode layers 313, a plurality of fourth electrode layers 314 are also formed on the second region II. The plurality of fourth electrode layers 314 are separate from the plurality of third electrode layers 313, and the fourth electrode layers 314 correspond one-to-one with the second electrode layers 312. Each fourth electrode layer 314 includes a plurality of seventh metal lines 3147 and a plurality of eighth metal lines 3148 that are interconnected. The seventh metal lines 3147 are parallel to the first direction X, and the eighth metal lines 3148 are parallel to the second direction Y. Each of the eighth metal lines 3148 is connected at both ends to a seventh metal line 3147. The sixth metal line 3136 and the eighth metal line 3148 are arranged at intervals along the first direction X, and the fifth metal line 3135 and the seventh metal line 3147 are arranged at intervals along the second direction Y. The fourth electrode layer 314 has a fourth projection on the surface of the substrate 300, and the second electrode layer 312 has a second projection on the surface of the substrate 300. The second projection and the fourth projection at least partially overlap. A plurality of second conductive plugs 332 are formed between the fourth electrode layer 314 and the corresponding second electrode layer 312 to electrically connect the fourth electrode layer 314 and the corresponding second electrode layer 312.

[0097] In this embodiment, a plurality of second conductive plugs 332 and a plurality of fourth electrode layers 314 are formed within the first dielectric layer.

[0098] In another embodiment, the formation of several fourth electrode layers and several second conductive plugs may be omitted.

[0099] In this embodiment, the second projection and the fourth projection completely overlap. In another embodiment, the second projection and the fourth projection may partially overlap.

[0100] In this embodiment, the first conductive plug 331 and the second conductive plug 332 are arranged at intervals in the first direction X, or at intervals in the second direction Y. In another embodiment, this is not a limitation.

[0101] In this embodiment, a plurality of second conductive plugs 332 located between the seventh metal line 3147 and the third metal line 3123 are arranged along the first direction X; a plurality of second conductive plugs 332 located between the eighth metal line 3148 and the fourth metal line 3124 are arranged along the second direction Y.

[0102] In this embodiment, a third lead-out terminal 303 is also formed in the second dielectric layer on the first lead-out region I, and a plurality of third electrode layers 313 are electrically connected to the third lead-out terminal 303; a fourth lead-out terminal 304 is also formed in the second dielectric layer on the second lead-out region II, and a plurality of fourth electrode layers 314 are electrically connected to the fourth lead-out terminal 304.

[0103] In this embodiment, a plurality of fifth conductive plugs 335 are also formed in the first dielectric layer, and the plurality of fifth conductive plugs 335 are located on the surface of the third lead-out terminal 303, and the first lead-out terminal 301 is located on the surface of the plurality of fifth conductive plugs 335; a plurality of sixth conductive plugs 336 are also formed in the first dielectric layer, and the plurality of sixth conductive plugs 336 are located on the surface of the fourth lead-out terminal 304.

[0104] Figure 7 This is a schematic diagram of the test structure according to another embodiment of the present invention.

[0105] Please refer to Figure 7 The test structure includes: a substrate 400, comprising a first region I, a second region II, and a third region III arranged along a first direction X and mutually independent, the second region II being located between the first region I and the third region III; a first lead-out terminal 401 located on the first region I; and a plurality of first electrode layers 411 located on the second region II, the plurality of first electrode layers 411 being electrically connected to the first lead-out terminal 401, each of the first electrode layers 411 including a plurality of first metal lines 4111 and a plurality of second metal lines 4112 interconnected, the first metal lines 4111 being parallel to the first direction X, the second metal lines 4112 being parallel to the second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 400 and perpendicular to each other, and each end of a second metal line 4112 being connected to a first metal line 4112. Lines 4111 are connected; a plurality of second electrode layers 412 are located on the second region II, the plurality of second electrode layers 412 and the plurality of first electrode layers 411 are mutually separate, each second electrode layer 412 includes a plurality of third metal lines 4123 and a plurality of fourth metal lines 4124 connected to each other, the third metal lines 4123 are parallel to the first direction X, the fourth metal lines 4124 are parallel to the second direction Y, each of the two ends of a fourth metal line 4124 is connected to a third metal line 4123, the second metal lines 4112 and the fourth metal lines 4124 are arranged at intervals along the first direction X, and the first metal lines 4111 and the third metal lines 4123 are arranged at intervals along the second direction Y; a second lead-out terminal 402 is located on the third region III, the second lead-out terminal 402 is electrically connected to the plurality of second electrode layers 412.

[0106] The main difference between this embodiment and the previous embodiment is that the shape of the test structure is different.

[0107] In this embodiment, the test structure is a U-shaped structure, with the first electrode layer 411 and the second electrode layer 412 arranged concentrically. The first electrode layer 411 includes two first metal lines 4111 arranged along the second direction Y and two second metal lines 4112 arranged along the first direction X. The second electrode layer 412 includes two third metal lines 4123 arranged along the second direction Y and two fourth metal lines 4124 arranged along the first direction X.

[0108] In this embodiment, the first lead-out terminal 401 and the first electrode layer 411 are located in different layers; the second lead-out terminal 402 and the second electrode layer 412 are located in different layers;

[0109] In this embodiment, the substrate 400 further includes a first lead-out region g1 and a second lead-out region g2. The first lead-out region g1 is located between the first region I and the second region II, and the second lead-out region g2 is located between the second region II and the third region III.

[0110] In this embodiment, the test structure further includes: a first auxiliary lead-out area 403 located on the first lead-out area g1 and the second area II, the first auxiliary lead-out area 403 being connected to the first lead-out terminal 401; a plurality of third conductive plugs 405 located between the first auxiliary lead-out area 403 and the first electrode layer 411, so that the first auxiliary lead-out area 403 is electrically connected to each of the first electrode layers 411; a second auxiliary lead-out area 404 located on the second lead-out area g2 and the second area II, the second auxiliary lead-out area 404 being connected to the second lead-out terminal 402; and a plurality of fourth conductive plugs 406 located between the second auxiliary lead-out area 404 and the second electrode layer 412, so that the second auxiliary lead-out area 404 is electrically connected to each of the second electrode layers 412.

[0111] Specifically, a plurality of the third conductive plugs 405 are located on the surface of the first electrode layer 411, and the first auxiliary lead-out area 403 is located on the surface of the plurality of the third conductive plugs 405; a plurality of the fourth conductive plugs 406 are located on the surface of the second electrode layer 412, and the second auxiliary lead-out area 404 is located on the surface of the plurality of the fourth conductive plugs 406.

[0112] More specifically, a plurality of the third conductive plugs 405 are located on the surface of each of the second metal wires 4112; and a plurality of the fourth conductive plugs 406 are located on the surface of each of the fourth metal wires 4124.

[0113] In another embodiment, the test structure further includes: a plurality of third electrode layers located on the second region, wherein the plurality of third electrode layers are located on different layers from the plurality of first electrode layers, and the third electrode layers correspond one-to-one with the first electrode layers; each third electrode layer includes a plurality of fifth metal lines and a plurality of sixth metal lines interconnected with each other; the fifth metal lines are parallel to the first direction, the sixth metal lines are parallel to the second direction, and each of the sixth metal lines is connected at both ends to a fifth metal line; the first electrode layer has a first projection on the substrate surface, and the third electrode layer has a third projection on the substrate surface, wherein the first projection and the third projection at least partially overlap; and a plurality of first conductive plugs located between the third electrode layer and the corresponding first electrode layer to electrically connect the third electrode layer to the corresponding first electrode layer.

[0114] In another embodiment, the test structure further includes: a plurality of fourth electrode layers located on the second region, wherein the plurality of fourth electrode layers are discrete from the plurality of third electrode layers and each of the fourth electrode layers corresponds to a second electrode layer; each of the fourth electrode layers includes a plurality of seventh metal lines and a plurality of eighth metal lines interconnected thereto; the seventh metal lines are parallel to the first direction and the eighth metal lines are parallel to the second direction; each of the eighth metal lines is connected at both ends to a seventh metal line; the sixth metal lines and the eighth metal lines are spaced apart along the first direction; the fifth metal lines and the seventh metal lines are spaced apart along the second direction; the fourth electrode layer has a fourth projection on the substrate surface; the second electrode layer has a second projection on the substrate surface; the second projection and the fourth projection at least partially overlap; and a plurality of second conductive plugs located between the fourth electrode layer and the corresponding second electrode layer to electrically connect the fourth electrode layer to the corresponding second electrode layer.

[0115] Accordingly, another embodiment of the present invention also provides a method for forming the above-mentioned test structure, please refer to... Figure 7 Please refer to the previous description for details, which will not be repeated here.

[0116] Figure 8 This is a schematic diagram of the test structure according to another embodiment of the present invention.

[0117] Please refer to Figure 8The test structure includes: a substrate 500, comprising a first region I, a second region II, and a third region III arranged along a first direction X and mutually independent, the second region II being located between the first region I and the third region III; a first lead-out terminal 501 located on the first region I; and a plurality of first electrode layers 511 located on the second region II, the plurality of first electrode layers 511 being electrically connected to the first lead-out terminal 501, each first electrode layer 511 including a plurality of first metal lines 5111 and a plurality of second metal lines 5112 interconnected, the first metal lines 5111 being parallel to the first direction X, the second metal lines 5112 being parallel to the second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 500 and perpendicular to each other, and each end of a second metal line 5112 being connected to a first metal line 5112. Lines 5111 are connected; a plurality of second electrode layers 512 are located on the second region II, the plurality of second electrode layers 512 and the plurality of first electrode layers 511 are mutually separate, each second electrode layer 512 includes a plurality of third metal lines 5123 and a plurality of fourth metal lines 5124 connected to each other, the third metal lines 5123 are parallel to the first direction X, the fourth metal lines 5124 are parallel to the second direction Y, each of the two ends of a fourth metal line 5124 is connected to a third metal line 5123, the second metal lines 5112 and the fourth metal lines 5124 are arranged at intervals along the first direction X, and the first metal lines 5111 and the third metal lines 5123 are arranged at intervals along the second direction Y; a second lead-out terminal 502 is located on the third region III, the second lead-out terminal 502 is electrically connected to the plurality of second electrode layers 512.

[0118] The main difference between this embodiment and the previous embodiment is that the shape of the test structure is different.

[0119] In this embodiment, the test structure is a spiral zigzag structure, with one electrode layer 511 and one second electrode layer 512 forming a test cell. Each test cell has a winding center. The first electrode layer 511 and the second electrode layer 512 are wound around the winding center in the same direction in a spiral zigzag manner. The centers of different test cells are different. In each test cell, the first electrode layer 511 has a first end (not shown in the figure) and a second end, and the second end (not shown in the figure) is located inside the first electrode layer 511. The first end is electrically connected to the first lead-out terminal 501. The second electrode layer 512 has a third end (not shown in the figure) and a fourth end (not shown in the figure), and the fourth end is located inside the second electrode layer 512. The third end is electrically connected to the second lead-out terminal 502.

[0120] The number of test cells is greater than or equal to one. In this embodiment, the number of test cells is one.

[0121] Accordingly, another embodiment of the present invention also provides a method for forming the above-mentioned test structure, please refer to... Figure 8 Please refer to the previous description for details, which will not be repeated here.

[0122] Figure 9 This is a schematic diagram of the test structure according to another embodiment of the present invention.

[0123] The main difference between this embodiment and the previous embodiment is:

[0124] In this embodiment, the number of test units in the test structure is greater than one.

[0125] In contrast to the case with only a single test unit, the test structure uses several test units to control the length of a single metal wire (the first electrode layer 511 and the second electrode layer 512), thereby controlling the voltage drop caused by the resistance when the metal wire is too long, which helps to improve the detection capability of the test structure.

[0126] Please Figure 8 Based on this, continue to refer to Figure 9 In this embodiment, in the test structure, a plurality of test cells are arranged in an array along the first direction X, and along the second direction Y, two adjacent test cells are mirror images of each other.

[0127] In this embodiment, the substrate 500 further includes a first lead-out region g1 and a second lead-out region g2. The first lead-out region g1 is located between the first region I and the second region II, and the second lead-out region g2 is located between the second region II and the third region III.

[0128] In this embodiment, the test structure further includes: a plurality of first auxiliary lead-out areas 601 located on the first lead-out area g1 and the second area g2, the plurality of first auxiliary lead-out areas 601 being parallel to the first direction X and electrically connected to the first lead-out end 501; a plurality of second auxiliary lead-out areas 602 located on the second lead-out area g2 and the second area g2, the plurality of second auxiliary lead-out areas 602 being parallel to the first direction X and electrically connected to the second lead-out end 502, and the first auxiliary lead-out areas 601 and the second auxiliary lead-out areas 602 being arranged at intervals along the second direction Y; each test structure cell being located between a first auxiliary lead-out area 601 and a second auxiliary lead-out area 602, and the first electrode layer 511 of the test structure cell being electrically connected to the first auxiliary lead-out area 601, and the second electrode layer 512 of the test structure cell being electrically connected to the second auxiliary lead-out area 602.

[0129] Accordingly, another embodiment of the present invention also provides a method for forming the above-mentioned test structure, please refer to... Figure 9 Please refer to the previous description for details, which will not be repeated here.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: The substrate includes a first region, a second region, and a third region arranged along a first direction and separated from each other, wherein the second region is located between the first region and the third region; The first lead-out terminal located in the first region; A plurality of first electrode layers are located on the second region, and the plurality of first electrode layers are electrically connected to the first lead-out terminal. Each first electrode layer includes a plurality of first metal lines and a plurality of second metal lines that are interconnected. The first metal lines are parallel to the first direction, and the second metal lines are parallel to the second direction. The first direction and the second direction are parallel to the substrate surface and perpendicular to each other. Each end of a second metal line is connected to a first metal line. A plurality of second electrode layers are located on the second region, the plurality of second electrode layers and the plurality of first electrode layers are separated from each other, each second electrode layer includes a plurality of third metal lines and a plurality of fourth metal lines connected to each other, the third metal lines are parallel to a first direction, the fourth metal lines are parallel to a second direction, and each end of a fourth metal line is connected to a third metal line. The second metal lines and the fourth metal lines are arranged at intervals along the first direction, and the first metal lines and the third metal lines are arranged at intervals along the second direction. A second lead is located on the third region, and the second lead is electrically connected to a plurality of the second electrode layers.

2. The test structure as described in claim 1, characterized in that, The test structure further includes: a first dielectric layer located on the surface of the substrate, and a plurality of first electrode layers and a plurality of second electrode layers located within the first dielectric layer.

3. The test structure as described in claim 2, characterized in that, The test structure further includes: a plurality of third electrode layers located on the second region, wherein the plurality of third electrode layers are located on different layers from the plurality of first electrode layers, and the third electrode layers correspond one-to-one with the first electrode layers; each third electrode layer includes a plurality of fifth metal lines and a plurality of sixth metal lines interconnected with each other; the fifth metal lines are parallel to the first direction, the sixth metal lines are parallel to the second direction, and each of the sixth metal lines is connected at both ends to a fifth metal line; the first electrode layer has a first projection on the substrate surface, and the third electrode layer has a third projection on the substrate surface, wherein the first projection and the third projection at least partially overlap; and a plurality of first conductive plugs located between the third electrode layer and the corresponding first electrode layer to electrically connect the third electrode layer to the corresponding first electrode layer.

4. The test structure as described in claim 3, characterized in that, A plurality of first conductive plugs located between the fifth metal wire and the first metal wire are arranged along the first direction; a plurality of first conductive plugs located between the sixth metal wire and the second metal wire are arranged along the second direction.

5. The test structure as described in claim 3, characterized in that, The third electrode layer is located on the first electrode layer; the test structure further includes: a second dielectric layer located on the surface of a plurality of first electrode layers, a plurality of second electrode layers and a first dielectric layer, and a plurality of first conductive plugs and a plurality of the third electrode layers located within the second dielectric layer.

6. The test structure as described in claim 3, characterized in that, The first electrode layer is located on the third electrode layer; a plurality of the first conductive plugs are located within the first dielectric layer; the test structure further includes: a second dielectric layer located between the substrate surface and the first dielectric layer, and a plurality of the third electrode layers are located within the second dielectric layer.

7. The test structure as described in claim 3, characterized in that, The test structure further includes: a plurality of fourth electrode layers located on the second region, wherein the plurality of fourth electrode layers are separate from the plurality of third electrode layers and correspond one-to-one with the second electrode layers; each fourth electrode layer includes a plurality of seventh metal lines and a plurality of eighth metal lines interconnected thereto; the seventh metal lines are parallel to the first direction and the eighth metal lines are parallel to the second direction; each of the eighth metal lines is connected at both ends to a seventh metal line; the sixth metal lines and the eighth metal lines are arranged at intervals along the first direction; the fifth metal lines and the seventh metal lines are arranged at intervals along the second direction; the fourth electrode layer has a fourth projection on the substrate surface; the second electrode layer has a second projection on the substrate surface; the second projection and the fourth projection at least partially overlap; and a plurality of second conductive plugs located between the fourth electrode layer and the corresponding second electrode layer to electrically connect the fourth electrode layer and the corresponding second electrode layer.

8. The test structure as described in claim 7, characterized in that, The first conductive plug and the second conductive plug are arranged at intervals in the first direction or at intervals in the second direction; there is a first gap between adjacent first electrode layers and second electrode layers, and a second gap between adjacent first conductive plugs and second conductive plugs, the second gap being greater than the first gap.

9. The test structure as described in claim 7, characterized in that, A plurality of second conductive plugs located between the seventh metal wire and the third metal wire are arranged along the first direction; a plurality of second conductive plugs located between the eighth metal wire and the fourth metal wire are arranged along the second direction.

10. The test structure as described in claim 1, characterized in that, The test structure is a zigzag interdigitated structure. The first electrode layer has a first line end and a second line end opposite each other in the first direction, and the second electrode layer has a third line end and a fourth line end opposite each other in the first direction. The first lead-out end, the second lead-out end, the first electrode layer, and the second electrode layer are located in the same layer. The substrate also includes a first lead-out region and a second lead-out region. The first lead-out region is located between the first region and the second region, and the second lead-out region is located between the second region and the third region. The first line end extends to the first lead-out region to be electrically connected to the first lead-out end, and the third line end extends to the second lead-out region to be electrically connected to the second lead-out end.

11. The test structure as described in claim 10, characterized in that, In each of the first electrode layers, the number of the first metal wires is greater than or equal to 2, and the number of the second metal wires is greater than or equal to 1; in each of the second electrode layers, the number of the third metal wires is greater than or equal to 2, and the number of the fourth metal wires is greater than or equal to 1.

12. The test structure as described in claim 1, characterized in that, The test structure is a U-shaped structure, with the first electrode layer and the second electrode layer arranged concentrically. The first electrode layer includes two first metal lines arranged along the second direction and two second metal lines arranged along the first direction. The second electrode layer includes two third metal lines arranged along the second direction and two fourth metal lines arranged along the first direction.

13. The test structure as described in claim 12, characterized in that, The first lead-out terminal and the first electrode layer are located on different layers; the second lead-out terminal and the second electrode layer are located on different layers; the substrate further includes a first lead-out region and a second lead-out region, the first lead-out region being located between the first region and the second region, and the second lead-out region being located between the second region and the third region; the test structure further includes: a first auxiliary lead-out region located on the first lead-out region and the second region, the first auxiliary lead-out region being connected to the first lead-out terminal; a plurality of third conductive plugs located between the first auxiliary lead-out region and the first electrode layer, so that the first auxiliary lead-out region is electrically connected to each of the first electrode layers; a second auxiliary lead-out region located on the second lead-out region and the second region, the second auxiliary lead-out region being connected to the second lead-out terminal; and a plurality of fourth conductive plugs located between the second auxiliary lead-out region and the second electrode layer, so that the second auxiliary lead-out region is electrically connected to each of the second electrode layers.

14. The test structure as described in claim 1, characterized in that, The test structure is a spiral zigzag structure, with a first electrode layer and a second electrode layer forming a test unit. Each test unit has a winding center. The first electrode layer and the second electrode layer are wound around the winding center in the same direction in a spiral zigzag manner. The centers of different test units are different. In each test unit, the first electrode layer has a first end and a second end opposite to each other. The second end is located inside the first electrode layer. The first end is electrically connected to the first lead-out end. The second electrode layer has a third end and a fourth end opposite to each other. The fourth end is located inside the second electrode layer. The third end is electrically connected to the second lead-out end.

15. The test structure as described in claim 14, characterized in that, The number of test units is greater than or equal to one; a plurality of test units are arranged in an array along the first direction, and along the second direction, two adjacent test units are mirror images of each other.

16. The test structure as described in claim 15, characterized in that, The substrate further includes a first lead-out region and a second lead-out region, the first lead-out region being located between the first region and the second region, and the second lead-out region being located between the second region and the third region; the test structure further includes: a plurality of first auxiliary lead-out regions located on the first lead-out region and the second region, the plurality of first auxiliary lead-out regions being parallel to the first direction and electrically connected to the first lead-out terminal; a plurality of second auxiliary lead-out regions located on the second lead-out region and the second region, the plurality of second auxiliary lead-out regions being parallel to the first direction and electrically connected to the second lead-out terminal, and the first auxiliary lead-out regions and the second auxiliary lead-out regions being arranged at intervals along the second direction; each test structure is located between a first auxiliary lead-out region and a second auxiliary lead-out region, and the first electrode layer of the test structure is electrically connected to the first auxiliary lead-out region, and the second electrode layer of the test structure is electrically connected to the second auxiliary lead-out region.

17. The test structure as described in claim 1, characterized in that, The number of first electrode layers is greater than or equal to 1; the number of second electrode layers is greater than or equal to 1; in each first electrode layer, the number of first metal wires is greater than or equal to 1, and the number of second metal wires is greater than or equal to 1; in each second electrode layer, the number of third metal wires is greater than or equal to 1, and the number of fourth metal wires is greater than or equal to 1.

18. A method for forming a test structure, characterized in that, include: A substrate is provided, the substrate comprising a first region, a second region, and a third region arranged along a first direction and being mutually independent, the second region being located between the first region and the third region; A first lead-out terminal is formed on the first region; A plurality of first electrode layers are formed on the second region. The plurality of first electrode layers are electrically connected to the first lead-out terminal. Each first electrode layer includes a plurality of first metal lines and a plurality of second metal lines that are interconnected. The first metal lines are parallel to the first direction, and the second metal lines are parallel to the second direction. The first direction and the second direction are parallel to the substrate surface and perpendicular to each other. Each end of a second metal line is connected to a first metal line. A plurality of second electrode layers are formed on the second region. The plurality of second electrode layers and the plurality of first electrode layers are separated from each other. Each second electrode layer includes a plurality of third metal lines and a plurality of fourth metal lines that are interconnected. The third metal lines are parallel to a first direction, and the fourth metal lines are parallel to a second direction. Each end of a fourth metal line is connected to a third metal line. The second metal lines and the fourth metal lines are arranged at intervals along the first direction, and the first metal lines and the third metal lines are arranged at intervals along the second direction. A second lead is formed on the third region, and the second lead is electrically connected to a plurality of the second electrode layers.

19. The method for forming the test structure as described in claim 18, characterized in that, The method further includes: forming a plurality of third electrode layers on the second region, wherein the plurality of third electrode layers are located on different layers from the plurality of first electrode layers, and the third electrode layers correspond one-to-one with the first electrode layers; each third electrode layer includes a plurality of fifth metal lines and a plurality of sixth metal lines interconnected with each other; the fifth metal lines are parallel to the first direction, the sixth metal lines are parallel to the second direction, and each of the fifth metal lines is connected at both ends to a sixth metal line; the first electrode layer has a first projection on the substrate surface, and the third electrode layer has a third projection on the substrate surface, wherein the first projection and the third projection at least partially overlap; and forming a plurality of first conductive plugs between the third electrode layer and the corresponding first electrode layer to electrically connect the third electrode layer to the corresponding first electrode layer.

20. The method for forming the test structure as described in claim 19, characterized in that, The third electrode layer is located on the first electrode layer; A method for forming a plurality of first conductive plugs, a first electrode layer, a second electrode layer, and a third electrode layer includes: forming a first dielectric layer on the substrate; forming a plurality of first electrode layers and a plurality of second electrode layers within the first dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer, the plurality of first electrode layers, and the plurality of second electrode layers; and forming a plurality of first conductive plugs and a plurality of third electrode layers within the second dielectric layer.

21. The method for forming the test structure as described in claim 19, characterized in that, The first electrode layer is located on the third electrode layer; the method of forming a plurality of first conductive plugs, a first electrode layer, a second electrode layer and a third electrode layer includes: forming a second dielectric layer on the substrate; forming the third electrode layer in the second dielectric layer; forming a first dielectric layer on the surface of the second dielectric layer and the plurality of third electrode layers; and forming a plurality of first conductive plugs, a plurality of first electrode layers and a plurality of second electrode layers in the first dielectric layer.

22. The method for forming the test structure as described in claim 19, characterized in that, The method further includes: forming a plurality of third electrode layers while simultaneously forming a plurality of fourth electrode layers on the second region, wherein the plurality of fourth electrode layers are discrete from the plurality of third electrode layers and each fourth electrode layer corresponds to a second electrode layer; each fourth electrode layer includes a plurality of seventh metal lines and a plurality of eighth metal lines interconnected, wherein the seventh metal lines are parallel to the first direction and the eighth metal lines are parallel to the second direction; each eighth metal line is connected at both ends to a seventh metal line; the sixth metal lines and the eighth metal lines are spaced apart along the first direction; the fifth metal lines and the seventh metal lines are spaced apart along the second direction; the fourth electrode layer has a fourth projection on the substrate surface; the second electrode layer has a second projection on the substrate surface; the second projection and the fourth projection at least partially overlap; and forming a plurality of second conductive plugs between the fourth electrode layer and the corresponding second electrode layer to electrically connect the fourth electrode layer to the corresponding second electrode layer.

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