Semiconductor test structure and semiconductor test method
By designing an array-based semiconductor test structure to measure dielectric breakdown, the problem of dielectric breakdown risk is solved, device reliability is improved, and device miniaturization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-06-05
Smart Images
Figure CN122161412A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing, and in particular to a semiconductor testing structure and a semiconductor testing method. Background Technology
[0002] In semiconductor manufacturing, process reliability is one of the core indicators for measuring product lifespan and stability. As the size of integrated circuit devices continues to shrink, reliability issues are becoming increasingly prominent. Among them, time-dependent dielectric breakdown (TDDB) is a time-related failure mechanism. Even under conditions where the applied electric field is below the critical electric field, the dielectric layer may still break down after being subjected to long-term stress, thus affecting the reliability of the device.
[0003] As integrated circuit process dimensions continue to shrink, the distance between the source / drain contact structure (CT) and the polysilicon gate (Poly) in transistors is also significantly reduced, exacerbating the optical proximity effect and thus increasing the risk of dielectric breakdown over time. Summary of the Invention
[0004] Based on this, the embodiments of this application provide a semiconductor test structure and a semiconductor test method, which can effectively monitor dielectric breakdown phenomena and facilitate device miniaturization.
[0005] To achieve the above objectives, in one aspect, some embodiments of this application provide a semiconductor test structure. This semiconductor test structure includes a test gate, multiple contact structures, a first test lead-out structure, and a second test lead-out structure. The multiple contact structures are arranged in a column at intervals along a first direction parallel to the substrate; the contact structures and the test gate have a first distance between them in a second direction parallel to the substrate; the second direction intersects the first direction; the first test lead-out structure is electrically connected to one end of the test gate; the second test lead-out structure extends along the first direction and is electrically connected to the same column of contact structures.
[0006] In some embodiments, the test gates extend along the first direction; the number of test gates is plurality of, corresponding to one side of each column of contact structures in the second direction; wherein, the first test lead structure is electrically connected to one end of the plurality of test gates; the second test lead structure includes a plurality of second lead wires and a second common wire. The plurality of second lead wires extend along the first direction and are electrically connected to each column of contact structures; the second common wire extends along the second direction and is electrically connected to one end of the plurality of second lead wires in the first direction away from the first test lead structure.
[0007] In some embodiments, the semiconductor test structure further includes a first test pad and a second test pad. The first test pad is electrically connected to the first test lead structure; the second test pad is electrically connected to the second common conductor.
[0008] In some embodiments, the plurality of contact structures are arranged in rows at intervals along the second direction; the semiconductor test structure further includes a plurality of strip-shaped active regions; the plurality of strip-shaped active regions extend along the second direction and are located between adjacent rows of contact structures; wherein adjacent strip-shaped active regions have a second spacing in the first direction.
[0009] In some embodiments, the orthographic projections of the plurality of strip-shaped active regions in the direction perpendicular to the substrate intersect the orthographic projections of the plurality of test gates in the direction perpendicular to the substrate in a mesh pattern.
[0010] In some embodiments, the test gate includes a first sub-gate and a second sub-gate; the first sub-gate extends along the first direction; the second sub-gate extends along the second direction; wherein the first sub-gate and the second sub-gate are alternately connected along the first direction to integrally form the test gate; the contact structure is located between adjacent second sub-gates; the contact structure and its adjacent first sub-gate have a first spacing in the second direction, and the contact structure and its adjacent second sub-gate have a third spacing in the first direction.
[0011] In some embodiments, the third spacing is equal to the first spacing.
[0012] On the other hand, this application also provides a semiconductor testing method according to some embodiments; the semiconductor testing method is implemented based on the semiconductor testing structure described in the preceding aspect of this application.
[0013] In some embodiments, the semiconductor testing method includes the following steps.
[0014] The preset contact structure and the test gate are spaced at multiple first distances in a second direction parallel to the substrate.
[0015] The dielectric breakdown between the first test lead structure and the second test lead structure is monitored under different values of the first spacing; wherein the first test lead structure is electrically connected to the test gate, and the second test lead structure is electrically connected to the contact structure in the same column;
[0016] The minimum value of the first spacing in the non-breakdown state is determined as the first target process parameter.
[0017] In some embodiments, the semiconductor testing method further includes the following steps.
[0018] The preset contact structure and the test gate have multiple first spacings, and adjacent strip-shaped active regions have multiple second spacings in a first direction parallel to the substrate; wherein the first direction intersects the second direction.
[0019] The dielectric breakdown between the first test lead structure and the second test lead structure is detected under different values of the first spacing and different values of the second spacing.
[0020] The minimum value of the first spacing and the minimum value of the second spacing in the non-breakdown state are respectively determined as the first target process parameter and the second target process parameter.
[0021] In some embodiments, the test gate includes a first sub-gate extending along the first direction and a second sub-gate extending along the second direction; the first sub-gate and the second sub-gate are alternately connected along the first direction to integrally form the test gate; the contact structure is located between adjacent second sub-gates; the semiconductor testing method further includes the following steps.
[0022] The preset contact structure and its adjacent second sub-gate have multiple third spacings in the first direction.
[0023] Monitor the dielectric breakdown between the first test lead structure and the second test lead structure under different values of the third spacing.
[0024] The minimum value of the third spacing in the non-breakdown state is determined as the third target process parameter.
[0025] The embodiments of this application may have, or at least have, the following advantages:
[0026] In this embodiment, the contact structures of the transistor source and drain regions are arrayed to form multiple contact structures spaced in columns along a first direction (e.g., the Y direction). A test gate is provided for each column of contact structures, such that each column of contact structures and its corresponding test gate have a first distance in a second direction. Furthermore, a first test lead structure electrically connected to the test gate is provided, and the contact structures in the same column are connected via a second test lead structure to form a contact chain structure (Rc Chain). Based on these technical features, by applying a stress voltage between the first and second test lead structures, the dielectric breakdown between multiple contact structures and the test gate can be measured simultaneously, thereby obtaining the relationship between the key size variable (i.e., the first distance) and dielectric breakdown. Thus, the minimum process parameters for the first distance can be obtained while effectively preventing dielectric breakdown, thereby not only improving the reliability of semiconductor devices but also facilitating device miniaturization.
[0027] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a semiconductor test structure provided in some embodiments;
[0030] Figure 2 This is a schematic diagram of another semiconductor test structure provided in some embodiments;
[0031] Figure 3 This is a schematic diagram of yet another semiconductor test structure provided in some embodiments;
[0032] Figure 4 This is a flowchart illustrating a semiconductor testing method provided in some embodiments;
[0033] Figure 5 This is a flowchart illustrating another semiconductor testing method provided in some embodiments;
[0034] Figure 6 This is a flowchart illustrating yet another semiconductor testing method provided in some embodiments.
[0035] Explanation of reference numerals in the attached figures:
[0036] 1-Test gate, 11-First sub-gate, 12-Second sub-gate, 2-Contact structure, 3-First test lead structure, 31-First lead wire, 32-First common wire, 4-Second test lead structure, 41-Second lead wire, 42-Second common wire, 5-First test pad, 6-Second test pad, 7-Interconnect structure, AA-Strip active area. Detailed Implementation
[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0039] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0041] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.
[0042] This application provides a semiconductor test structure and semiconductor test method that can effectively monitor dielectric breakdown and facilitate device miniaturization.
[0043] In some embodiments, please refer to Figure 1The semiconductor test structure includes a test gate 1, multiple contact structures 2, a first test lead-out structure 3, and a second test lead-out structure 4. The multiple contact structures 2 are arranged in columns at intervals along a first direction (e.g., the Y direction) parallel to the substrate; the contact structures 2 and the test gate 1 have a first spacing x1 in a second direction (e.g., the X direction) parallel to the substrate; the second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction); the first test lead-out structure 3 is electrically connected to one end of the test gate 1; the second test lead-out structure 4 extends along the first direction (e.g., the Y direction) and is electrically connected to the same column of contact structures 2.
[0044] For example, the first direction (e.g., the Y direction) is orthogonal to the second direction (e.g., the X direction).
[0045] In some examples, such as Figure 1 As shown, the test gate 1 extends in a strip shape along a first direction (e.g., the Y direction).
[0046] In some embodiments, the semiconductor structure includes a plurality of transistors; the plurality of transistors are arranged in an array, and are spaced apart in columns along a first direction (e.g., the Y direction) and spaced apart in rows along a second direction (e.g., the X direction).
[0047] It should be noted that transistors in the same column share a single test gate 1.
[0048] In some examples, the transistor includes source and drain regions located on either side of the test gate 1 in a second direction (e.g., the X direction); wherein the contact structure 2 is located on the side of the corresponding source or drain region away from the substrate in the direction perpendicular to the substrate and is in ohmic contact with the source or drain region.
[0049] For example, in an embodiment where the test gate 1 extends in a strip shape along a first direction (e.g., the Y direction) (such as...) Figure 1 In the test gate 1, each column of contact structure 2 is located on one side of the corresponding test gate 1 in the second direction (e.g., the X direction).
[0050] For example, the material of test gate 1 includes, but is not limited to, polysilicon.
[0051] For example, contact structure 2 can be a contact layer or a pad. The material of the contact layer includes, but is not limited to, metal silicides, such as titanium silicides or cobalt silicides; the material of the pad includes, but is not limited to, conductive metals, such as copper (Cu).
[0052] For example, multiple contact structures 2 have the same dimensions in a first direction (e.g., the Y direction).
[0053] For example, multiple contact structures 2 have the same dimensions in a second direction (e.g., the X direction).
[0054] For example, the value of the first spacing x1 ranges from 30nm to 70nm.
[0055] For example, the value of the first spacing x1 can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm or 70nm, etc.
[0056] For example, the material of structure 3 obtained by the first test includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zn).
[0057] For example, the material of the second test leading to structure 4 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zn).
[0058] It should be noted that in this embodiment of the application, the second test lead-out structure 4 connects the contact structures 2 in the same column in series to form a contact chain structure (Rc Chain).
[0059] In this embodiment, the contact structures 2 of the transistor source and drain regions are arrayed to form multiple contact structures 2 arranged in columns along a first direction (e.g., the Y direction). A test gate 1 is provided for each column of contact structures 2, such that each column of contact structures 2 and its corresponding test gate 1 have a first spacing x1 in a second direction (e.g., the X direction). Furthermore, a first test lead structure 3 electrically connected to the test gate 1 is provided, and the contact structures 2 in the same column are connected to a common terminal through a second test lead structure 4 to form a contact chain structure (Rc Chain). Based on the above technical features, by applying a stress voltage between the first test lead structure 3 and the second test lead structure 4, the dielectric breakdown between multiple contact structures 2 and the test gate 1 can be measured simultaneously, thereby obtaining the relationship between the key size variable (i.e., the first spacing x1) and dielectric breakdown. In this way, the minimum process parameter of the first spacing x1 can be obtained while effectively preventing dielectric breakdown, thereby not only improving the reliability of semiconductor devices but also facilitating device miniaturization.
[0060] For example, the above-mentioned dielectric breakdown includes time-dependent dielectric breakdown (TDDB).
[0061] In some embodiments, please continue reading Figure 1The test gate 1 extends along a first direction (e.g., the Y direction); there are multiple test gates 1, corresponding to one side of each column of contact structures 2 in a second direction (e.g., the X direction); wherein, the first test lead structure 3 is electrically connected to one end of the multiple test gates 1; the second test lead structure 4 includes multiple second lead wires 41 and a second common wire 42. The multiple second lead wires 41 extend along the first direction (e.g., the Y direction) and are electrically connected to each column of contact structures 2; the second common wire 42 extends along the second direction (e.g., the X direction) and is electrically connected to one end of the multiple second lead wires 41 in the first direction (e.g., the Y direction) away from the first test lead structure 3.
[0062] It should be noted that the lead wire 41 and the second common wire 42 of the same second test lead structure 4 are an integral structure.
[0063] For example, multiple test gates 1 have the same size in a first direction (e.g., the Y direction).
[0064] For example, multiple test gates 1 have the same size in a second direction (e.g., the X direction).
[0065] For example, the contact structure 2 is located on the same side of the corresponding test gate 1 in the second direction (e.g., the X direction).
[0066] In some embodiments, please continue reading Figure 1 The first test lead structure 3 includes a first lead wire 31 and a first common wire 32. The plurality of first lead wires 31 extend along a first direction (e.g., the Y direction) and are electrically connected to the test gate 1. The first common wire 32 extends along a second direction (e.g., the X direction) and is electrically connected to one end of the plurality of first lead wires 31 that is away from the second test lead structure 4 in the first direction (e.g., the Y direction).
[0067] It should be noted that the first lead wire 31 and the first common wire 32 of the same first test lead structure 3 are an integral structure.
[0068] In some embodiments, please continue reading Figure 1 The first lead wire 31 is electrically connected to the test gate 1 through the interconnect structure 7.
[0069] For example, the material of the interconnect structure 7 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zu).
[0070] In some embodiments, please continue reading Figure 1The semiconductor test structure also includes a first test pad 5 and a second test pad 6. The first test pad 5 is electrically connected to the first test lead structure 3; the second test pad 6 is electrically connected to the second common conductor 42.
[0071] For example, the first test pad 5 is electrically connected to the first common conductor 32.
[0072] For example, the material of the first test pad 5 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zu).
[0073] For example, the material of the second test pad 6 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zu).
[0074] It should be noted that, in the process of testing the semiconductor test structure in this embodiment of the application, stress voltage can be applied between the first test pad 5 and the second test pad 6 to simultaneously measure the dielectric breakdown between multiple contact structures 2 and the test gate 1.
[0075] In some embodiments, please refer to Figure 2 Multiple contact structures 2 are arranged in rows at intervals along a second direction (e.g., the X direction); the semiconductor test structure also includes multiple strip-shaped active regions AA; the multiple strip-shaped active regions AA extend along the second direction (e.g., the X direction) and are located between adjacent rows of contact structures 2; wherein, adjacent strip-shaped active regions AA have a second spacing x2 in a first direction (e.g., the Y direction).
[0076] In some embodiments, a shallow trench isolation structure (STI) is provided in the interval region between adjacent strip-shaped active regions AA.
[0077] For example, multiple strip-shaped active regions AA have the same size in the first direction (e.g., the Y direction).
[0078] For example, multiple strip-shaped active regions AA have the same size in the second direction (e.g., the X direction).
[0079] For example, the second spacing x2 is greater than the first spacing x1.
[0080] For example, the value of the second spacing x2 ranges from 80nm to 140nm.
[0081] For example, the value of the second spacing x2 can be 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 108nm, 110nm, 115nm, 120nm, 125nm, 130nm, 132nm, 135nm, or 140nm, etc.
[0082] In this embodiment, by applying a stress voltage between the first test pad 5 and the second test pad 6, the dielectric breakdown between multiple contact structures 2 and the test gate 1 can be measured simultaneously, and the relationship between the first spacing x1 and dielectric breakdown and the relationship between the second spacing x2 and dielectric breakdown can be obtained. Thus, the minimum process parameters of the first spacing x1 and the second spacing x2 can be obtained while effectively preventing dielectric breakdown. This not only improves the reliability of semiconductor devices, but also facilitates device miniaturization.
[0083] It should be noted that by measuring the relationship between the second spacing x2 and dielectric breakdown, the dielectric breakdown problem caused by excessive step height between the shallow trench isolation structure and the strip active area AA can be effectively monitored.
[0084] In some embodiments, please refer to Figure 2 The orthographic projections of multiple strip-shaped active regions AA in the direction perpendicular to the substrate intersect with the orthographic projections of multiple test gates 1 in the direction perpendicular to the substrate in a mesh pattern.
[0085] In some embodiments, please refer to Figure 3 The test gate 1 includes a first sub-gate 11 and a second sub-gate 12; the first sub-gate 11 extends along a first direction (e.g., the Y direction); the second sub-gate 12 extends along a second direction (e.g., the X direction); wherein the first sub-gate 11 and the second sub-gate 12 are alternately connected along the first direction (e.g., the Y direction) to form a test gate 1; a contact structure 2 is located between adjacent second sub-gates 12; the contact structure 2 and its adjacent first sub-gate 11 have a first spacing x1 in the second direction (e.g., the X direction), and the contact structure 2 and its adjacent second sub-gate 12 have a third spacing x3 in the first direction (e.g., the Y direction).
[0086] In some embodiments, the third spacing x3 is equal to the first spacing x1.
[0087] For example, the value of the third spacing x3 ranges from 30nm to 70nm.
[0088] For example, the value of the third spacing x3 can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, or 70nm, etc.
[0089] In this embodiment, by applying a stress voltage between the first test pad 5 and the second test pad 6, the dielectric breakdown between multiple contact structures 2 and the test gate 1 can be measured simultaneously, and the relationship between the first spacing x1 and dielectric breakdown and the relationship between the third spacing x3 and dielectric breakdown can be obtained. Thus, the minimum process parameters of the first spacing x1 and the third spacing x3 can be obtained while effectively preventing dielectric breakdown. This not only improves the reliability of semiconductor devices, but also facilitates device miniaturization.
[0090] It should be noted that by measuring the relationship between the third spacing x3 and dielectric breakdown, the dielectric breakdown caused by the corner rounding problem at the connection position of the first sub-gate 11 and the second sub-gate 12 of the test gate 1 can be effectively monitored.
[0091] This application also provides a semiconductor testing method according to some embodiments, which is implemented based on the semiconductor testing structure of the foregoing embodiments of this application. The semiconductor testing method also possesses all the technical advantages of the foregoing semiconductor testing structure. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be described in detail below.
[0092] In some embodiments, please refer to Figure 4 The semiconductor testing method includes the following steps S110~S130.
[0093] S110, a preset contact structure and a test gate are spaced at multiple first distances in a second direction parallel to the substrate.
[0094] S120, monitor the dielectric breakdown between the first test lead structure and the second test lead structure under different first spacing values; wherein, the first test lead structure is electrically connected to the test gate, and the second test lead structure is electrically connected to the same column of contact structures.
[0095] In this step, a stress voltage is applied between the first test lead structure and the second test lead structure to obtain the dielectric breakdown status between the contact structure and the test gate.
[0096] S130, the minimum value of the first gap in the non-breakdown state is determined as the first target process parameter.
[0097] In this embodiment, multiple first gaps are preset between the contact structure and the test gate. A stress voltage is applied between the first test lead structure and the second test lead structure, while simultaneously measuring the dielectric breakdown between the multiple contact structures and the test gate. This allows the relationship between the first gaps and dielectric breakdown to be obtained. Thus, the minimum value of the first gap in the non-breakdown state is obtained and determined as the first target process parameter, thereby determining the minimum process parameter for the first gap.
[0098] In some embodiments, please refer to Figure 5 The semiconductor testing method also includes the following steps S210~S230.
[0099] S210, a plurality of first spacings between the preset contact structure and the test gate, and a plurality of second spacings between adjacent strip-shaped active regions in a first direction parallel to the substrate; wherein the first direction intersects the second direction.
[0100] S220, detect the dielectric breakdown between the first test lead structure and the second test lead structure under different first spacing values and different second spacing values.
[0101] S230, the minimum value of the first gap and the minimum value of the second gap in the non-breakdown state are determined as the first target process parameter and the second target process parameter, respectively.
[0102] In this embodiment, multiple first spacings and multiple second spacings are preset between the contact structure and the test gate. A stress voltage is applied between the first test lead structure and the second test lead structure, while simultaneously measuring the dielectric breakdown between the multiple contact structures and the test gate. This allows the determination of the relationship between the first spacing and dielectric breakdown, as well as the relationship between the second spacing and dielectric breakdown. Thus, the minimum values of the first spacing and the second spacing in the non-breakdown state are determined as the first target process parameter and the second target process parameter, respectively, thereby determining the minimum process parameters for the first spacing and the second spacing.
[0103] In some embodiments, the test gate includes a first sub-gate extending along a first direction and a second sub-gate extending along a second direction; the first sub-gate and the second sub-gate are alternately connected along the first direction to integrally form the test gate; a contact structure is located between adjacent second sub-gates; see also Figure 6 The semiconductor testing method also includes the following steps S310~S330.
[0104] S310, a preset contact structure and its adjacent second sub-gate with multiple third spacings in a first direction.
[0105] S320 monitors the dielectric breakdown between the first test lead-out structure and the second test lead-out structure under different values of the third spacing.
[0106] S330, the minimum value of the third spacing in the non-breakdown state is determined as the third target process parameter.
[0107] In this embodiment, multiple third spacings are preset between the contact structure and the test gate. A stress voltage is applied between the first and second test leads, and the dielectric breakdown between the multiple contact structures and the test gate is measured simultaneously to obtain the relationship between the third spacing and dielectric breakdown. Thus, the minimum value of the third spacing in the non-breakdown state is obtained and determined as the third target process parameter, thereby determining the minimum process parameter for the third spacing.
[0108] In the description of this specification, references to terms such as "some embodiments," "some examples," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0110] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.
Claims
1. A semiconductor testing structure, characterized in that, include: Test gate; Multiple contact structures are arranged in columns at intervals along a first direction parallel to the substrate; the contact structures and the test gate have a first distance in a second direction parallel to the substrate. The second direction intersects with the first direction; The first test lead-out structure is electrically connected to one end of the test gate; The second test lead-out structure extends along the first direction and is electrically connected to the same column of the contact structures.
2. The semiconductor test structure according to claim 1, characterized in that, The test gate extends along the first direction; there are multiple test gates, each located on one side of each column of the contact structure in the second direction; wherein, The first test lead structure is electrically connected to one end of the plurality of test gates; The second test lead-out structure includes: Multiple second lead wires extend along the first direction and are electrically connected to each column of the contact structures. The second common conductor extends along the second direction and electrically connects the plurality of second lead conductors at one end of the first test lead structure away from the first test lead structure in the first direction.
3. The semiconductor test structure according to claim 2, characterized in that, Also includes: The first test pad is electrically connected to the first test lead structure; The second test pad is electrically connected to the second common conductor.
4. The semiconductor test structure according to claim 2, characterized in that, The plurality of contact structures are arranged in rows at intervals along the second direction; the semiconductor test structure further includes: Multiple strip-shaped active regions extend along the second direction and are located between adjacent rows of the contact structures; The adjacent strip-shaped active regions have a second spacing in the first direction.
5. The semiconductor test structure according to claim 4, characterized in that, The orthographic projections of the plurality of strip-shaped active regions in the direction perpendicular to the substrate intersect the orthographic projections of the plurality of test gates in the direction perpendicular to the substrate in a mesh pattern.
6. The semiconductor test structure according to claim 1, characterized in that, The test gate includes: The first sub-gate extends along the first direction; The second sub-gate extends along the second direction; The first sub-gate and the second sub-gate are alternately connected along the first direction to form the test gate; the contact structure is located between adjacent second sub-gates; the contact structure and its adjacent first sub-gate have the first spacing in the second direction, and the contact structure and its adjacent second sub-gate have the third spacing in the first direction.
7. The semiconductor test structure according to claim 6, characterized in that, The third spacing is equal to the first spacing.
8. A semiconductor testing method, characterized in that, The semiconductor testing structure is implemented based on any one of claims 1 to 7; the semiconductor testing method includes: The preset contact structure and the test gate are spaced at multiple first distances in a second direction parallel to the substrate; The dielectric breakdown between the first test lead structure and the second test lead structure is monitored under different values of the first spacing; wherein the first test lead structure is electrically connected to the test gate, and the second test lead structure is electrically connected to the contact structure in the same column; The minimum value of the first spacing in the non-breakdown state is determined as the first target process parameter.
9. The semiconductor testing method according to claim 8, characterized in that, Also includes: The preset contact structure and the test gate have multiple first spacings, and adjacent strip-shaped active regions have multiple second spacings in a first direction parallel to the substrate; wherein the first direction intersects the second direction; Detect the dielectric breakdown between the first test lead structure and the second test lead structure under different values of the first spacing and different values of the second spacing; The minimum value of the first spacing and the minimum value of the second spacing in the non-breakdown state are respectively determined as the first target process parameter and the second target process parameter.
10. The semiconductor testing method according to claim 8, characterized in that, The test gate includes a first sub-gate extending along the first direction and a second sub-gate extending along the second direction; the first sub-gate and the second sub-gate are alternately connected along the first direction and integrally form the test gate. The contact structure is located between adjacent second sub-gates; the semiconductor testing method further includes: The preset contact structure and its adjacent second sub-gate have multiple third spacings in the first direction; Monitor the dielectric breakdown between the first test lead-out structure and the second test lead-out structure under different values of the third spacing; The minimum value of the third spacing in the non-breakdown state is determined as the third target process parameter.