Industrial control logic generation and security guarantee method based on large language model and closed loop verification and related equipment

Abstract

The application discloses an industrial control logic generation and security guarantee method based on a large language model and a closed loop verification and related equipment, and relates to the technical field of industrial control logic generation and security guarantee. The application discloses an industrial control logic generation and security guarantee method based on a large language model and a closed loop verification and related equipment, and relates to the technical field of industrial control logic generation and security guarantee. The application can improve the engineering development efficiency of industrial control logic and reduce the error cost, and can be widely applied to the fields of industrial control system automation engineering and network security technology.

Description

Technical Field

[0001] This invention relates to the fields of industrial control system automation engineering and network security technology, and in particular to a method and related equipment for generating and ensuring the security of industrial control logic based on a large language model and closed-loop verification. Background Technology

[0002] PLCs are the core of industrial automation, and their control logic is typically written using languages ​​defined by the IEC 61131-3 standard (such as ladder diagrams, function block diagrams, and structured text). Current industrial control logic engineering heavily relies on engineers manually translating unstructured natural language requirements documents into rigorous, IEC-compliant PLC control logic. This process is labor-intensive, time-consuming, and prone to introducing syntactic or functional logic errors, severely hindering the rapid development and deployment of industrial software. While intelligent generation solutions, such as LLMs, improve efficiency, their verification mechanisms (such as the functional verification of Spec2Control) are superficial and cannot fundamentally guarantee the quality of the generated code. In the detection of security vulnerabilities in industrial control logic, traditional functional testing and existing independent security verification tools (such as PyLC / Pynguin, StructuredFuzzer, and PLC-VBS) are open-loop, lagging post-audit methods. They cannot proactively and efficiently discover and fix industrial security risks such as JMP logic skipping, scan cycle anomalies caused by malicious loops, and external malicious tampering of critical variables (variable persistence vulnerabilities) before deployment. More importantly, these tools cannot translate complex security reports into structured, machine-understandable instructions to automate code correction, thus failing to create an efficient security delivery loop. Summary of the Invention

[0003] In view of this, the main objective of the embodiments of the present invention is to provide a method and related equipment for generating and ensuring the security of industrial control logic based on a large language model and closed-loop verification, in order to solve at least one of the problems in the prior art. The present invention can improve the engineering development efficiency of industrial control logic and reduce error costs.

[0004] To achieve the above objectives, one aspect of this invention provides a method for generating and ensuring the security of industrial control logic based on a large language model and closed-loop verification. The method includes: The input data undergoes a first transformation to obtain a structured intermediate representation; The intermediate representation is then transformed to obtain the control logic code; Static compliance verification and dynamic security verification are performed on the control logic code to obtain compliance verification results and security verification results, respectively. When the compliance verification result is a verification failure or the security verification result is a verification failure, a structured correction prompt is obtained, the control logic code is corrected according to the structured correction prompt, and the steps of performing static compliance verification and dynamic security verification on the control logic code are returned. When both the compliance verification result and the security verification result are successful, output a security verification metadata report and the control logic code.

[0005] In some embodiments, performing a first transformation on the input data to obtain a structured intermediate representation includes the following steps: Receive input natural language text and obtain input data; By using a pre-trained domain model, the input data is analyzed at multiple levels to obtain key entities and logical relationships; The key entities and logical relationships are first transformed to obtain the intermediate representation in structured JSON format.

[0006] In some embodiments, the second transformation of the intermediate representation to obtain control logic code includes the following steps: By using data from the industrial control field, the initial basic model is fine-tuned to obtain the target basic model; The intermediate representation is input into the target basic large model, and the program code structure is obtained based on the logical type field in the intermediate representation; Based on the input variable fields in the intermediate representation, generate the corresponding input variable definitions within the program code structure; Based on the output action field in the intermediate representation, generate the corresponding output action definition within the program code structure; Based on the defined input variables and the defined output actions, basic execution logic is generated; The security constraint field in the intermediate representation is used as the highest priority interlocking logic or exception handling code and embedded into the critical path of the basic execution logic to obtain the control logic code.

[0007] In some embodiments, performing static compliance verification and dynamic security verification on the control logic code to obtain compliance verification results and security verification results respectively includes the following steps: The control logic code is subjected to format verification and semantic analysis to obtain the compliance verification result; The control logic code is subjected to logic flow tampering detection and variable persistence vulnerability scanning to obtain the security verification results.

[0008] In some embodiments, the step of performing logic flow tampering detection and variable persistence vulnerability scanning on the control logic code to obtain the security verification result includes the following steps: Import the control logic code into the simulation runtime environment to dynamically obtain the scan cycle; Predict the baseline period threshold and the maximum safe period threshold; The scan period is compared with the baseline period threshold and the maximum safe period threshold; When the scanning period is greater than the maximum security period threshold, a malicious loop vulnerability exists, and the security verification result is output as verification failure. When the scanning period is less than the baseline period threshold, abnormal behavior exists, and the security verification result is output as verification failure.

[0009] In some embodiments, the method of performing logic flow tampering detection and variable persistence vulnerability scanning on the control logic code to obtain the security verification result further includes the following steps: Import the control logic code into the simulation runtime environment and identify the key physical output data block variables; Obtain the memory address corresponding to the data block variable; Through the industrial communication protocol interface, an external malicious attacker is simulated during the current scanning cycle to write malicious values ​​to the memory address; The stored value at the memory address is read in the next scan cycle; When the stored value is the malicious value or the stored value is close to the malicious value, a variable persistence vulnerability exists, and the security verification result is output as verification failure.

[0010] In some embodiments, when the compliance verification result is a verification failure or the security verification result is a verification failure, obtaining a structured correction prompt and correcting the control logic code according to the structured correction prompt includes the following steps: A verification report is generated when the compliance verification result is a verification failure or the security verification result is a verification failure. The verification report is parsed to obtain the structured correction prompts; Based on the structured correction prompts, the control logic code is partially modified to obtain the corrected control logic code; The structured correction prompt includes safety features, fault location information, and correction requirements.

[0011] To achieve the above objectives, another aspect of this invention proposes an industrial control logic generation and security assurance system based on a large language model and closed-loop verification, the system comprising: The optimization module is used to perform a first transformation on the input data to obtain a structured intermediate representation; A generation module is used to perform a second transformation on the intermediate representation to obtain control logic code; The verification module is used to perform static compliance verification and dynamic security verification on the control logic code, and obtain compliance verification results and security verification results respectively. The structured feedback generation module is used to obtain a structured correction prompt when the compliance verification result is a verification failure or the security verification result is a verification failure, correct the control logic code according to the structured correction prompt, and return to the steps of performing static compliance verification and dynamic security verification on the control logic code. The output module is used to output a security verification metadata report and the control logic code when the compliance verification result is successful and the security verification result is successful.

[0012] To achieve the above objectives, another aspect of the present invention provides an electronic device, the electronic device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method described above.

[0013] To achieve the above objectives, another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0014] To achieve the above objectives, another aspect of the present invention provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions to cause the computer device to perform the aforementioned method.

[0015] The embodiments of the present invention include at least the following beneficial effects: The present invention provides a method and related equipment for generating and ensuring the security of industrial control logic based on a large language model and closed-loop verification. This scheme performs a first transformation on the input data to obtain a structured intermediate representation, providing a unified and standardized intermediate data representation for subsequent processing, thereby improving processing efficiency and accuracy; performs a second transformation on the intermediate representation to obtain control logic code, ensuring that the generated logic can be smoothly imported and compiled in the engineering software of different mainstream PLC manufacturers; and performs static compliance verification and dynamic security verification on the control logic code to obtain compliance verification results and security verification results respectively, ensuring that the code is safe and secure. It achieves simultaneous compliance and safety. When either compliance or safety verification fails, a structured correction prompt is obtained. The control logic code is then corrected based on this prompt, ensuring that the correction process does not disrupt verified and functionally correct logic within the code. This significantly improves iteration efficiency and correction accuracy. The steps for static compliance and dynamic safety verification of the control logic code are then returned. When both compliance and safety verification succeed, a safety verification metadata report and the control logic code are output. This solution improves the engineering development efficiency of industrial control logic and reduces error costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram of the overall architecture for industrial control logic generation and security assurance based on a large language model and closed-loop verification provided in this embodiment of the invention. Figure 2 This is a flowchart of the industrial control logic generation and security assurance method based on large language model and closed-loop verification provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the processing procedure of the industrial control logic generation and security assurance method based on large language model and closed-loop verification provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this invention; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this invention as detailed in the appended claims.

[0019] It should be noted that although functional modules are divided in the system diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first / S100" and "second / S200" in the specification, claims, and the foregoing drawings may be used herein to describe various concepts, but unless specifically stated otherwise, these concepts are not limited by these terms. These terms are used only to distinguish one concept from another. For example, first information may also be referred to as second information without departing from the scope of the embodiments of the invention, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" or "when" as used herein may be interpreted as "when," "in response to a determination," or "in the event of a determination."

[0020] The terms “at least one,” “multiple,” “each,” “any,” etc., used in this invention, “at least one” includes one, two, or more than two; “multiple” includes two or more than two; “each” refers to each of the corresponding multiple; and “any” refers to any one of the multiple.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0022] Before providing a detailed description of the embodiments of the present invention, some of the nouns and terms involved in the embodiments of the present invention will be explained first. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations.

[0023] A Programmable Logic Controller (PLC) is a digital computing controller with a microprocessor used for automation control. It can load control instructions into memory for storage and execution at any time.

[0024] The JMP instruction is the core instruction in assembly language for implementing unconditional jumps. It achieves program jumps by modifying the instruction pointer (IP) or simultaneously modifying the code segment register (CS) and the instruction pointer (IP).

[0025] Intermediate representation (IR) is an abstract representation generated by a compiler or interpreter during source code processing, existing between the source language and the target language (such as machine code or bytecode). It serves as a bridge between the "front end" (source code parsing) and the "back end" (code optimization and target code generation) in the compilation process, primarily used to simplify code analysis, optimization, and cross-platform target code generation.

[0026] Large Language Models (LLMs), also known as large-scale language models, are artificial intelligence models designed to understand and generate human language. They are trained on large amounts of text data and can perform a wide range of tasks, including text summarization, translation, sentiment analysis, and more.

[0027] Industrial Control Systems (ICS), as the core support of modern industry, encompass various types of control systems, including Programmable Logic Controllers (PLCs). PLCs are the cornerstone of modern industrial control systems, widely used in process industries, critical infrastructure, transportation, and intelligent manufacturing—fields with extremely high reliability requirements. However, traditional PLC software development models suffer from serious efficiency and quality issues. At the development front end, engineers must manually and rigorously translate highly unstructured, even ambiguous, natural language requirements documents (Control Narratives) or process descriptions from process or demand departments into control logic conforming to IEC standards through analysis and understanding. This translation process from natural language to standardized code is extremely time-consuming and labor-intensive, and highly susceptible to human error due to engineers' oversight of specifications and logical details. This significantly prolongs subsequent debugging and verification cycles, severely restricting the rapid iteration of industrial software and its responsiveness to complex process changes.

[0028] Currently, there are intelligent generation technologies, represented by the Spec2Control workflow or agent architectures based on tool-enhanced LLMs. Their core purpose is to solve the efficiency problem of industrial programming. Therefore, their main drawback lies in the inherent uncontrollability of the generated control logic in terms of industrial-grade security, and the superficial and limited nature of their integrated verification mechanisms. These existing solutions essentially treat LLMs as code translators rather than security assurance tools, resulting in inherent security risks in the generated logic. There are also independent verification technologies, represented by the PyLC / Pynguin translation testing framework, StructuredFuzzer, and PLC-VBS scanners. Their main drawback is that, as independent and powerful tools, they are completely decoupled from the code generation process, exhibiting significant lag and unidirectionality, and carrying the risk of cross-platform semantic loss.

[0029] In view of this, this invention provides a method and related equipment for industrial control logic generation and security assurance based on a large language model and closed-loop verification. The system device of this solution, namely the "Industrial Control Logic Generation and Security Assurance System," consists of four core modules and two key interfaces, such as... Figure 1 As shown, the system employs an input optimizer (M1), an LLM core generator (M2), a closed-loop verifier (M3), a structured feedback generator (M4), a PLC simulation runtime environment (RTE) interface, and a code output and deployment interface. The closed-loop verifier (M3) integrates static compliance checks and customized deep dynamic safety verification, and utilizes the PLC simulation runtime environment (RTE) interface to provide a high-fidelity, controllable virtual PLC runtime environment for dynamic safety testing.

[0030] The system operates based on an LLM intelligent agent architecture and utilizes a PLC simulation runtime environment (RTE) for dynamic verification, such as... Figure 1As shown, the user-input Natural Language (NL) control requirements are converted into a high-precision JSON intermediate representation (IR) by M1, and then converted into PLC control logic code by M2. Utilizing the precise input of M1 and the efficient generation of the LLM significantly shortens the initial generation time. Next, the PLC control logic code undergoes dual verification (compliance verification and security verification) by M3. If verification fails, M3 passes the original error information to M4, which converts it into structured correction instructions. These instructions are then fed back to M2 via a feedback channel to drive iterative correction. Only after M3's verification passes is the code output through M5. This system method forms a complete closed loop of "natural language requirements - structured IR - efficient generation - deep security verification - structured feedback correction - secure code output" through the M1, M2, M3, M4, PLC simulation runtime environment (RTE) interface and code output and deployment interface. It organically integrates the efficient generation capability of LLM, customized deep industrial security detection technology and automated semantic feedback mechanism, and realizes the complete integration of the generation and verification process in the existing technology. It achieves seamless and automated delivery from unstructured requirements to verified security control logic, ensuring the high efficiency and high security of the final output code, thereby improving the engineering development efficiency of industrial control logic and reducing error costs.

[0031] Figure 2 This is an optional flowchart of an industrial control logic generation and security assurance method based on a large language model and closed-loop verification provided in an embodiment of the present invention. Figure 2 The method may include, but is not limited to, steps S100 to S500: Step S100: Perform a first transformation on the input data to obtain a structured intermediate representation; Step S200: Perform a second transformation on the intermediate representation to obtain the control logic code; Step S300: Perform static compliance verification and dynamic security verification on the control logic code to obtain compliance verification results and security verification results respectively; Step S400: When the compliance verification result is verification failure or the security verification result is verification failure, obtain the structured correction prompt, correct the control logic code according to the structured correction prompt, and return to the steps of performing static compliance verification and dynamic security verification on the control logic code. Step S500: When the compliance verification result is successful and the security verification result is successful, output the security verification metadata report and control logic code.

[0032] In step S100 of some embodiments, the input optimizer, as the starting point of the automated generation process, can solve the long-standing problem of ambiguous and unstructured requirements in the field of industrial control. The input optimizer efficiently and accurately transforms unstructured, and even ambiguous, control requirement documents input by users in natural language into an intermediate representation, typically in strict JSON format, so that the subsequent LLM core generator can accurately understand and operate on them.

[0033] In some embodiments, step S100 may include, but is not limited to, steps S110 to S130: Step S110: Receive the input natural language text to obtain input data; Step S120: Through a pre-trained domain model, the input data is analyzed at multiple levels to obtain key entities and logical relationships; Step S130: Perform a first transformation on the key entities and logical relationships to obtain a structured intermediate representation in JSON format.

[0034] In step S110 of some embodiments, the user inputs control requirements in the form of natural language. The input optimizer receives the natural language input by the user and uses it as input data to provide a data basis for subsequent transformation.

[0035] In step S120 of some embodiments, the input optimizer employs domain knowledge graphs and deep semantic parsing techniques. The input optimizer first performs multi-level parsing of the input data using a pre-trained domain model optimized for the industrial control domain. This domain model can accurately identify key entities (such as sensors, actuators, valves, pumps, and control variables) and their data types and hardware addresses in the input data, and extract complex control relationships and logic (such as interlocking logic, sequential timing control, exception handling procedures, PID control loops, etc.).

[0036] In step S130 of some embodiments, the input optimizer rigorously maps these extracted key entities and logical relationships into a structured JSON-formatted intermediate representation (IR). This IR contains all necessary constraints and information, including: a Logic_Type field specifying the overall control flow (e.g., "interlocked logic," "multi-step timing control"); a list of Input_Variables fields detailing all input signals (including variable names, data types, I / O addresses, or memory addresses); and a list of Output_Actions fields detailing all output actions and desired states (including actuator addresses, desired values, delay parameters, etc.).

[0037] It is important to note that the input optimizer forcibly extracts and encodes the Safety_Constraints field (e.g., "temperature must not exceed 80°C" and "pressure must be between 1.5 bar and 2.0 bar") in the early stages. This ensures that safety requirements are clearly defined and structured from the control requirements input stage, providing the primary safety objective and verification criteria for the subsequent deep dynamic safety verification of the closed-loop validator, thus guaranteeing the security of the generated code from the source.

[0038] In step S200 of some embodiments, the LLM core generator, the central intelligent engine of the system, automates the conversion from the abstract, structured intermediate representation (IR) provided by the input optimizer to industrial-grade, deployable PLC control logic code. One of the core functions of the LLM core generator is high-fidelity code generation. Based on the JSON-formatted IR provided by the input optimizer, it generates PLC control logic fully compliant with the IEC 61131-3 international standard and outputs it in PLCOpen XML format. The use of a universal data exchange standard format ensures that the generated logic can be smoothly imported and compiled in the engineering software of different mainstream PLC manufacturers. The core generated logic mainly focuses on structured text (ST), while also supporting the mapping of simple logic to ladder diagrams (LD) or function block diagrams (FBD) in PLCOpen XML representation.

[0039] In some embodiments, step S200 may include, but is not limited to, steps S210 to S260: Step S210: Fine-tune the initial basic large model using data from the industrial control field to obtain the target basic large model; Step S220: Input the intermediate representation into the target basic large model, and obtain the program code structure based on the logical type field in the intermediate representation; Step S230: Generate the corresponding input variable definition within the program code structure based on the input variable fields in the intermediate representation; Step S240: Generate the corresponding output action definition within the program code structure based on the output action field in the intermediate representation; Step S250: Generate basic execution logic based on the input variable definition and output action definition; Step S260: The security constraint field in the intermediate representation is used as the highest priority interlocking logic or exception handling code and embedded into the critical path of the basic execution logic to obtain the control logic code.

[0040] In step S210 of some embodiments, the LLM core generator employs a base model that has been fine-tuned with data from the industrial control field to ensure that the target base model obtained after fine-tuning has a deep understanding of industrial terminology, control logic patterns, and IEC 61131-3 syntax rules.

[0041] In step S220 of some embodiments, the input of the LLM core generator adopts a highly structured Prompting mechanism, with the intermediate representation as the main generation instruction. The LLM core generator strictly determines the program code structure based on the Logic_Type field in the intermediate representation.

[0042] In step S230 of some embodiments, the LLM core generator uses the intermediate representation as the main generation instruction. Based on the input variable fields in the intermediate representation, it generates input variable definitions within the program code structure, realizing the mapping declaration from physical input signals to internal program variables. For example, the input variable fields (such as {"name":"TempSensor1", "type":"REAL", "address":"IW100"}) describe the semantics, data type, and physical address of each input point. Based on these input variable fields, standardized variable declaration statements are generated at appropriate locations in the program code structure (such as the global variable table or the input interface area of ​​a function block). Simultaneously, corresponding IO mapping logic is generated, i.e., based on the address information, code is generated to periodically read physical input module data (such as IW100) into the program variable (such as TempSensor1).

[0043] In step S240 of some embodiments, the LLM core generator uses the intermediate representation as the main generation instruction. Based on the output action field in the intermediate representation, it generates output action definitions within the program code structure, realizing the mapping declaration from internal program commands to physical output points. For example, the output action field (e.g., {"name":"HeaterRelay", "type":"BOOL", "address":"QW0.0"}) describes the semantics, data type, and physical address of each output point. Based on this output action field, the declaration of output variables is generated within the program code structure. Simultaneously, corresponding IO mapping logic is generated, i.e., code that writes the result of internal logical operations (e.g., the Boolean variable HeaterRelay) to the physical output address (e.g., QW0.0).

[0044] In step S250 of some embodiments, a specific control algorithm is instantiated within the program code structure based on the declared input variables and output actions to form the basic execution logic.

[0045] In step S260 of some embodiments, to achieve safety-by-design, the LLM core generator, during the generation of control logic code, forces the safety constraint (Safety_Constraints) field (e.g., upper and lower temperature limits) extracted from the intermediate representation to be used as the highest priority interlocking logic or exception handling code, and embeds it into the critical path of the basic execution logic to generate PLC control logic code. This ensures at the architectural level that the safety logic cannot be bypassed by the basic execution logic. Here, the critical path refers to the signal chain that directly affects the action of the final actuator (such as a motor or valve). Embedding into the critical path means that the safety logic is directly connected to the necessary path from control decision to physical output. For example, taking reactor temperature control as an example, the safety constraint field is reactor temperature ≤150℃; the basic execution logic is automatic heating control according to the recipe, with a target temperature of 140℃. Embedding the safety constraint field as the highest priority interlocking logic or exception handling code into the critical path of the basic execution logic results in the following control logic code: / / Basic execution logic If in automatic mode and (actual temperature < 140.0), then Regular heating command := true; else Regular heating command := false; endif / / Forced embedded security interlock logic Final heating command := Regular heating command AND (Actual temperature <= 150.0); / / Or force-embedded exception handling code If the actual temperature is >150.0, then... Final heating command := false; Trigger an emergency alarm; else Final heating command := Regular heating command; endif Heating valve output := final heating command; / / Mapped to physical output In the example of reactor temperature control, the goal of the basic execution logic is to precisely stabilize the temperature at the ideal operating point of 140°C to complete production in an optimal manner. By embedding safety constraints into the critical path of the basic execution logic, a safety logic is formed to prevent hazards (such as equipment damage, leakage, or explosion). Once the temperature exceeds the safety constraint of 150°C, the safety logic will immediately cut off heating, thus prioritizing safety.

[0046] In step S300 of some embodiments, a closed-loop verifier is used, which integrates two parallel verification sub-modules: static compliance verification and customized deep dynamic security verification, to ensure that the code is qualified in both functionality and security.

[0047] In some embodiments, step S300 may include, but is not limited to, steps S310 to S320: Step S310: Perform format verification and semantic analysis on the control logic code to obtain compliance verification results; Step S320: Perform logic flow tampering detection and variable persistence vulnerability scanning on the control logic code to obtain security verification results.

[0048] In step S310 of some embodiments, in the static compliance verification submodule of the closed-loop validator, multi-level compliance verification is performed based on PLCOpen XML structured parsing to conduct basic syntax, structure, and functional quality checks on the control logic code. For example, the multi-level compliance verification includes strict XML Schema verification to ensure that the file structure output by the closed-loop validator conforms to industry standards and can be successfully parsed and imported by mainstream engineering software (such as TIA Portal or Studio 5000). The multi-level compliance verification also includes in-depth semantic analysis to check whether the generated control logic meets the basic functional requirements specified in the intermediate representation of the input optimizer, such as: whether there are I / O address conflicts or out-of-bounds accesses to ensure no illegal operation of critical system memory; whether data type definitions and usage strictly match to avoid potential runtime errors; and whether there are low-level functional logic errors such as multiple output coils or unused variables. If the XML Schema verification of the control logic code fails, or if the control logic code does not meet the basic functional requirements specified in the intermediate representation of the input optimizer, a compliance verification result indicating verification failure is output. Conversely, if the XML Schema validation of the control logic code is successful, and the control logic code meets the basic functional requirements specified in the intermediate representation of the input optimizer, then the validation result of the successful verification will be output.

[0049] By performing format verification and semantic analysis on the control logic code, all compliance defects that may lead to compilation failure or functional uncertainty can be systematically eliminated.

[0050] In step S320 of some embodiments, the dynamic security verification submodule of the closed-loop verifier performs customized and dynamic detection of JMP logic flow tampering and critical variable persistence vulnerabilities that may lead to serious physical consequences in industrial control logic, thereby ensuring that the LLM-generated code has advanced security resistance capabilities before deployment.

[0051] In some embodiments, step S320 may include, but is not limited to, steps S3211 to S3215: Step S3211: Import the control logic code into the simulation runtime environment and dynamically obtain the scan cycle; Step S3212: Predict the baseline period threshold and the maximum safe period threshold; Step S3213: Compare the scan cycle with the baseline cycle threshold and the maximum safe cycle threshold; Step S3214: When the scanning period is greater than the maximum security period threshold, a malicious loop vulnerability exists, and the security verification result is output as verification failure. Step S3215: When the scanning period is less than the baseline period threshold, there is abnormal behavior, and the security verification result is output as verification failure.

[0052] In step S3211 of some embodiments, for logic flow tampering verification, the generated logic control code is imported into a high-fidelity PLC simulation runtime environment (RTE) for execution. This environment simulates real CPU scheduling, I / O read / write, and task loops. Simultaneously, the closed-loop verifier monitors the PTC's scan time in real time with high precision. .

[0053] In step S3212 of some embodiments, a baseline cycle threshold can be obtained by analyzing program logic, performing performance analysis in a clean environment, or determining the typical expected scan cycle of the program based on design specifications. The maximum safe cycle threshold can be obtained by determining the worst-case scan cycle upper limit that the system can tolerate without causing control function failure or safety risks through safety constraints such as the physical time constant of the control process and communication timeout limits.

[0054] In step S3213 of some embodiments, when running a preset structured fuzz test input sequence for a JMP instruction or loop structure, the loop closure verifier will use the scan cycle acquired in real time. Compared with the pre-determined reference period threshold and maximum safety threshold Compare them.

[0055] In step S3214 of some embodiments, if the scan cycle Significantly greater than the maximum safety threshold If the error occurs, it is determined that there is an uncontrolled malicious loop vulnerability, which may cause the PLC control to malfunction. Therefore, a security verification result of verification failure is output.

[0056] In step S3215 of some embodiments, if the scan cycle Significantly below the baseline period threshold If the percentage is below 50%, it is determined that there is an abnormal behavior where the JMP instruction skips the critical security logic. This indicates that the logic flow has been tampered with, so a security verification result of verification failure is output.

[0057] In some embodiments, step S320 may also include, but is not limited to, steps S3221 to S3225: Step S3221: Import the control logic code into the simulation runtime environment and identify the data block variables of the key physical outputs; Step S3222: Obtain the memory address corresponding to the data block variable; Step S3223: Through the industrial communication protocol interface, simulate an external malicious attacker in the current scanning cycle and write malicious values ​​to the memory address; Step S3224: Read the stored value of the memory address in the next scan cycle; Step S3225: When the stored value is malicious or close to a malicious value, a variable persistence vulnerability exists, and the security verification result is output as verification failure.

[0058] In steps S3221 to S3222 of some embodiments, the variable persistence vulnerability scan focuses on detecting the resistance of the control logic to external malicious interference. For the variable persistence vulnerability scan, the generated logic control code is imported into a high-fidelity PLC simulation runtime environment (RTE) for execution. During code execution, the closed-loop verifier first identifies the variable block (VB) variables and their corresponding memory addresses for key physical outputs (such as safety valve status and emergency stop signals). .

[0059] In step S3223 of some embodiments, industrial communication protocol interfaces such as S7Comm (Siemens communication protocol) are used to simulate an external malicious attacker sending data to a memory address. Write a malicious value .

[0060] In step S3224 of some embodiments, within the next PLC scan cycle after the malicious value is written to the memory address (or a preset very short time) During the cycle, the stored value at the memory address is read again to check whether the control logic can overwrite and correct the written malicious value in a timely manner.

[0061] In step S3225 of some embodiments, if within the next PLC scan cycle after the malicious value is written to the memory address (or a preset very short time) If the memory address value read during the period is still malicious or close to malicious, it indicates that the control logic has failed to reset or correct the variable to a safe state. Therefore, it is determined that the control logic code has a variable persistence vulnerability and is highly susceptible to external network attacks. Thus, a security verification result of verification failure is output.

[0062] In some embodiments, if the scanning period is less than or equal to the maximum security threshold, the scanning period is greater than or equal to the baseline period threshold, and in the variable persistence vulnerability scan, it is determined that the control logic code does not have a variable persistence vulnerability, then a successful security verification result is output.

[0063] In step S400 of some embodiments, a structured feedback generator is used to transform the raw, complex, and highly technical verification report generated by the closed-loop verifier into structured correction prompts that can be directly understood and precisely operated by the LLM core generator. This transformation serves as a bridge connecting security verification results and intelligent code generation, completely breaking through the bottleneck of relying on manual analysis in the traditional "open-loop audit" model and realizing an automated self-correcting closed loop.

[0064] In some embodiments, step S400 may include, but is not limited to, steps S410 to S430: Step S410: When the compliance verification result is verification failure or the security verification result is verification failure, generate a verification report; Step S420: Parse the verification report to obtain structured correction suggestions; Step S430: Based on the structured correction prompts, make partial modifications to the control logic code to obtain the corrected control logic code; The structured correction prompts include safety features, fault location information, and correction requirements.

[0065] In step S410 of some embodiments, when the compliance verification result is a verification failure or the security verification result is a verification failure, the closed-loop verifier will generate an original verification report containing a specific XML path and an error description.

[0066] In step S420 of some embodiments, the original verification report is parsed by a structured feedback generator and transformed into structured correction prompts. Exemplarily, the structured feedback generator receives the original verification report from the closed-loop verifier. The original error data stream in this report may include, but is not limited to, low-level error signals such as "Scanning time exceeded at 450ms, associated with Ladder Rung 15" or "Variable 'Safety_Valve_State' tampered successfully at address DB1.DBX1.0". The structured feedback generator uses a small semantic model or a pre-defined mapping rule base for industrial security vulnerabilities to parse and abstract these original error data streams, thereby elevating low-level error signals to high-level semantic correction instructions.

[0067] In some embodiments, the output of the structured feedback generator is a structured correction prompt text (such as JSON format) with explicit and strict constraints, containing at least the following three core dimensions: First, Error_Type, which specifies the safety nature of the error, such as "LogicFlow_JMP_Vulnerability" or "VB_Persistence_Failure"; second, Location, which provides precise fault location information, such as "Ladder_Rung: 15" or "XML_Line:320"; and most importantly, Correction_Constraint, which is a strict correction requirement, such as "Must add InputCondition to JMP or eliminate the Loop structure. Ensure 'Safety_Valve_State' is reset or explicitly controlled at the start of every cycle."

[0068] In step S430 of some embodiments, the generated structured correction hints are efficiently fed back to the LLM core generator via the feedback channel. The LLM core generator strictly modifies specific locations of the control logic code according to the semantic correction instructions of the structured feedback generator, thereby driving a new round of control logic code generation and verification until the control logic code completely passes all functional and deep security checks of the closed-loop verifier.

[0069] For example, when the system enters the iterative correction phase, the LLM core generator uses the structured correction hints (containing precise information such as Error_Type, Location, and Correction_Constraint) returned by the structured feedback generator as new context input. The LLM core generator is guided to switch from "free generation mode" to "constrained correction mode," rather than simply rewriting code. By utilizing the precise error locations provided by the structured feedback generator, it performs minimal, targeted modifications only to the erroneous or vulnerable code blocks, ensuring the accuracy of the correction and adhering to the principle of minimal modification. Through constrained correction mode, it ensures that the correction process does not break verified, functionally correct logic in the code (maintaining code stability), greatly improving iteration efficiency and correction accuracy, and achieving an automated self-correction closed loop.

[0070] In step S500 of some embodiments, when the compliance verification result is successful and the security verification result is successful, that is, when the closed-loop verifier's dual judgment of the control logic code is completely qualified, without functional errors and passes the deep dynamic security detection, the control logic code can be provided to the external configuration tool or enter the actual deployment process.

[0071] For example, when both compliance and security verification results are successful, the code output and deployment interface receives a successful verification signal from the closed-loop verifier and the final control logic code. This final control logic code is in the widely recognized PLCOpen XML standard format, ensuring platform independence and interoperability with mainstream industrial configuration software (such as Siemens TIA Portal, Rockwell Studio 5000, etc.). The PLCOpen XML format control logic code file is then packaged and delivered seamlessly from natural language requirements to verified, secure code via the code output and deployment interface (e.g., RESTful API or file export), achieving "NL-to-Verified-Code-to-Deployment".

[0072] In some embodiments, to ensure the highest level of security compliance and traceability, a security validation metadata report is embedded or included when the control logic code is output in the code output and deployment interface. This metadata may include, but is not limited to, the hash value of the code that finally passes validation, a summary of the results of all functionalities and security tests performed by the closed-loop validator, and key security parameters (e.g., those used in dynamic security validation). (Security threshold). By attaching this "security certification certificate," the code output and deployment interface not only completes the code delivery but also ensures the traceability and secure trust chain of the deliverables during compliance audits and subsequent maintenance.

[0073] refer to Figure 3 , Figure 3 This demonstrates a complete closed-loop process from natural language input to final code delivery. The process begins with "input natural language control requirements," which are then processed by the "input optimizer" to generate input logic (IR). The IR then enters the "LLM core generator" to produce PLCopen XML code. The code subsequently enters the "closed-loop validator" for double verification. If verification fails, the process enters the "structured feedback generator" to generate correction instructions and loops back to the "LLM core generator" for iteration. If verification succeeds, the process proceeds to "output and deployment" and terminates.

[0074] This invention also provides an industrial control logic generation and security assurance system based on a large language model and closed-loop verification, which can implement the above-mentioned industrial control logic generation and security assurance method based on a large language model and closed-loop verification. The system includes: The optimization module is used to perform a first transformation on the input data to obtain a structured intermediate representation; The generation module is used to perform a second transformation on the intermediate representation to obtain the control logic code; The verification module is used to perform static compliance verification and dynamic security verification on the control logic code, and obtain compliance verification results and security verification results respectively. The structured feedback generation module is used to obtain structured correction prompts when the compliance verification result is a verification failure or the security verification result is a verification failure. It then corrects the control logic code according to the structured correction prompts and returns the steps for performing static compliance verification and dynamic security verification on the control logic code. The output module is used to output a security verification metadata report and control logic code when the compliance verification result is successful and the security verification result is successful.

[0075] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0076] This invention also provides an electronic device, which includes a processor and a memory. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including a tablet computer, an in-vehicle computer, or similar device.

[0077] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0078] refer to Figure 4 , Figure 4 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention. The memory 602 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called and executed by the processor 601. The input / output interface 603 is used to implement information input and output; The communication interface 604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 605 transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604); The processor 601, memory 602, input / output interface 603, and communication interface 604 are connected to each other within the device via bus 605.

[0079] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0080] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0081] This invention also provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions to cause the computer device to perform the aforementioned method.

[0082] In summary, the industrial control logic generation and security assurance method and related equipment based on large language models and closed-loop verification of the present invention have the following advantages: 1. This invention presents an LLM core generator with dual core functions: high-fidelity code generation and precise closed-loop correction. The LLM core generator can achieve high-fidelity mapping from JSON IR structures to PLCOpen XML tags and instruction sequences. It can identify variable types (such as BOOL, INT, REAL) in the IR and accurately map them to the XML. <datatype>Tags are used to convert the control logic in IR into PLCOpen XML. <pou>Text blocks under (Program OrganizationUnit) <st>or graphic elements <ld>This ensures that the generated instruction sequence conforms to the PLC's scan cycle execution semantics. When the system enters the iterative correction phase, the LLM core generator uses the structured correction prompt returned by the structured feedback generator as new context input, performing minimal and targeted modifications to the erroneous or defective code blocks, greatly improving iteration efficiency and correction accuracy.

[0083] 2. Existing technologies (such as PyLC / Pynguin) are limited to functional correctness in their testing objectives. This invention employs a deep dynamic security verification submodule within a closed-loop verifier, custom-integrating logic flow tampering detection (by monitoring the scan cycle of the PLC simulation RTE) and variable persistence vulnerability scanning (by simulating malicious writing of critical data blocks VB using the S7Comm protocol). This proactive and dynamic detection of critical security vulnerabilities in industrial control logic, such as JMP logic skipping, malicious loops, and VB tampering, is incorporated into the generation workflow, ensuring that the final code possesses advanced security resistance capabilities before deployment.

[0084] 3. Existing verification tools are open-loop (one-way output reports), and corrections rely on manual analysis and intervention by engineers, which is inefficient. This invention employs a structured feedback generator to transform the complex, raw security verification error data generated by the closed-loop verifier into a structured correction prompt that can be directly understood and manipulated by the LLM core generator. This drives the model to perform automated, high-precision iterative corrections of the code, eliminating the manual analysis step and achieving an end-to-end automated delivery closed loop from "requirements" to "security code." It constructs an efficient, non-manually-intervention-free automated closed loop of "generation-deep verification-structured correction."

[0085] 4. In existing technologies, manual programming is time-consuming and error-prone, and error detection is usually delayed until a separate verification stage, resulting in high repair costs. This invention employs an input optimizer to convert natural language into a high-precision JSON intermediate representation, significantly shortening the initial generation time. Simultaneously, by moving the verification module of the closed-loop validator forward and implementing automated correction, it ensures that most functional and security defects are resolved in the early stages of code generation, thereby minimizing the cost of error detection and repair.

[0086] 5. Existing translation testing solutions (such as PyLC / Pynguin) suffer from potential semantic equivalence deviations when translating PLC's strong real-time logic into high-level languages. This invention directly utilizes the PLC simulation RTE interface and industrial communication protocols (such as S7Comm) for verification, rather than relying on cross-language translation. This ensures high-fidelity industrial-grade verification results and avoids semantic loss and subsequent debugging difficulties caused by translation.

[0087] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0088] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0089] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0091] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0092] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0093] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0094] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0095] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.< / ld> < / st> < / pou> < / datatype>

Claims

1. A method for generating and ensuring the security of industrial control logic based on a large language model and closed-loop verification, characterized in that, Includes the following steps: The input data undergoes a first transformation to obtain a structured intermediate representation; The intermediate representation is then transformed to obtain the control logic code; Static compliance verification and dynamic security verification are performed on the control logic code to obtain compliance verification results and security verification results, respectively. When the compliance verification result is a verification failure or the security verification result is a verification failure, a structured correction prompt is obtained, the control logic code is corrected according to the structured correction prompt, and the steps of performing static compliance verification and dynamic security verification on the control logic code are returned. When both the compliance verification result and the security verification result are successful, output a security verification metadata report and the control logic code.

2. The method according to claim 1, characterized in that, The first transformation of the input data to obtain a structured intermediate representation includes the following steps: Receive input natural language text and obtain input data; By using a pre-trained domain model, the input data is analyzed at multiple levels to obtain key entities and logical relationships; The key entities and logical relationships are first transformed to obtain the intermediate representation in structured JSON format.

3. The method according to claim 1, characterized in that, The second transformation of the intermediate representation to obtain the control logic code includes the following steps: By using data from the industrial control field, the initial basic model is fine-tuned to obtain the target basic model; The intermediate representation is input into the target basic large model, and the program code structure is obtained based on the logical type field in the intermediate representation; Based on the input variable fields in the intermediate representation, generate the corresponding input variable definitions within the program code structure; Based on the output action field in the intermediate representation, generate the corresponding output action definition within the program code structure; Based on the defined input variables and the defined output actions, basic execution logic is generated; The security constraint field in the intermediate representation is used as the highest priority interlocking logic or exception handling code and embedded into the critical path of the basic execution logic to obtain the control logic code.

4. The method according to claim 1, characterized in that, The process of performing static compliance verification and dynamic security verification on the control logic code to obtain compliance verification results and security verification results respectively includes the following steps: The control logic code is subjected to format verification and semantic analysis to obtain the compliance verification result; The control logic code is subjected to logic flow tampering detection and variable persistence vulnerability scanning to obtain the security verification results.

5. The method according to claim 4, characterized in that, The process of performing logic flow tampering detection and variable persistence vulnerability scanning on the control logic code to obtain the security verification result includes the following steps: Import the control logic code into the simulation runtime environment to dynamically obtain the scan cycle; Predict the baseline period threshold and the maximum safe period threshold; The scan period is compared with the baseline period threshold and the maximum safe period threshold; When the scanning period is greater than the maximum security period threshold, a malicious loop vulnerability exists, and the security verification result is output as verification failure. When the scanning period is less than the baseline period threshold, abnormal behavior exists, and the security verification result is output as verification failure.

6. The method according to claim 4, characterized in that, The method for performing logic flow tampering detection and variable persistence vulnerability scanning on the control logic code to obtain the security verification result further includes the following steps: Import the control logic code into the simulation runtime environment and identify the key physical output data block variables; Obtain the memory address corresponding to the data block variable; Through the industrial communication protocol interface, an external malicious attacker is simulated during the current scanning cycle to write malicious values ​​to the memory address; The stored value at the memory address is read in the next scan cycle; When the stored value is the malicious value or the stored value is close to the malicious value, a variable persistence vulnerability exists, and the security verification result is output as verification failure.

7. The method according to claim 1, characterized in that, When the compliance verification result is a verification failure or the security verification result is a verification failure, a structured correction prompt is obtained, and the control logic code is corrected according to the structured correction prompt, including the following steps: A verification report is generated when the compliance verification result is a verification failure or the security verification result is a verification failure. The verification report is parsed to obtain the structured correction prompts; Based on the structured correction prompts, the control logic code is partially modified to obtain the corrected control logic code; The structured correction prompt includes safety features, fault location information, and correction requirements.

8. An industrial control logic generation and security assurance system based on large language models and closed-loop verification, characterized in that, include: The optimization module is used to perform a first transformation on the input data to obtain a structured intermediate representation; A generation module is used to perform a second transformation on the intermediate representation to obtain control logic code; The verification module is used to perform static compliance verification and dynamic security verification on the control logic code, and obtain compliance verification results and security verification results respectively. The structured feedback generation module is used to obtain a structured correction prompt when the compliance verification result is a verification failure or the security verification result is a verification failure, correct the control logic code according to the structured correction prompt, and return to the steps of performing static compliance verification and dynamic security verification on the control logic code. The output module is used to output a security verification metadata report and the control logic code when the compliance verification result is successful and the security verification result is successful.

9. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement the method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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