Planarization resistive element and method of manufacturing the same

Abstract

The present application provides a kind of flattening resistance element and its manufacturing method, it includes a substrate, a resistance layer and an electrode layer, the present application solves the problem of impedance increase and product characteristic anomaly caused by improper joint of the interface of electrode layer and resistance layer, including after the completion of electrode layer process, by using laser or grinding to eliminate the height difference of interface and process the structure of electrode layer profile discontinuity.

Description

Technical Field

[0001] This invention relates to a flattened resistor element and its manufacturing method, and particularly to a flattened resistor element and its manufacturing method that maintains a stable impedance under long-term energization. Background Technology

[0002] Sputtering is a physical vapor deposition technique. In the process of thin film resistors, sputtering uses electricity to deposit sputtered target material atoms or molecules onto semiconductor wafers, glass, or ceramics through a metal mask to form a thin film of a specific shape.

[0003] The sputtering process generates a large amount of heat, causing the mask to expand due to exposure to the heat source. This expansion causes the pattern on the mask to deviate from its relative position on the substrate. This pattern misalignment can lead to oversputtering of the target material during sputtering, affecting dimensional stability.

[0004] Due to the characteristics of traditional printing technology, uneven thickness and excessive height differences occur in the contact area between the electrode layer and the resistive layer, which hinders electron migration and further increases impedance.

[0005] In addition, the printing technology can also cause excess material to be splashed at the edges of the printed layer, resulting in discontinuities in the electrode layer contour structure, uneven current distribution, and complex current paths.

[0006] The three situations described above can cause the performance of the resistive element to become unstable, thereby affecting the consistency and reliability of the product. Furthermore, they can cause localized overheating, further impacting the reliability of the element and potentially leading to a decrease in the thermal stability of the resistor. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a planarized resistive element and its manufacturing method, resolving the issue of uneven height differences in the contact area between the electrode layer and the resistive layer of existing resistors. This unevenness hinders electron migration and further increases current impedance. In such cases, the performance of the resistive element becomes unstable, affecting product consistency and reliability. Furthermore, it can cause localized overheating, further impacting element reliability and potentially leading to a decrease in the resistor's thermal stability.

[0008] This invention provides a method for manufacturing a planarized resistive element, comprising:

[0009] Forming a substrate;

[0010] Electrode layers are formed at both ends of the substrate;

[0011] The surface of the electrode layer is formed with a chamfered recess by laser or grinding;

[0012] A resistive layer is formed, covering the chamfered recess of the electrode layer; and

[0013] A protective layer is formed on the resistive layer.

[0014] Preferably, the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

[0015] Preferably, the chamfered concave platform has a chamfer angle of 40°-120°.

[0016] Preferably, the average roughness of the centerline of the chamfered concave surface is 0.1 nm-10 μm.

[0017] Furthermore, the present invention also provides a flattened resistive element comprising:

[0018] substrate;

[0019] Electrode layers are disposed at both ends of the substrate, and the electrode layers have chamfered recesses.

[0020] A resistive layer is disposed on the surface of the substrate, and the resistive layer is connected to the electrode layer; and

[0021] A protective layer is disposed on the resistive layer and exposes the electrode layer.

[0022] Preferably, the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

[0023] Preferably, the chamfered concave platform has a chamfer angle of 40°-120°.

[0024] Preferably, the average roughness of the centerline of the surface of the chamfered recess of the electrode layer is 0.1 nm-10 μm.

[0025] The electrode layer of the present invention is provided with a chamfered recess, which improves the flatness, thickness consistency and bonding stability of the contact surface between the electrode layer and the resistor layer. It solves the technical problems of uneven current distribution, complex current path, local overheating, and easy deformation and poor contact under long-term energization caused by the height difference of the junction surface and discontinuous electrode layer contour structure in existing resistors. This reduces the impedance change rate of the resistor element under long-term energization and improves the consistency, reliability and thermal stability of the product. Attached Figure Description

[0026] Figure 1 This is a top view of the planarized resistive element of the present invention.

[0027] Figures 2 to 5 This is a schematic diagram of the manufacturing process of the planarized resistive element of the present invention.

[0028] Figure 6 yes Figure 1A magnified view of area A in the image.

[0029] Figure 7 This is a flowchart of the manufacturing method of the planarized resistive element of the present invention.

[0030] Attached icon number

[0031] 1. Flattened resistor element;

[0032] 10 substrates;

[0033] 20 electrode layers;

[0034] 30 resistive layers;

[0035] 40 protective layers;

[0036] 50° chamfered concave platform;

[0037] 60 junction;

[0038] 70Ω resistor protrusion;

[0039] A. Border area;

[0040] D1 First segment difference;

[0041] D2 second segment difference;

[0042] Steps S01-S04;

[0043] θ is the tangent angle. Detailed Implementation

[0044] The following detailed descriptions of various embodiments of the present invention, accompanied by accompanying drawings, will facilitate a better understanding by the reader. In addition to these detailed descriptions, the present invention can be widely implemented in other embodiments. Any easy substitutions, modifications, or equivalent changes to the described embodiments should be understood to be included within the scope of the present invention, and the definition of the patent scope should be based on the claims. It should be noted that the drawings are for illustrative purposes only and do not represent the actual size or quantity of the components; some details may not be fully depicted for the sake of simplicity.

[0045] For the sake of simplicity, a rectangular resistor is used as an example, but it should be understood that it is used as an example and not to limit the invention. The flattened resistor element of the present invention can be implemented in any shape.

[0046] Please see Figures 1 to 6 As shown, Figure 1 This is a top view of the planarized resistive element of the present invention. Figures 2 to 5 This is a schematic diagram illustrating the manufacturing process of the planarized resistive element of the present invention. Figure 6 yes Figure 1 A magnified view of area A in the image.

[0047] The planarized resistive element 1 of the present invention comprises a substrate 10, an electrode layer 20, a resistive layer 30 and a protective layer 40.

[0048] Step S01, as follows Figure 2 As shown, a substrate 10 is provided, and electrode layers 20 are printed on both ends of the substrate 10 to form two electrodes.

[0049] Step S02, as follows Figure 3 As shown, the surface of the electrode layer 20 is repaired by laser or grinding to form a chamfered recess 50. The length of the chamfered recess 50 is less than or equal to half the length of the electrode layer, so that the highest point of the electrode layer remains unchanged, thereby preventing overspraying of material. The surface roughness Ra of the repaired electrode layer is less than 1 μm. The electrode layer is made of an alloy, and its composition may include metals such as titanium, copper, aluminum, nickel, gold, carbon, and silicon.

[0050] The chamfered recess 50 has a chamfered angle θ of 40°-120°, the distance between the chamfered recess 50 and the surface of the electrode layer 20 has a first step difference D1 of 0.1μm-20μm, the distance between the chamfered recess 50 and the surface of the substrate 10 has a second step difference D2 of 0.1μm-10μm, and the average roughness (Ra) of the centerline of the surface of the chamfered recess 50 is 0.1nm-10μm.

[0051] Step S03, as follows Figure 4 As shown, a sputtered resistive layer 30 is deposited on the substrate 10 and the electrode layer 20. The resistive layer 30 covers the substrate 10 and the chamfered recess 50 of the electrode layer 20. The thickness of the resistive layer 30 is less than or equal to the first step difference D1 of the chamfered recess 50, and the first step difference D1 is greater than the second step difference D2 of the chamfered recess 50. The resistive layer 30 contacts the side surface and top surface of the chamfered recess 50 to increase the contact surface area between the resistive layer 30 and the electrode layer 20, prevent oversputtering of the resistive layer 30, and ensure that the thickness of the contact area between the resistive layer 30 and the electrode layer 20 is consistent. This avoids uneven thickness, which can cause the resistive layer 30 to deform and warp easily due to heat when energized, resulting in excessive height difference in the contact area, which in turn hinders electron migration and increases impedance. The resistive layer is made of a sputtered alloy, which may be composed of metals such as titanium, copper, aluminum, nickel, gold, carbon, and silicon.

[0052] Step S04, as follows Figure 5 As shown, a protective layer 40 is printed on the resistive layer 30 and then cured. The total thickness of the protective layer 40 and the resistive layer 30 is greater than or equal to the first segment difference D1 of the chamfered recess 50. The material of the protective layer 40 can be epoxy resin or a mixture of epoxy resins.

[0053] Please see Figure 7 , Figure 7This is a flowchart of the manufacturing method of the planarized resistive element of the present invention.

[0054] Figure 7 Region A is the boundary area between the resistive layer 30 and the electrode layer 20. The resistive protrusion 70 on region A is a protrusion formed due to the obstruction of the chamfered recess 50 during the sputtering process, so that the resistive layer 30 and the electrode layer 20 are completely attached, maintaining the consistency of the outline of the electrode layer 20 and the resistive layer 30.

[0055] The printing, laser, grinding, sputtering and curing processes used in this invention can be performed using existing technologies to achieve the same effect. For the sake of brevity, this invention will not be described in detail.

[0056] [Example 1]: Impedance value detection

[0057] To test the effect of the flattened resistor element of the present invention, a conventional resistor lacking the technical features of the present invention was used as the control group, and the flattened resistor element of the present invention was used as the experimental group. The change in impedance value was tested at the initial energization (i.e., without changing any conditions). The experimental results are shown in Table 1. The flattened resistor element of the present invention can suppress the impedance change rate to 0.01%-1%.

[0058] Table 1:

[0059]

[0060] [Example 2]: Resistance value detection after prolonged energization

[0061] To test the effect of the flattened resistor element of the present invention, the present invention was used as the experimental group, and the existing resistor lacking the flattened resistor of the present invention was used as the control group. The change in resistance value was tested under a 1000-hour power-on life test. The experimental results are shown in Table 2. The flattened resistor element of the present invention can suppress the resistance change rate to 0.05%.

[0062] Table 2:

[0063]

[0064] As can be seen from the above experimental results, the flattened resistor element of the present invention can effectively reduce the instability of the resistance value. Its impedance change rate and resistance value change rate after 1000 hours of power-on are 0.01%-1% and 0.05%, respectively. Compared with the existing resistors, which are 98% and 10%, the resistance value stability is significantly improved. Therefore, it is proven that the present invention can prevent the resistance value from being unstable and maintain high resistance value accuracy and reliability under high temperature and long-term operation.

[0065] The electrode layer of the present invention is provided with a chamfered recess, which improves the flatness, thickness consistency and bonding stability of the contact surface between the electrode layer and the resistor layer. It solves the technical problems of uneven current distribution, complex current path, local overheating, and easy deformation and poor contact under long-term energization caused by the height difference of the junction surface and discontinuous electrode layer contour structure in existing resistors. This reduces the impedance change rate of the resistor element under long-term energization and improves the consistency, reliability and thermal stability of the product.

[0066] Therefore, the high-temperature resistant resistor element of the present invention effectively improves the temperature resistance capability, and the resistance value change is 2%-10% between 150℃ and 350℃, preventing the resistance value from drifting and maintaining the accuracy and reliability of the resistance value for a long time in high-temperature environments.

Claims

1. A method for manufacturing a flattened resistive element, characterized in that, Include: Forming a substrate; Electrode layers are formed at both ends of the substrate; A chamfered recess is formed on the surface of the electrode layer by laser or grinding; A resistive layer is formed and covers the chamfered platform of the electrode layer; as well as A protective layer is formed on the resistive layer.

2. The manufacturing method as described in claim 1, characterized in that, The length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

3. The manufacturing method as described in claim 1, characterized in that, The chamfered concave platform has a chamfer angle of 40°-120°.

4. The manufacturing method as described in claim 1, characterized in that, The average surface roughness of the centerline of the chamfered concave platform is 0.1 nm-10 μm.

5. A flattened resistive element, characterized in that, Include: substrate; Electrode layers are disposed at both ends of a substrate, and the electrode layers have chamfered recesses. A resistive layer is disposed on the surface of the substrate, and the resistive layer is connected to the electrode layer; and A protective layer is disposed on the resistive layer and exposes the electrode layer.

6. The flattening resistor element as described in claim 5, characterized in that, The length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

7. The flattening resistor element as described in claim 5, characterized in that, The chamfered concave platform has a chamfer angle of 40°-120°.

8. The flattening resistor element as described in claim 5, characterized in that, The average surface roughness of the centerline of the chamfered concave platform of the electrode layer is 0.1 nm-10 μm.

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