Optimization method, device, medium and product of sparse matrix vector multiplication algorithm
By adaptively selecting the optimal block shape and load balancing strategy, the sparse matrix vector multiplication algorithm is optimized, solving the problem of uneven utilization of sparse matrix computing resources and realizing efficient sparse matrix vector multiplication algorithm computation on GPU platform.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF SCI & TECH OF CHINA
- Filing Date
- 2026-03-16
- Publication Date
- 2026-06-16
AI Technical Summary
The sparse matrix-vector multiplication algorithm suffers from uneven utilization of computational resources on GPU platforms, resulting in performance limitations and making it difficult to achieve efficient computation.
By adaptively selecting the optimal block shape, rearranging the rows of sparse matrix data, and dynamically allocating computational tasks based on the number of non-zero elements, the algorithm for sparse matrix vector multiplication is optimized by adopting AtBSR format storage and load balancing strategies.
It achieves efficient and balanced computation of sparse matrix-vector multiplication algorithm on GPU platform, improves storage density and computation efficiency, and avoids the problem of uneven load between thread bundles.
Smart Images
Figure CN122220671A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the fields of high-performance computing and sparse computing, and in particular to an optimization method, device, medium and product for a sparse matrix-vector multiplication algorithm. Background Technology
[0002] Sparse matrix-vector multiplication (SpMV) is a core operation in scientific computing, widely used in linear solvers, finite element analysis, and graph algorithms. GPUs, due to their high parallel computing capabilities, have become the mainstream platform for accelerating SpMV. However, the irregular distribution of non-zero elements in a sparse matrix leads to discontinuous memory access and uneven load, limiting GPU performance. SpMV is calculated as y = A × x, where A is a sparse matrix and x and y are dense vectors. Because the vast majority of elements in a sparse matrix are zero, SpMV operations are characterized by uneven data load and poor data locality, making it a performance bottleneck for many iterative algorithms.
[0003] To improve the execution efficiency of SpMV on GPUs, existing techniques typically employ a block-based strategy to enhance data locality and reduce warp (thread bundle) divergence. However, traditional methods often use overly fixed block shapes, applying a uniform block size to all sparse matrices and ignoring the structural differences between matrices. The block shape cannot be adaptively adjusted, thus impacting storage density and computational efficiency. Furthermore, for sparse matrices with significant differences in the number of non-zero elements between rows, some rows may contain far more blocks than others, causing excessive load on the threads processing these rows, while other threads remain idle—a clear issue of uneven load distribution among threads. Consequently, the overall performance of SpMV on GPU platforms is limited, hardware computing resources cannot be fully and evenly utilized, making it difficult to achieve efficient SpMV computation. Summary of the Invention
[0004] The purpose of this application is to provide an optimization method, device, medium, and product for sparse matrix-vector multiplication algorithms, which can solve the problem mentioned above that "hardware computing resources cannot be fully and evenly utilized, making it difficult to achieve efficient SpMV computation".
[0005] To achieve the above objectives, this application provides the following solution: Firstly, this application provides an optimization method for a sparse matrix-vector multiplication algorithm, including: Obtain the target sparse matrix; For the target sparse matrix, multiple preset candidate block shapes are set, the score of each candidate block shape is calculated in turn, and the candidate block shape with the highest score is selected as the optimal block shape; The number of non-zero elements in each data row of the target sparse matrix is counted, and the data rows are rearranged according to the number of non-zero elements in all data rows. The rearranged target sparse matrix is divided into blocks based on the optimal block shape. The task of calculating the target sparse matrix after processing and partitioning is assigned to multiple thread bundles for parallel execution; wherein, for each data row: if the number of corresponding non-zero elements does not exceed a preset threshold, the data row is assigned to one thread bundle for processing; if the number of corresponding non-zero elements exceeds the preset threshold, the data row is split into multiple subtasks according to the preset threshold and assigned to different thread bundles for processing.
[0006] In one embodiment, the step of calculating the score for each candidate block shape specifically includes: Based on the total number of non-zero elements, the total number of thread bundles, and the basic size parameters of the candidate block shape, the score of the corresponding candidate block shape is obtained, wherein the basic size parameters include the number of blocks, the number of block rows, and the number of block columns.
[0007] In one embodiment, the step of obtaining the score of the corresponding candidate block shape based on the total number of non-zero elements, the total number of thread bundles, and the basic size parameters of the candidate block shape specifically includes: Based on the total number of non-zero elements, the number of block rows, the number of block columns, and the number of blocks, determine the block storage density of the corresponding candidate block shape; Based on the total number of thread bundles and the number of block rows, determine the number of atomic operations corresponding to the candidate block shape; Based on the total number of thread bundles and the number of block columns, determine the number of shuffling operations for the corresponding candidate block shape; The ratio of the number of atomic operations to the total number of non-zero elements is calculated to obtain the atomic operation ratio. The ratio of the number of shuffle operations to the total number of non-zero elements is calculated to obtain the shuffle operation ratio. Based on the block storage density, the atomic operation ratio, the shuffle operation ratio, and a preset weighting coefficient, the score of the corresponding candidate block shape is determined.
[0008] In one embodiment, the weighting coefficients include a first weighting factor for the block storage density, a second weighting factor for the atomic operation ratio, and a third weighting factor for the shuffling operation ratio. The step of determining the score of the corresponding candidate block shape based on the block storage density, the atomic operation ratio, the shuffling operation ratio, and the preset weighting coefficient is calculated using the following formula: ; In the formula, The block storage density, The atomic operation ratio is... The mixing ratio is the ratio for the washing operation. The first weighting factor, This is the second weighting factor. This is the third weighting factor.
[0009] In one embodiment, the target sparse matrix after being divided into blocks is stored in the form of four arrays, namely, a block pointer array, a block value array, a block column index array, and a row record index array.
[0010] In one embodiment, the task of calculating the target sparse matrix is performed using a tensor core or CUDA core on a GPU platform.
[0011] In one embodiment, after the step of allocating the task of calculating the processed, segmented target sparse matrix to multiple thread bundles for parallel execution, the method further includes: By performing a data shuffling operation within the thread bundle, the results calculated by each thread within the same thread bundle are reduced to obtain a reduced result. The reduction results of the same data row are accumulated to the corresponding position in the output vector through atomic addition operations.
[0012] Secondly, this application also provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the above-described method.
[0013] Thirdly, this application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program implements the above-described method when executed by a processor.
[0014] Fourthly, this application also provides a computer program product, including a computer program, characterized in that the computer program implements the above-described method when executed by a processor.
[0015] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides an optimization method for a sparse matrix-vector multiplication algorithm. For a target sparse matrix, multiple preset candidate block shapes are defined. The score of each candidate block shape is calculated sequentially, and the candidate block shape with the highest score is selected as the optimal block shape. By adaptively selecting the optimal block shape, the block strategy can flexibly adapt to the structural characteristics of different sparse matrices, thus avoiding the performance loss caused by the rigidity of traditional fixed block shapes. The number of non-zero elements in each data row of the target sparse matrix is counted, and multiple data rows are rearranged based on the number of non-zero elements in all data rows. The rearranged target sparse matrix is then divided into blocks based on the optimal block shape. Thus, through row rearrangement and column compression techniques, the storage density is further improved. For each data row: if the number of corresponding non-zero elements does not exceed a preset threshold, the data row is assigned to a thread bundle for processing; if the number of corresponding non-zero elements exceeds the preset threshold, the data row is split into multiple subtasks according to the preset threshold and assigned to different thread bundles for processing. Thus, the computing tasks are dynamically allocated according to the number of non-zero elements in the data row, and the excessively long rows are reasonably split according to the preset threshold, which realizes load balancing between thread bundles and avoids performance bottlenecks caused by some thread bundles processing too much data. This ensures that GPU parallel computing resources are used efficiently and in a balanced manner. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart illustrating an optimization method for a sparse matrix-vector multiplication algorithm according to an embodiment of this application. Figure 2 This is a flowchart illustrating an optimization method for a sparse matrix-vector multiplication algorithm according to an embodiment of this application. Figure 3 This is an example diagram of the target sparse matrix in the optimization method of the sparse matrix-vector multiplication algorithm according to an embodiment of this application; Figure 4 This is an example diagram of the target sparse matrix after block processing in the optimization method of the sparse matrix-vector multiplication algorithm according to an embodiment of this application. Figure 5 A diagram showing the ATBSR format representation of matrix data in the target sparse matrix of an optimization method for a sparse matrix-vector multiplication algorithm according to an embodiment of this application. Figure 6 This is a schematic diagram of the overall process of optimizing a sparse matrix-vector multiplication algorithm according to an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0020] See Figure 1 This application provides an optimization method for a sparse matrix-vector multiplication algorithm, comprising the following steps: S100: Obtain the target sparse matrix; S200: For the target sparse matrix, set multiple preset candidate block shapes, calculate the score of each candidate block shape in turn, and select the candidate block shape with the highest score as the optimal block shape; S300: Count the number of non-zero elements in each data row of the target sparse matrix, and rearrange the data rows according to the number of non-zero elements in all data rows; S400: Perform block processing on the rearranged target sparse matrix based on the optimal block shape; S500: The task of calculating the target sparse matrix after processing and partitioning is assigned to multiple thread bundles for parallel execution; wherein, for each data row: if the number of corresponding non-zero elements does not exceed a preset threshold, the data row is assigned to a thread bundle for processing; if the number of corresponding non-zero elements exceeds the preset threshold, the data row is split into multiple subtasks according to the preset threshold and assigned to different thread bundles for processing.
[0021] In S100, the target sparse matrix refers to the sparse matrix to be processed, characterized by the vast majority of its elements being zero, with only a few non-zero elements present. In this step, since the performance difference between simple storage formats and other formats is not significant in small-scale, uniform data scenarios, for regular sparse matrices with small data sizes and uniformly distributed non-zero elements, traditional formats such as CSR or ELL can be directly used for storage and computation. For other sparse matrices with large-scale or irregular distribution characteristics, the adaptive tiled storage format (AtBSR, Adaptive Tiled BSR) designed in this application can be used.
[0022] For example, the input of this application is based on the most basic CSR matrix storage format. By statistically analyzing information such as the average number of elements per row, the variance of the number of elements per row, and the number of elements in the longest and shortest rows, the CSR format is used if the number of elements is small and the data is evenly distributed. If the number of elements in a row is exactly the same, then the ELL format is used. Therefore, when traditional CSR or ELL formats are difficult to achieve efficient load balancing and storage compression, the adaptive AtBSR format of this application can be enabled to handle large-scale, irregularly distributed, and sparse matrices with significant differences in row length (high variance). This application can customize judgment criteria such as size threshold and uniformity threshold and their specific values according to actual conditions, without imposing specific restrictions.
[0023] In S200, when using the AtBSR storage format, the optimal shape needs to be adaptively selected from the preset candidate block shapes. Specifically, the step of calculating the score of each candidate block shape includes: obtaining the score of the corresponding candidate block shape based on the total number of non-zero elements, the total number of thread bundles, and the basic size parameters of the candidate block shape, wherein the basic size parameters include the number of blocks, the number of block rows, and the number of block columns.
[0024] Specifically, the steps for obtaining the score of the corresponding candidate block shape based on the basic size parameters of the total number of non-zero elements, the total number of thread bundles, and the candidate block shape include: determining the block storage density of the corresponding candidate block shape based on the total number of non-zero elements, the number of block rows, the number of block columns, and the number of blocks; determining the number of atomic operations for the corresponding candidate block shape based on the total number of thread bundles and the number of block rows; determining the number of shuffling operations for the corresponding candidate block shape based on the total number of thread bundles and the number of block columns; calculating the ratio of the number of atomic operations to the total number of non-zero elements to obtain the atomic operation ratio; calculating the ratio of the number of shuffling operations to the total number of non-zero elements to obtain the shuffling operation ratio; and determining the score of the corresponding candidate block shape based on the block storage density, the atomic operation ratio, the shuffling operation ratio, and a preset weighting coefficient.
[0025] See Figure 6 Multiple preset candidate block shapes are set (e.g., 1x32, 2x16, 4x8, 8x4, 16x2, 32x1). The score of each candidate block shape is calculated in turn. The score is then quantitatively evaluated through a comprehensive scoring function. Finally, the candidate block shape with the highest score is selected as the optimal block shape.
[0026] Typically, the runtime of the sparse matrix-vector multiplication (SpMV) algorithm is decomposed into the following parts: ; In the formula, This indicates the time taken for memory access. This indicates the time taken for the calculation. This indicates the time taken for data shuffling operations within a warp (thread bundle). This indicates the time taken for atomic operations. Different block shapes primarily affect three parameters: block storage density, which further affects... and The number of atomic operations will affect The number of mixed washing operations will affect .
[0027] For example, assume the number of warps is warpCount (the total number of thread bundles), the total number of non-zero elements is nnz, the number of blocks is blockCount, and the block size is... , For the number of rows in the block, Here, warpCount refers to the total number of thread bundles involved in the processing when performing SpMV computation on the GPU. During the adaptive block selection phase, its value is a theoretical value defined based on matrix characteristics and hardware configuration, etc. The specific definition and estimation method can be adjusted according to the actual application scenario.
[0028] Block storage density can be expressed as: ; The number of atomic operations can be expressed as: ; The number of mixed washing operations can be expressed as: ; This application includes a score function: ; In the formula, For block storage density, This represents the proportion of atomic operations. The weighting coefficients for the shuffling operation ratio include a first weighting factor for block storage density, a second weighting factor for the atomic operation ratio, and a third weighting factor for the shuffling operation ratio. As the first weighting factor, As the second weighting factor, The third weighting factor is used to quantify the relative impact of various factors on runtime. The specific values of the weighting factors can be obtained through actual testing and calibration on different hardware platforms, without any specific restrictions.
[0029] In the selection of block shape, the shape with the best theoretical performance is selected first based on the scoring function. If the number of parallel tasks (number of warps) corresponding to the best block shape is insufficient to fill the physical computing units of the GPU, that is, the physical threads cannot be fully utilized, the block shape that can start the most physical threads (i.e. occupy the GPU computing units to the maximum extent) is selected to avoid idle hardware resources and ensure that the underlying computing power is fully utilized.
[0030] In S300 and S400, see Figures 3-5 The number of non-zero elements in each row of the target sparse matrix is counted, and all data rows of the target sparse matrix are sorted according to the number to achieve compression and recombination of elements within the row. Thus, the rearranged target sparse matrix is divided into blocks according to the optimal block shape mentioned above. Through rearrangement and compression, this format has a higher storage density than the traditional block format.
[0031] See Figure 4 Based on the number of non-zero elements in each row of a sparse matrix, the data rows are rearranged. The main criterion for sorting is the number of non-zero elements in each row, so that data rows with fewer non-zero elements are placed before those with more. For multiple data rows with the same number of non-zero elements, the order in which they are arranged is not limited and can be arbitrary. At the same time, the originally discrete non-zero elements in the same data row of the matrix are aggregated together.
[0032] Based on the selected optimal block shape, the rearranged target sparse matrix is divided into multiple regular data blocks according to the optimal block shape. This block is more consistent with the distribution characteristics of matrix elements, thereby improving storage locality and the efficiency of subsequent parallel computing.
[0033] See Figure 5 The target sparse matrix is divided into blocks of 8x4 size. The block-based target sparse matrix is stored in the form of four arrays: block pointer array (blcPtr), block value array (blcVal), block column index array (blcIdx), and row record index array (recorder row index).
[0034] Specifically, for `blcPtr`: this array represents the prefix sum of the number of blocks in a row. For `blcVal`: this array stores the values of all non-zero elements within each block sequentially, ensuring that data within the same block is stored contiguously in memory, thereby optimizing memory access locality. For `blcIdx`: this array corresponds to the `blcVal` array, storing the local column index of each non-zero element within its respective block. For `recorder row index`: this array records the information of the original rows after rearrangement, that is, the row number of the original sparse matrix corresponding to each new row position. Its core function is to maintain the row mapping relationship before and after rearrangement.
[0035] In S500, in order to solve the load imbalance caused by the non-uniform distribution of sparse matrix data, achieve complex load balancing between and within thread bundles, and avoid a certain thread bundle from processing too many blocks and becoming a performance bottleneck, this application proposes a two-level load balancing strategy.
[0036] Specifically, the load balancing strategy is divided into two levels: within a warp and between warps. Within a warp, computation is performed at the warp level as the smallest unit of execution, with all threads within it having a completely balanced load, coordinating the processing of multiple elements in the same data row each time. Between warps, rows with a large number of data blocks are dynamically split to ensure that the number of consecutive data blocks allocated to each warp does not exceed a preset threshold. During this process, the starting position of the task processed by each warp and the row index position of the task processed by each warp are obtained. This threshold parameter can be obtained through testing and tuning on different hardware platforms; this application supports customizing this value according to the actual application scenario. For example, such as... Figure 6 As shown, the threshold can be set to cap = 4.
[0037] Finally, based on the block shape and load partitioning strategy obtained above, load balancing format conversion can be performed to convert the CSR format to the AtBSR storage format of this application.
[0038] See Figure 2 In this application, the computation task of the target sparse matrix is executed through the tensor cores or CUDA cores of the GPU platform. During the computation phase of this invention, the computation task of the target sparse matrix is configured to be optionally executed through the tensor cores or CUDA cores of the GPU platform; at the same time, the int16 data type is used instead of int32 to store the data, compressing the storage space required; in addition, the memory access behavior is controlled by PTX inline assembly, further optimizing the data loading and storage efficiency, thereby achieving a significant improvement in overall performance.
[0039] In one embodiment, after assigning the task of calculating the target sparse matrix after processing and partitioning to multiple thread bundles, this application further includes: reducing the results calculated by each thread within the same thread bundle through a data shuffling operation to obtain a reduction result, that is, the intermediate accumulation result of the data processed by the warp is finally obtained in a few threads (e.g., thread 0) within the warp; and accumulating the reduction result of the same data row to the corresponding position of the output vector through an atomic addition operation.
[0040] The AtBSR format of this application is characterized by no data dependency on rows. "No data dependency on rows" means that when processing sparse matrices, locating, accessing, or calculating data in any row does not require knowing or referencing any information from other rows (especially the previous row). The position can be determined solely by the row position. In contrast, the traditional BSR format has data dependencies between rows. It is necessary to determine the position of an element based on the column index information of the preceding element, which results in a serial dependency characteristic in the access process.
[0041] See Figure 6 This figure illustrates an overall exemplary flow of an optimization method for a sparse matrix-vector multiplication algorithm. First, six preset candidate block shapes are evaluated using a scoring function, and 4x8 is ultimately selected as the optimal block shape. The rearranged target sparse matrix is then divided into blocks according to this optimal block shape. The figure also indicates a preset load balancing threshold (cap=4) to control the maximum number of consecutive data points processed by each thread bundle. During the computation phase, multiple thread bundles process their assigned tasks in parallel, and multiple thread bundles jointly process multiple data points within the same data row (e.g., warp3 and warp4, warp5 and warp6, etc.). Finally, within a few threads within a warp (e.g., thread 0), an intermediate accumulated result for the data processed by that warp is obtained. Atomic addition operations are used to accumulate the reduction results of the same data row to the corresponding positions in the output vector, thus completing the efficient sparse matrix-vector multiplication computation.
[0042] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 7As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media to run. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection.
[0043] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0044] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0045] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0046] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0047] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0048] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
[0049] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0051] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. An optimization method for a sparse matrix-vector multiplication algorithm, characterized in that, include: Obtain the target sparse matrix; For the target sparse matrix, multiple preset candidate block shapes are set, the score of each candidate block shape is calculated in turn, and the candidate block shape with the highest score is selected as the optimal block shape; The number of non-zero elements in each data row of the target sparse matrix is counted, and the data rows are rearranged according to the number of non-zero elements in all data rows. The rearranged target sparse matrix is divided into blocks based on the optimal block shape. The task of calculating the target sparse matrix after processing and partitioning is assigned to multiple thread bundles for parallel execution; wherein, for each data row: if the number of corresponding non-zero elements does not exceed a preset threshold, the data row is assigned to one thread bundle for processing; if the number of corresponding non-zero elements exceeds the preset threshold, the data row is split into multiple subtasks according to the preset threshold and assigned to different thread bundles for processing.
2. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 1, characterized in that, The step of calculating the score for each candidate block shape specifically includes: Based on the total number of non-zero elements, the total number of thread bundles, and the basic size parameters of the candidate block shape, the score of the corresponding candidate block shape is obtained, wherein the basic size parameters include the number of blocks, the number of block rows, and the number of block columns.
3. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 2, characterized in that, The step of obtaining the score of the corresponding candidate block shape based on the total number of non-zero elements, the total number of thread bundles, and the basic size parameters of the candidate block shape specifically includes: Based on the total number of non-zero elements, the number of block rows, the number of block columns, and the number of blocks, determine the block storage density of the corresponding candidate block shape; Based on the total number of thread bundles and the number of block rows, determine the number of atomic operations corresponding to the candidate block shape; Based on the total number of thread bundles and the number of block columns, determine the number of shuffling operations for the corresponding candidate block shape; The ratio of the number of atomic operations to the total number of non-zero elements is calculated to obtain the atomic operation ratio. The ratio of the number of shuffle operations to the total number of non-zero elements is calculated to obtain the shuffle operation ratio. Based on the block storage density, the atomic operation ratio, the shuffle operation ratio, and a preset weighting coefficient, the score of the corresponding candidate block shape is determined.
4. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 3, characterized in that, The weighting coefficients include a first weighting factor for the block storage density, a second weighting factor for the atomic operation ratio, and a third weighting factor for the shuffling operation ratio. The step of determining the score of the corresponding candidate block shape based on the block storage density, the atomic operation ratio, the shuffling operation ratio, and the preset weighting coefficient is calculated using the following formula: ； In the formula, The block storage density, The atomic operation ratio is... The mixing ratio is the ratio for the washing operation. The first weighting factor, This is the second weighting factor. This is the third weighting factor.
5. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 1, characterized in that, The target sparse matrix after being divided into blocks is stored in the form of four arrays: a block pointer array, a block value array, a block column index array, and a row record index array.
6. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 1, characterized in that, The task of calculating the target sparse matrix is performed using the tensor cores or CUDA cores of the GPU platform.
7. The optimization method for the sparse matrix-vector multiplication algorithm according to claim 1, characterized in that, After the step of allocating the task of calculating the target sparse matrix after processing and partitioning to multiple thread bundles for parallel execution, the method further includes: By performing a data shuffling operation within the thread bundle, the results calculated by each thread within the same thread bundle are reduced to obtain a reduced result. The reduction results of the same data row are accumulated to the corresponding position in the output vector through atomic addition operations.
8. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement an optimized method for the sparse matrix-vector multiplication algorithm according to any one of claims 1-7.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements an optimized method for the sparse matrix-vector multiplication algorithm as described in any one of claims 1-7.
10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements an optimized method for the sparse matrix-vector multiplication algorithm as described in any one of claims 1-7.