A full-gan power electronic monolithic integrated circuit and a preparation method thereof

Abstract

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics and solid-state electronics technology, and specifically relates to an all-GaN power electronic monolithic integrated circuit and its fabrication method. Background Technology

[0002] With the development of power semiconductor devices, power devices made of wide-bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are being used more and more widely. GaN-based power devices, especially heterojunctions with high-mobility two-dimensional electron gas (2DEG) channels (such as AlGaN / GaN), have become candidate materials for a new generation of power conversion systems with high conversion efficiency and high power density due to their excellent material properties such as wide bandgap, high critical breakdown field strength and high operating temperature.

[0003] In semiconductor technology, all-GaN monolithic integration technology has gradually become one of the key technologies for improving integrated circuit performance due to its smaller system size, lower assembly cost, simple and excellent fabrication process, lower parasitic inductance resulting from smaller device interconnect distances, and faster switching speed due to smaller GaN device parasitic parameters and near-zero reverse recovery time. Traditional circuits typically use MOSFETs as switching devices. However, with the increase in power density and operating frequency, traditional MOSFET devices face many challenges, such as high switching losses, high leakage current, and switching speed limitations caused by capacitance effects. Therefore, using GaN HEMTs can effectively solve these problems, providing better switching performance and energy efficiency.

[0004] All-GaN power electronics monolithic integration technology enables the monolithic integration of enhancement-mode devices, depletion-mode devices, and driver circuits. Its advantages include reduced chip area, simplified packaging and smaller package size, reduced threshold voltage drift and dynamic on-resistance degradation due to the use of low-voltage transistors as control transistors, superior high-frequency performance due to reduced parasitic parameters, and reduced switching losses. Dielectric-isolated technology offers significant advantages in power electronics and other fields, particularly in suppressing crosstalk and substrate bias effects. Applying composite substrates to GaN power cell monolithic integration fully leverages the advantages of composite substrate technology, such as matching thermal expansion coefficients with epitaxial layers, high withstand voltage, high mechanical strength, and high thermal conductivity. It also facilitates subsequent large-area, thick-film GaN epitaxial layer growth. Utilizing composite substrate technology yields high-performance monolithic integrated structures, thereby fully realizing the performance advantages of GaN power cells. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an all-GaN power electronic monolithic integrated circuit and its fabrication method, so as to realize monolithic integration of GaN power units, reduce epitaxial layer matching and reduce switching losses.

[0006] This invention provides an all-GaN power electronic monolithic integrated circuit, comprising, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer, and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, and a p-GaN layer is grown; the gate portion of the p-GaN layer is etched and filled with a passivation layer, followed by the growth of a gate metal; source metal and drain metal are grown on both sides of the gate region of the p-GaN layer, respectively; a deep trench is provided between the driving circuit and the low-voltage transistor, and between the high-voltage transistor and the low-voltage transistor, penetrating the passivation layer, the AlGaN layer, the GaN layer, the GaN / AlGaN buffer layer, and the Si layer, and the deep trench is filled with a dielectric; the all-GaN power electronic monolithic integrated circuit is obtained through top vias and interconnect processes.

[0007] This invention also provides a method for fabricating the above-mentioned all-GaN power electronic monolithic integrated circuit, comprising the following steps:

[0008] (1) An AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer, and an AlGaN layer are sequentially deposited on an insulating composite substrate to obtain a GaN HEMT structure;

[0009] (2) Etch the AlGaN layer, and then grow the p-GaN layer;

[0010] (3) Etch out the gate portion of the p-GaN layer and fill it with a passivation layer, then grow the gate metal G. D and gate metal G E ;

[0011] (4) After etching, source metal S is grown on both sides of the gate region of the p-GaN layer. D Heyuanji Metal S E Drain metal D D and drain metal D E Deep trench etching is used below the source electrode, penetrating the passivation layer, AlGaN layer, GaN layer, GaN / AlGaN buffer layer, and terminating at the Si layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer.

[0012] (5) Deep trench etching is performed between the driving circuit and the low voltage tube, and between the high voltage tube and the low voltage tube, penetrating the passivation layer, AlGaN layer, GaN layer, GaN / AlGaN buffer layer and Si layer.

[0013] (6) Fill the deep trench described in step (5) with a medium to achieve isolation between the high-voltage tube, the low-voltage tube and the drive circuit;

[0014] (7) By using top vias and interconnection processes, the source of the high-voltage transistor is connected to the drain of the low-voltage transistor, the gate of the high-voltage transistor is connected to the source of the low-voltage transistor, and the gate of the low-voltage transistor is connected to the driving circuit, thus obtaining a full GaN power electronic monolithic integrated circuit.

[0015] Preferably, the insulating composite substrate in step (1) is a material whose thermal expansion coefficient matches that of Si, including one of polycrystalline AlN ceramic, SiN ceramic or SOI (Silicon On Insulator).

[0016] Preferably, the gate metal in step (3), the source metal and the drain metal in step (4) include, but are not limited to, one or more of W, TiN, Al, Ni, Ti, Au, Mo and Pt.

[0017] Preferably, the etching methods in steps (2), (3), (4), and (5) include, but are not limited to, ICP and RIE, and the etching atmosphere includes, but is not limited to, one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2, and He.

[0018] Preferably, the materials of the passivation layer in step (3) and the medium in step (6) include, but are not limited to, one or more of the following stacked structures: SiO2, Al2O3, HfO2, La2O3, ZrO2, and Si3N4.

[0019] Preferably, the growth methods for the passivation layer in step (3) and the medium in step (6) include, but are not limited to, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, and sputtering.

[0020] Preferably, the high-voltage tube corresponds to the D-mode GaN device region, and the low-voltage tube corresponds to the E-mode GaN device region.

[0021] This invention provides an application of the above-mentioned all-GaN power electronic monolithic integrated circuit in a half-bridge circuit.

[0022] The present invention also provides an application of the above-mentioned all-GaN power electronic monolithic integrated circuit in a full-bridge circuit.

[0023] Advantages

[0024] (1) This invention achieves high efficiency and low power consumption: The all-GaN power electronics monolithic integrated circuit achieves enhancement characteristics by growing a p-GaN layer on top of the AlGaN / GaN heterojunction. This structure avoids the normally-on mode in traditional GaN HEMTs, reduces static power consumption during power conversion, and improves the overall efficiency of the system.

[0025] (2) The present invention has good electrical isolation: an insulating oxide layer is formed between the device and the substrate in the composite substrate, which effectively reduces mutual interference between devices (such as parasitic capacitance and parasitic diode effect). In addition, the driving circuit, high voltage tube and low voltage tube are isolated by deep trench etching technology, and the source and substrate are at the same potential, which can avoid substrate crosstalk.

[0026] (3) The present invention can reduce leakage current and switching loss: the insulating layer of the composite substrate can reduce substrate leakage current and parasitic effects caused by the substrate, and the dielectric above p-GaN makes the device gate leakage current smaller. Both of these factors improve the electrical performance of the system and reduce power loss.

[0027] (4) This invention exhibits excellent thermal stability: the insulating layer in the composite substrate helps limit heat transfer to the silicon substrate, reducing thermal coupling effects between devices. This thermal isolation improves the performance stability of integrated circuits under high-temperature conditions. Furthermore, the p-GaN process achieves enhanced devices while maintaining better thermal stability.

[0028] (5) The present invention achieves low parasitic effects: it avoids the parasitic effects caused by wire bonding, heterogeneous packaging and other methods of Si-based driving circuits and Si-based low-voltage devices, and improves their switching performance.

[0029] (6) The present invention has a fast switching speed: the common source and common gate technology reduces the Miller capacitance of the all-GaN device, and takes advantage of the extremely low reverse recovery effect of GaN device to greatly reduce turn-off loss and switching time. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of the all-GaN power electronic monolithic integrated circuit of the present invention.

[0031] Figure 2 This is a schematic diagram of the GaN HEMT structure of the present invention.

[0032] Figure 3 This is a schematic diagram of the structure after the p-GaN layer is grown according to the present invention.

[0033] Figure 4 This is a schematic diagram of the structure after the gate metal is grown according to the present invention.

[0034] Figure 5 This is a schematic diagram of the structure after the source metal and drain metal of the present invention have been grown.

[0035] Figure 6 This is a schematic diagram of the structure after the deep groove is etched in this invention.

[0036] Figure 7 This is a schematic diagram of the structure of the present invention after the deep trench is filled with the medium.

[0037] Figure 8 This is a schematic diagram illustrating the structure of the all-GaN power electronic monolithic integrated circuit of the present invention used in a half-bridge circuit.

[0038] Figure 9 This is a schematic diagram illustrating the structure of the all-GaN power electronic monolithic integrated circuit of the present invention used in a full-bridge circuit.

[0039] Figure reference numerals: 1-High voltage transistor, 2-Low voltage transistor, 3-Driver circuit, 110-Insulating composite substrate, 120-AlN layer, 130-Si layer, 140-GaN / AlGaN buffer layer, 150-GaN layer, 160-AlGaN layer, 170-p-GaN layer, 180-Passivation layer, 191-Gate metal G D 192-Gate metal G E 193-Source Metal S D 194-Source Metal S E 195-Drain metal D D 196-Drain metal D E 200-2DEG layer. Detailed Implementation

[0040] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0041] Example

[0042] This invention provides an all-GaN power electronic monolithic integrated circuit, such as... Figure 1 As shown, the circuit includes, from bottom to top, an insulating composite substrate 110, an AlN layer 120, a Si layer 130, a GaN / AlGaN buffer layer 140, a GaN layer 150, and an AlGaN layer 160; a 2DEG layer 200 is formed between the GaN layer 150 and the AlGaN layer 160; the AlGaN layer 160 is etched, and a p-GaN layer 170 is grown; the gate portion of the p-GaN layer 170 is etched and filled with a passivation layer 180, followed by the growth of a gate metal; source metal and drain metal are grown on both sides of the gate region of the p-GaN layer 170, respectively; a deep trench is provided between the driving circuit 3 and the low-voltage transistor 2, and between the high-voltage transistor 1 and the low-voltage transistor 2, penetrating the passivation layer 180, the AlGaN layer 160, the GaN layer 150, the GaN / AlGaN buffer layer 140, and the Si layer 130, and the deep trench is filled with a dielectric; a full GaN power electronic monolithic integrated circuit is obtained through top vias and interconnection processes.

[0043] This invention also provides a method for fabricating the above-mentioned all-GaN power electronic monolithic integrated circuit, comprising the following steps:

[0044] (1) As Figure 2 As shown, an AlN layer 120, a Si layer 130, a GaN / AlGaN buffer layer 140, a GaN layer 150, and an AlGaN layer 160 are sequentially disposed on an insulating composite substrate 110 to obtain a GaN HEMT structure.

[0045] (2) Figure 3 As shown, the AlGaN layer 160 is etched, followed by the growth of the p-GaN layer 170;

[0046] (3) Figure 4 As shown, the p-GaN layer 170 gate portion is etched and filled with a passivation layer 180, followed by the growth of the gate metal G. D 191 and gate metal G E 192;

[0047] (4) Figure 5 As shown, after etching, source metal S is grown on both sides of the gate region of the p-GaN layer 170. D 193 and source metal S E 194. Drain metal D D 195 and drain metal D E 196, wherein a deep trench is used below the source electrode, penetrating the passivation layer 180, AlGaN layer 160, GaN layer 150, GaN / AlGaN buffer layer 140, and terminating at Si layer 130; a 2DEG layer 200 is formed between the GaN layer 150 and AlGaN layer 160.

[0048] (5) Figure 6 As shown, deep trench etching is performed between the driving circuit 3 and the low-voltage tube 2, and between the high-voltage tube 1 and the low-voltage tube 2, penetrating the passivation layer 180, the AlGaN layer 160, the GaN layer 150, the GaN / AlGaN buffer layer 140 and the Si layer 130.

[0049] (6) Figure 7 As shown, the deep trench described in step (5) is filled with a medium to achieve isolation between the high-pressure tube 1, the low-pressure tube 2, and the drive circuit 3;

[0050] (7) Figure 1 As shown, through top vias and interconnection processes, the source of high-voltage transistor 1 is connected to the drain of low-voltage transistor 2, the gate of high-voltage transistor 1 is connected to the source of low-voltage transistor 2, and the gate of low-voltage transistor 2 is connected to the driving circuit 3, thus obtaining a full GaN power electronic monolithic integrated circuit.

[0051] This invention provides an application of the above-mentioned all-GaN power electronic monolithic integrated circuit in a half-bridge circuit, such as... Figure 8 As shown.

[0052] This invention also provides an application of the above-mentioned all-GaN power electronic monolithic integrated circuit in a full-bridge circuit, such as... Figure 9 As shown.

Claims

1. A monolithic GaN power electronic integrated circuit, characterized in that, The all-GaN power electronic monolithic integrated circuit includes, from bottom to top, an insulating composite substrate (110), an AlN layer (120), a Si layer (130), a GaN / AlGaN buffer layer (140), a GaN layer (150), and an AlGaN layer (160); a 2DEG layer (200) is formed between the GaN layer (150) and the AlGaN layer (160); the AlGaN layer (160) is etched, and a p-GaN layer (170) is grown; the gate portion of the p-GaN layer (170) is etched and filled with a passivation layer. (180), then the gate metal is grown; the active metal and drain metal are grown on both sides of the gate region of the p-GaN layer (170); a deep trench is provided between the driving circuit (3) and the low voltage tube (2), and between the high voltage tube (1) and the low voltage tube (2), penetrating the passivation layer (180), AlGaN layer (160), GaN layer (150), GaN / AlGaN buffer layer (140) and Si layer (130), and the deep trench is filled with dielectric; a full GaN power electronic monolithic integrated circuit is obtained through top vias and interconnection processes.

2. A method for fabricating an all-GaN power electronic monolithic integrated circuit as described in claim 1, comprising the following steps: (1) An AlN layer (120), a Si layer (130), a GaN / AlGaN buffer layer (140), a GaN layer (150), and an AlGaN layer (160) are sequentially disposed on an insulating composite substrate (110) to obtain a GaN HEMT structure. (2) Etch the AlGaN layer (160), and then grow the p-GaN layer (170); (3) The p-GaN layer (170) gate portion is etched and filled with a passivation layer (180), followed by growth of the gate metal G. D (191) and gate metal G E (192); (4) After etching, source metal S is grown on both sides of the gate region of the p-GaN layer (170). D (193) and source metal S E (194) Drain metal D D (195) and drain metal D E (196) wherein a deep trench is used below the source electrode, penetrating the passivation layer (180), AlGaN layer (160), GaN layer (150), GaN / AlGaN buffer layer (140), and terminating at the Si layer (130); a 2DEG layer (200) is formed between the GaN layer (150) and the AlGaN layer (160); (5) Deep trench etching is performed between the driving circuit (3) and the low-voltage tube (2), the high-voltage tube (1) and the low-voltage tube (2), penetrating the passivation layer (180), the AlGaN layer (160), the GaN layer (150), the GaN / AlGaN buffer layer (140) and the Si layer (130). (6) Fill the deep trench described in step (5) with a medium to achieve isolation between the high-pressure tube (1), the low-pressure tube (2), and the drive circuit (3); (7) By using top vias and interconnection processes, the source of the high-voltage transistor (1) is connected to the drain of the low-voltage transistor (2), the gate of the high-voltage transistor (1) is connected to the source of the low-voltage transistor (2), and the gate of the low-voltage transistor (2) is connected to the driving circuit (3), thus obtaining a full GaN power electronic monolithic integrated circuit.

3. The preparation method according to claim 2, characterized in that, The insulating composite substrate (110) in step (1) is a material whose thermal expansion coefficient matches that of Si, including one of polycrystalline AlN ceramic, SiN ceramic or SOI.

4. The preparation method according to claim 2, characterized in that, The gate metal in step (3), the source metal in step (4), and the drain metal include one or more of W, TiN, Al, Ni, Ti, Au, Mo, and Pt.

5. The preparation method according to claim 2, characterized in that, The etching methods in steps (2), (3), (4), and (5) include ICP and RIE, and the etching atmosphere includes one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2, and He.

6. The preparation method according to claim 2, characterized in that, The materials of the passivation layer (180) in step (3) and the medium in step (6) include one or more stacked structures of SiO2, Al2O3, HfO2, La2O3, ZrO2, and Si3N4.

7. The preparation method according to claim 2, characterized in that, The methods for growing the passivation layer (180) in step (3) and the medium in step (6) include chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, and sputtering.

8. The application of the all-GaN power electronic monolithic integrated circuit as described in claim 1 in a half-bridge circuit.

9. The application of the all-GaN power electronic monolithic integrated circuit as described in claim 1 in a full-bridge circuit.

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