Power device junction temperature and current monitoring method and system based on source parasitic voltage feature extraction and fixed-point MLP edge inference
By extracting source parasitic voltage features and using fixed-point MLP edge inference, the problem of real-time, non-destructive, and high-precision monitoring of junction temperature and current of power devices in high-frequency power electronic systems is solved, achieving efficient monitoring in an edge computing environment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
- Filing Date
- 2026-02-10
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies struggle to achieve high-precision, non-destructive, real-time monitoring of junction temperature and current of power devices in high-frequency power electronic systems, especially in edge computing environments where deployment is difficult. Furthermore, traditional methods suffer from slow response speeds, high costs, and high computational complexity.
A method based on source parasitic voltage feature extraction and fixed-point MLP edge inference is adopted. By capturing the source parasitic inductance voltage of power devices in real time, converting it into a voltage integral waveform, extracting key time-domain features, and deploying a fixed-point multilayer perceptron on an FPGA for inference, the junction temperature and current can be monitored.
It achieves high-precision junction temperature and current monitoring with extremely low latency, meets the real-time requirements of high-frequency Buck circuits, reduces computing resources and costs, and is suitable for edge device deployment.
Smart Images
Figure CN122259975A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power device parasitic parameter measurement technology, and in particular to a method and system for monitoring junction temperature and current of power devices based on source parasitic voltage feature extraction and fixed-point MLP edge inference. Background Technology
[0002] As power electronic systems evolve towards higher power density, higher frequency, and higher reliability, monitoring the health status of core power devices (such as MOSFETs) becomes crucial. Among these, junction temperature and operating current are two of the most critical parameters for characterizing their operating status, predicting their lifespan, and even enabling proactive thermal management of the system. Traditional monitoring methods have significant limitations: 1) Junction temperature monitoring usually uses external thermistors or infrared thermal imaging. The former has a slow response speed, cannot directly measure the chip junction temperature and has installation delays, while the latter is expensive and difficult to apply in closed systems. 2) Current monitoring typically uses a series sampling resistor or a Hall sensor. The former introduces additional power loss and reduces system efficiency, while the latter has issues with cost, bandwidth, and linearity. 3) Model estimation is usually based on the positive correlation between the on-resistance Rds(on) and junction temperature in the device datasheet. This method relies heavily on accurate calibration and is easily affected by factors such as device aging and process discreteness, making it difficult to guarantee accuracy.
[0003] In recent years, the academic community has proposed using the parasitic parameters of power devices (such as the package source inductance Ls) for non-destructive monitoring. During switching transients, the change in current flowing through Ls will generate an induced voltage Vss across it. This voltage contains rich information about the switching process and is directly related to the rate of change of current (di / dt), while di / dt itself is affected by junction temperature and current magnitude. However, the practical application of this method faces significant challenges: 1) Feature extraction is difficult: Vss signal is a high-frequency, transient, and weak signal that is easily overwhelmed by switching noise, resulting in unstable feature extraction. 2) High computational complexity: To achieve high-precision estimation, complex machine learning algorithms (such as deep learning) are often required. These algorithms run on general-purpose processors or even high-performance DSPs, with inference latency of tens or even hundreds of microseconds, which cannot meet the real-time requirements of high-frequency Buck circuits (switching frequencies of hundreds of kHz to several MHz). 3) Edge deployment bottleneck: Floating-point operation model has high requirements for computing resources and memory bandwidth, making it difficult to deploy on resource-constrained edge FPGAs or ASICs, and power consumption and cost are difficult to control. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a method and system for monitoring junction temperature and current of power devices based on source parasitic voltage feature extraction and fixed-point MLP edge inference, which can achieve high-precision and high-reliability online monitoring of junction temperature and current with extremely low latency and limited hardware resources.
[0005] The technical solution adopted by this invention to solve its technical problem is: to provide a method for monitoring junction temperature and current of power devices based on source parasitic voltage feature extraction and fixed-point MLP edge inference, including the following steps: Real-time capture of the source parasitic inductance voltage of power devices and conversion into voltage integral waveform; Extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The extracted time-domain features are input into a fixed-point multilayer perceptron deployed on the edge device to infer the junction temperature and current of the power device.
[0006] Furthermore, several time-domain characteristics sensitive to changes in device junction temperature and current include maximum, minimum, average, standard deviation, and voltage at a fixed time point.
[0007] Furthermore, the fixed-point format of the multilayer perceptron includes 8 integer bits and 12 decimal bits, with the decimal point fixed at the boundary between the integer and decimal bits.
[0008] Furthermore, the fixed-point multilayer perceptron includes one input layer, two hidden layers, and one output layer; wherein, the input layer includes multiple neurons that correspond one-to-one with the temporal features of the input, each hidden layer includes 16 neurons, and the output layer includes two neurons that correspond to the junction temperature and current of the output, respectively.
[0009] Furthermore, the fixed-point multilayer perceptron is deployed on an FPGA. Its input interfaces include an ADC data input bus interface, a clock signal interface, a reset signal interface, and an inference start signal interface. Its output interfaces include a junction temperature output bus interface and a current output bus interface.
[0010] Furthermore, the weight parameters and bias parameters of the fixed-point multilayer perceptron are stored on the ROM of the FPGA.
[0011] Furthermore, the fixed-point multilayer perceptron breaks down the inference process into four pipelines during inference, corresponding to the input layer, hidden layer and output layer of the multilayer perceptron, respectively, and builds an independent computing module for each pipeline on the FPGA to achieve parallel processing.
[0012] Furthermore, a control state machine is built on the FPGA to coordinate the data flow and control flow during inference, so that the feature vectors can flow through the input layer, the first hidden layer, the second hidden layer and the output layer in sequence without waiting for the previous level of inference to complete, thereby minimizing inference latency.
[0013] This invention also provides a power device junction temperature and current monitoring system based on source parasitic voltage feature extraction, comprising: The feature acquisition unit is used to capture the source parasitic inductance voltage of the power device in real time and convert it into a voltage integral waveform; The voltage extraction unit is used to extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The edge inference device is equipped with a fixed-point multilayer perceptron, which is used to infer the junction temperature and current of the power device based on the extracted time-domain features.
[0014] Furthermore, the feature acquisition unit includes a high-side active integrator composed of an RC network and an operational amplifier.
[0015] Beneficial effects By adopting the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: This invention directly utilizes the parasitic parameters of the device itself, without the need for additional external components such as thermistors, sampling resistors, and Hall sensors. It does not introduce additional power consumption, does not change the main power circuit, and truly realizes non-destructive online monitoring of the junction temperature and current of power devices. This invention designs a fully pipelined hierarchical architecture on an FPGA and combines it with the parallel computing characteristics of FPGA hardware to compress the inference latency to 200ns, achieving high real-time performance at the microsecond level and meeting the most demanding high-frequency power conversion application requirements. This invention, through carefully designed feature engineering and fixed-pointing techniques, greatly reduces the model's requirements for computing resources, storage resources, and memory bandwidth while ensuring model accuracy, thus guaranteeing high-precision inference at the edge. The entire monitoring system can be integrated as an IP core with the Buck circuit's digital controller on the same FPGA or ASIC, significantly reducing the system's size, complexity, and overall cost. This invention can prevent devices from being damaged by overheating by monitoring junction temperature in real time and accurately, and can also predict the remaining lifespan of devices by combining lifespan models, thus achieving predictive maintenance. Attached Figure Description
[0016] Figure 1 This is a flowchart of the first embodiment of the present invention; Figure 2 This is a schematic diagram of the Vss extraction circuit according to an embodiment of the present invention; Figure 3 This is a Vss integral waveform diagram of an embodiment of the present invention; Figure 4 This is a schematic diagram of the MLP interface according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the floating-point MLP prediction performance of the first embodiment of the present invention; Figure 6 This is a schematic diagram of the fixed-point MLP prediction performance of the first embodiment of the present invention; Figure 7 This is a predicted waveform and prediction delay diagram of the first embodiment of the present invention. Detailed Implementation
[0017] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0018] The first embodiment of the present invention relates to a method for monitoring the junction temperature and current of power devices based on source parasitic voltage feature extraction and fixed-point MLP edge inference. It aims to overcome the shortcomings of the prior art through the collaborative design of hardware feature extraction, software intelligent algorithm and hardware accelerated inference, and realize non-destructive, real-time and high-precision online monitoring of the junction temperature and current of power MOSFETs in Buck converters in an edge computing environment.
[0019] Specifically, firstly, the source parasitic inductance voltage Vss is captured using a dedicated analog front-end circuit, from which five key time-domain features are robustly extracted. Then, using a specially trained and optimized fixed-point multilayer perceptron model, a highly parallel pipelined architecture is employed on an FPGA to achieve extremely fast joint inference of junction temperature T and current Ids0. Figure 1 As shown, it includes the following steps: Real-time capture of the source parasitic inductance voltage of power devices and conversion into voltage integral waveform; Extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The extracted time-domain features are input into a fixed-point multilayer perceptron deployed on the edge device to infer the junction temperature and current of the power device.
[0020] VSS extracts hardware circuits such as Figure 2 As shown, a Vss sampling circuit based on a high-side active integrator is designed. This circuit is directly connected between the source of the power MOSFET and ground, and forms an integrator with an operational amplifier through a precision RC network. Figure 3This demonstrates how the Vss integral waveform, actually acquired by the hardware circuit, is extracted during a complete switching cycle of the Buck circuit.
[0021] Then, five time-domain features that are sensitive to junction temperature and current changes and are easy to calculate are extracted from the Vss integral waveform, such as... Figure 4 As shown, the maximum, minimum, average, standard deviation, and voltage at fixed time points are input to an optimized fixed-point multilayer perceptron model for inference.
[0022] This implementation specifically optimizes the MLP to adapt it to the resource constraints of edge-side FPGAs / ASICs and the real-time requirements of high-frequency Buck circuits, including: 1) Fixed-point transformation: Convert the conventional floating-point MLP to a Q8.12 fixed-point model, which significantly reduces the model's consumption of computing resources and memory bandwidth while ensuring prediction accuracy, and solves the deployment bottleneck of floating-point models on resource-constrained edge hardware; 2) Lightweight structure design: A compact network structure of 5-16-16-2 is adopted. The input layer corresponds to 5 Vss time-domain features, and 2 hidden layers with 16 neurons each are set. The output layer directly outputs two target parameters, junction temperature and current, to avoid the high computational cost caused by complex networks. 3) Hardware pipeline adaptation: In conjunction with the FPGA pipeline architecture, the matrix multiplication, activation function and other operations of MLP are decomposed into dedicated hardware modules for parallel execution, so that a single inference only requires 10 clock cycles (200ns delay), which meets the real-time requirements of high-frequency Buck circuits with switching frequencies of hundreds of kHz to several MHz.
[0023] Traditional machine learning models use floating-point numbers to store parameters and perform calculations, requiring complex hardware processing units and placing extremely high demands on the resources and bandwidth of FPGAs / ASICs. Fixed-point modeling, on the other hand, uses integers to replace floating-point numbers for calculations: physical quantities or model parameters containing decimals are scaled to integers for storage by a fixed ratio, calculations are performed entirely using integers, and finally scaled back to the actual physical quantities, completely avoiding the resource consumption of floating-point operations.
[0024] This implementation uses the Q8.12 fixed-point format, with a total integer bit length of 8 bits, including 1 sign bit and 7 integer value bits. It can represent integers ranging from -128 to +127, covering the junction temperature and current value range. The fractional bit length is 12 bits, representing a minimum precision far exceeding the monitoring error requirements for junction temperature and current without sacrificing monitoring accuracy. The total bit length is 20 bits, significantly less than 32-bit single-precision floating-point numbers, greatly reducing storage and bandwidth consumption, thus adapting to edge device deployments.
[0025] Figure 5 and Figure 6 These are schematic diagrams illustrating the prediction performance of floating-point MLP and MLP after Q8.12 fixed-point conversion. It is not difficult to see that the prediction performance of MLP remains basically unchanged after Q8.12 fixed-point conversion.
[0026] The optimized multilayer perceptron in this embodiment adopts a lightweight 5-16-16-2 architecture customized for edge FPGA deployment. Each digit corresponds to the number of neurons in each layer of the neural network. The specific meaning is broken down in conjunction with the invention scenario as follows: The input layer has 5 neurons, corresponding to 5 time-domain features (such as waveform rise slope, peak amplitude, duration, etc.) that are sensitive to junction temperature and current extracted from the Vss integral waveform. The number of input layer neurons is matched one-to-one with the number of features to receive stable feature data captured by the hardware circuit as input for model inference. The two hidden layer neurons are configured with 16, indicating that the MLP contains two hidden layers, each with 16 neurons. The 16 neurons are sufficient to capture the nonlinear coupling relationship between the Vss feature and the junction temperature and current, while avoiding the surge in computation caused by too many neurons. This perfectly adapts to the hardware characteristics of fixed-point modification and FPGA pipeline parallel computing.
[0027] The output layer has 2 neurons, corresponding to the two core monitoring targets of this invention—junction temperature and current. The output layer directly outputs the fixed-point calculation results of these two parameters, and the actual physical quantities can be obtained after simple inverse scaling.
[0028] The external interface of the MLP inference engine deployed on the FPGA includes an ADC data input bus, a clock signal, a reset signal, an inference start signal, and two output buses for junction temperature and current. Its hardware interface module is implemented as follows.
[0029] module mlp_inference ( input clk, input rst_n, / / --- Input Interface --- input i_valid, input signed [DATA_WIDTH-1:0] i_adc_max, input signed [DATA_WIDTH-1:0] i_adc_min, input signed [DATA_WIDTH-1:0] i_adc_mean, input signed [DATA_WIDTH-1:0] i_adc_std, input signed [DATA_WIDTH-1:0] i_adc_at_2e6, / / --- Output Interface --- output reg o_valid, output reg signed [DATA_WIDTH-1:0] o_temp, output reg signed [DATA_WIDTH-1:0] o_ids0 ); The clock (clk) and reset (rst_n) are used to adapt to FPGA timing control and ensure synchronous pipeline execution. The five signed [DATA_WIDTH-1:0] type signals of the input interface correspond to five time-domain features extracted from the Vss integral waveform. `signed` indicates a fixed-point signed number, and `DATA_WIDTH` should correspond to the bit width of the Q8.12 fixed-point conversion. The output interface `o_valid` is the valid flag for the inference result, `o_temp` outputs the fixed-point junction temperature result, and `o_ids0` outputs the fixed-point current result.
[0030] The internal core modules of the MLP inference engine deployed on the FPGA include: Parameter ROM: Used to store the weights and bias parameters of the fixed-point MLP model; Pipeline computation unit: The 5-16-16-2 MLP network is decomposed into a multi-stage pipeline, and the computation of each layer (matrix multiplication, addition, activation function) is completed in a dedicated hardware module; Control state machine: coordinates data flow and control flow to ensure that each pipeline stage receives data and begins computation at the correct time.
[0031] This implementation breaks down the complete process of a single inference task into multiple independent stages. The feature vector starts from the input layer and flows sequentially through the first hidden layer, the second hidden layer, and the output layer like an assembly line. The next stage can start processing new input data before the previous stage is completed, thereby compressing the latency of single-sample inference to the sum of the latencies of each stage and achieving high throughput to meet the real-time computing requirements of high-frequency Buck circuits.
[0032] Specifically, the inference process is divided into four main pipelines corresponding to the four levels of the MLP, with each level corresponding to a complete level of MLP computation. In some preferred embodiments, to further reduce single-level latency, the computation steps within each level can be further divided into sub-pipeline stages, forming a nested structure of main pipelines combined with sub-pipelines.
[0033] Taking a high-frequency Buck circuit as an example, when the Vss feature of the first switching cycle is calculated in stage 2 of the pipeline, the Vss feature of the second switching cycle has already entered stage 1 of the pipeline for calculation. At this time, the total delay of single-sample inference is only the sum of the delays of the three main pipeline stages, which is much smaller than the switching cycle, ensuring that real-time junction temperature and current data can be output in each switching cycle.
[0034] Figure 7 Simulation results of real-time intelligent monitoring on a running Buck circuit are presented. Measurements of the entire time delay from the eigenvector input to the effective MLP output show that, driven by a 50MHz system clock, a complete inference cycle is completed in just 10 clock cycles. Calculated delay: 10 clock cycles × 20 ns / cycle = 200 ns.
[0035] This implementation achieves high-precision, real-time monitoring of junction temperature and current of power devices through the collaborative work of hardware feature extraction, software intelligent algorithms, and hardware accelerated inference, solving the problems of real-time performance, accuracy, and deployment cost of traditional methods.
[0036] The second embodiment of the present invention relates to a power device junction temperature and current monitoring system based on source parasitic voltage feature extraction and fixed-point MLP edge inference, used to implement the above-mentioned power device junction temperature and current monitoring method, including: The feature acquisition unit is used to capture the source parasitic inductance voltage of the power device in real time and convert it into a voltage integral waveform; The voltage extraction unit is used to extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The edge inference device is equipped with a fixed-point multilayer perceptron, which is used to infer the junction temperature and current of the power device based on the extracted time-domain features.
[0037] VSS extracts hardware circuits such as Figure 2 As shown, a Vss sampling circuit based on a high-side active integrator is designed. This circuit is directly connected between the source of the power MOSFET and ground, and forms an integrator with an operational amplifier through a precision RC network. Figure 3 This demonstrates how the Vss integral waveform, actually acquired by the hardware circuit, is extracted during a complete switching cycle of the Buck circuit.
[0038] Then, five time-domain features that are sensitive to junction temperature and current changes and are easy to calculate are extracted from the Vss integral waveform, such as... Figure 4 As shown, the maximum, minimum, average, standard deviation, and voltage at fixed time points are input to an optimized fixed-point multilayer perceptron model for inference.
[0039] The multilayer perceptron adopts a lightweight 5-16-16-2 architecture, a fixed-point version of the Q8.12, customized for edge-side FPGA deployment. External interfaces include an ADC data input bus, clock signal, reset signal, inference start signal, and two output buses for junction temperature and current. Internal core modules include: Parameter ROM: Used to store the weights and bias parameters of the fixed-point MLP model; Pipeline computation unit: The 5-16-16-2 MLP network is decomposed into a multi-stage pipeline, and the computation of each layer (matrix multiplication, addition, activation function) is completed in a dedicated hardware module; The control state machine coordinates the data flow and control flow, ensuring that each pipeline stage receives data and begins computation at the correct time. Feature vectors start from the input and flow sequentially through the first hidden layer, the second hidden layer, and the output layer, much like an assembly line. This entire process does not wait for the previous inference to complete, maximizing throughput.
Claims
1. A method for monitoring junction temperature and current of power devices based on source parasitic voltage feature extraction and fixed-point MLP edge inference, characterized in that, Includes the following steps: Real-time capture of the source parasitic inductance voltage of power devices and conversion into voltage integral waveform; Extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The extracted time-domain features are input into a fixed-point multilayer perceptron deployed on the edge device to infer the junction temperature and current of the power device.
2. The method for monitoring junction temperature and current of power devices according to claim 1, characterized in that, Several time-domain characteristics that are sensitive to changes in device junction temperature and current include maximum, minimum, average, standard deviation, and voltage at a fixed time point.
3. The method for monitoring junction temperature and current of power devices according to claim 1, characterized in that, The fixed-point format of a multilayer perceptron includes 8 integer bits and 12 decimal bits, with the decimal point fixed at the boundary between the integer and decimal bits.
4. The method for monitoring junction temperature and current of power devices according to claim 1, characterized in that, The fixed-point multilayer perceptron includes one input layer, two hidden layers, and one output layer. The input layer includes multiple neurons that correspond one-to-one with the temporal features of the input, each hidden layer includes 16 neurons, and the output layer includes two neurons that correspond to the junction temperature and current of the output.
5. The method for monitoring junction temperature and current of power devices according to claim 4, characterized in that, The fixed-point multilayer perceptron is deployed on an FPGA. Its input interfaces include an ADC data input bus interface, a clock signal interface, a reset signal interface, and an inference start signal interface. Its output interfaces include a junction temperature output bus interface and a current output bus interface.
6. The method for monitoring junction temperature and current of power devices according to claim 5, characterized in that, The weight parameters and bias parameters of the fixed-point multilayer perceptron are stored on the ROM of the FPGA.
7. The method for monitoring junction temperature and current of power devices according to claim 5, characterized in that, The fixed-point multilayer perceptron breaks down the inference process into four pipelines during inference, corresponding to the input layer, hidden layer and output layer of the multilayer perceptron, respectively. An independent computing module is built for each pipeline on the FPGA to achieve parallel processing.
8. The method for monitoring junction temperature and current of power devices according to claim 7, characterized in that, A control state machine is built on the FPGA to coordinate the data flow and control flow during inference, so that the feature vector can flow through the input layer, the first hidden layer, the second hidden layer and the output layer in sequence without waiting for the previous level of inference to complete, thereby minimizing inference latency.
9. A power device junction temperature and current monitoring system based on source parasitic voltage feature extraction, characterized in that, include: The feature acquisition unit is used to capture the source parasitic inductance voltage of the power device in real time and convert it into a voltage integral waveform; The voltage extraction unit is used to extract multiple time-domain features that are sensitive to changes in device junction temperature and current from the voltage integral waveform; The edge inference device is equipped with a fixed-point multilayer perceptron, which is used to infer the junction temperature and current of the power device based on the extracted time-domain features.
10. The junction temperature and current monitoring system according to claim 9, characterized in that, The feature acquisition unit includes a high-side active integrator consisting of an RC network and an operational amplifier.