A reconstruction speed control method and device based on PID control, equipment, storage medium and program product

Abstract

The method comprises the following steps: acquiring dotting data of an input / output path of an operation unit; determining local time delay data of each operation unit; storing the local time delay data into a mapping table; analyzing the mapping table to obtain a current average time delay corresponding to the operation unit; comparing the current average time delay with a preset target time delay to obtain a current target deviation; calculating a PID adjustment term and determining a regulation strategy value; converting the regulation strategy value into a reconstruction bandwidth control value; determining a current service characteristic index according to the dotting data; disassembling the reconstruction bandwidth control value according to the current service characteristic index; and issuing the disassembled result to each operation unit; and checking the disassembled result based on each operation unit, and adjusting the reconstruction speed according to a checking result, so as to realize intelligent balancing of the reconstruction speed and the host IO performance.

Description

Technical Field

[0001] This disclosure relates to the field of distributed storage technology, and in particular to a reconstruction speed control method, apparatus, device, storage medium and program product based on PID control. Background Technology

[0002] In storage systems, when a storage service unit fails and recovers, the cluster automatically triggers a refactoring process. Only after the refactoring is complete will the cluster be fully healthy and able to provide complete data services. Therefore, in production environments, the faster the refactoring, the better, to complete data migration as quickly as possible while ensuring cluster performance. Data migration in distributed storage systems involves remote data retrieval and local writing, which inherently consumes the CPU, disk, and network resources of nodes. Even after the node recovers, it continues to provide storage services, and new write or read requests for business data also consume these resources. If the refactoring consumes too many resources, it will crowd out the system resources needed for business I / O, leading to a decline in production performance and potentially even business interruptions.

[0003] The reconstruction process consumes significant amounts of CPU, network bandwidth, and disk I / O resources, easily leading to resource contention with the host's normal business I / O, resulting in degraded host I / O performance and impacting business stability. Most reconstruction speed control methods in related technologies employ static rate limiting strategies, pre-setting a fixed reconstruction rate. This approach cannot dynamically adjust based on real-time system load, resulting in low reconstruction efficiency and prolonged system vulnerability. Furthermore, it fails to fully utilize system resources to accelerate reconstruction when the host is idle. Moreover, reconstruction speed cannot be infinitely adjustable, but can only be divided into several tiers, such as typical high, medium, and low tiers, each with fixed reconstruction bandwidth and IOPS, which cannot meet the demands of all environments. Adjustment is highly dependent on the experience of operations personnel; improper parameter adjustments can even impact production operations. Production environment operations fluctuate, and a single set of reconstruction parameters cannot always adapt to dynamically changing business needs. Even if the reconstruction speed can be dynamically adjusted manually, the limited number of tiers does not guarantee that the current reconstruction parameters are optimal, meaning it cannot guarantee a sufficiently fast reconstruction speed or eliminate any impact on business operations. In summary, related technologies have slow reconstruction speeds and a significant impact on business stability. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a reconfigurable speed control method, apparatus, device, storage medium, and program product based on PID control.

[0005] This disclosure provides a reconfiguration speed control method based on PID control, the method comprising: Obtain the data points of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the data points, store the local latency data in a mapping table, parse the mapping table, and obtain the current average latency of the corresponding operating unit. The current average delay is compared with the preset target delay to obtain the current target deviation. The PID adjustment term is calculated based on the current target deviation, and the control strategy value is determined based on the PID adjustment term. The control strategy value is converted into a reconstructed bandwidth control value. The current service characteristic indicators are determined based on the data points. The reconstructed bandwidth control value is then decomposed based on the current service characteristic indicators, and the decomposition results are sent to each operating unit. The disassembly results are verified by each operating unit, and the reconstruction speed is adjusted according to the verification results.

[0006] The method provided in this disclosure includes obtaining the point data of the input / output path of an operating unit, determining the local latency data of each operating unit based on the point data, storing the local latency data in a mapping table, parsing the mapping table to obtain the current average latency of the corresponding operating unit, and including: Pre-set collection points on the input / output path of each operating unit, acquire point data based on the collection points, pre-process the point data based on the operating unit, and obtain the local latency data of the corresponding operating unit based on the pre-processing result. Each operating unit reports its local latency data according to a preset cycle, and stores the reported local latency data in a mapping table. According to the preset parsing task, the local latency data of all reported operating units in the mapping table is traversed, the local latency value currently stored in the corresponding operating unit is read, and the local latency values ​​of all operating units are averaged to obtain the current average latency.

[0007] The method provided in this disclosure, based on each operating unit reporting local latency data according to a preset period, and storing the reported local latency data in a mapping table, includes: Assess the reporting status of all operational units; If it is determined that all operating units have reported, the version number of the reported local latency data is checked. If the version numbers of all local latency data are consistent, all local latency data are stored in the mapping table. If the version numbers of local latency data are inconsistent, each operating unit re-reports the local latency data. If it is determined that an operating unit has not reported, then each operating unit will re-report its local latency data.

[0008] The method provided in this disclosure compares the current average latency with a preset target latency to obtain a current target deviation, calculates a PID adjustment term based on the current target deviation, and determines a control strategy value based on the PID adjustment term, including: Subtract the current average delay from the preset target delay to obtain the current target deviation; The proportional adjustment term is obtained by multiplying the current target deviation by a preset proportional coefficient. The integral adjustment term is obtained by accumulating all historical target deviations with the current target deviation and multiplying by the sampling period. The differential adjustment term is obtained by calculating the deviation change rate based on all historical target deviations and the current target deviation. The PID adjustment term is obtained by combining the proportional adjustment term, integral adjustment term, and derivative adjustment term. The PID adjustment term is converted into a control strategy value through a preset mapping rule.

[0009] The method provided in this disclosure converts the control strategy value into a reconstructed bandwidth control value, decomposes the reconstructed bandwidth control value, and sends the decomposition result to each operating unit, including: The control strategy value is converted into a reconstructed bandwidth control value through a preset mapping function. The current business characteristic index is extracted from the data points, the current business characteristic index is parsed to determine the priority side, and the reconstructed bandwidth control value is decomposed based on the priority side to obtain the decomposition result. The disassembly results are then distributed to each operating unit.

[0010] The method provided in this disclosure, which verifies the disassembly results based on each operating unit and adjusts the reconstruction speed according to the verification results, includes: Based on the legality verification of the disassembly results by each operating unit, if the disassembly results are legal, the reconstructed bandwidth in the disassembly results is used to perform a first update on the sending queue, and the disk scheduler is updated a second time with the set value of the number of read and write operations per second. Adjust the reconstruction speed based on the first and second update results; If the disassembly result is invalid, then this update will be abandoned.

[0011] This disclosure also provides a reconfiguration speed control device based on PID control, the device comprising: The acquisition module is used to acquire the data points of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the data points, store the local latency data in a mapping table, parse the mapping table, and obtain the current average latency of the corresponding operating unit. The comparison module is used to compare the current average delay with the preset target delay to obtain the current target deviation, calculate the PID adjustment term based on the current target deviation, and determine the control strategy value based on the PID adjustment term. The conversion module is used to convert the control strategy value into a reconstructed bandwidth control value, determine the current service characteristic indicators based on the data points, decompose the reconstructed bandwidth control value based on the current service characteristic indicators, and send the decomposition results to each operating unit. The verification module is used to verify the disassembly results based on each operating unit and adjust the reconstruction speed according to the verification results.

[0012] The apparatus provided in this disclosure, wherein the acquisition module is specifically used for: Pre-set collection points on the input / output path of each operating unit, acquire point data based on the collection points, pre-process the point data based on the operating unit, and obtain the local latency data of the corresponding operating unit based on the pre-processing result. Each operating unit reports its local latency data according to a preset cycle, and stores the reported local latency data in a mapping table. According to the preset parsing task, the local latency data of all reported operating units in the mapping table is traversed, the local latency value currently stored in the corresponding operating unit is read, and the local latency values ​​of all operating units are averaged to obtain the current average latency.

[0013] The apparatus provided in this disclosure, wherein the acquisition module is specifically used for: Assess the reporting status of all operational units; If it is determined that all operating units have reported, the version number of the reported local latency data is checked. If the version numbers of all local latency data are consistent, all local latency data are stored in the mapping table. If the version numbers of local latency data are inconsistent, each operating unit re-reports the local latency data. If it is determined that an operating unit has not reported, then each operating unit will re-report its local latency data.

[0014] The apparatus provided in this disclosure embodiment, wherein the comparison module is specifically used for: Subtract the current average delay from the preset target delay to obtain the current target deviation; The proportional adjustment term is obtained by multiplying the current target deviation by a preset proportional coefficient. The integral adjustment term is obtained by accumulating all historical target deviations with the current target deviation and multiplying by the sampling period. The differential adjustment term is obtained by calculating the deviation change rate based on all historical target deviations and the current target deviation. The PID adjustment term is obtained by combining the proportional adjustment term, integral adjustment term, and derivative adjustment term. The PID adjustment term is converted into a control strategy value through a preset mapping rule.

[0015] The conversion module in the apparatus provided in this disclosure is specifically used for: The control strategy value is converted into a reconstructed bandwidth control value through a preset mapping function. The current business characteristic index is extracted from the data points, the current business characteristic index is parsed to determine the priority side, and the reconstructed bandwidth control value is decomposed based on the priority side to obtain the decomposition result. The disassembly results are then distributed to each operating unit.

[0016] The apparatus provided in this disclosure, wherein the verification module is specifically used for: Based on the legality verification of the disassembly results by each operating unit, if the disassembly results are legal, the reconstructed bandwidth in the disassembly results is used to perform a first update on the sending queue, and the disk scheduler is updated a second time with the set value of the number of read and write operations per second. Adjust the reconstruction speed based on the first and second update results; If the disassembly result is invalid, then this update will be abandoned.

[0017] This disclosure also provides an electronic device, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the PID-based reconfiguration speed control method provided in this disclosure.

[0018] This disclosure also provides a computer-readable storage medium storing a computer program for executing the PID-based reconfiguration speed control method provided in this disclosure.

[0019] The technical solution provided in this disclosure has the following advantages compared with the prior art: The PID-based reconfiguration speed control method disclosed in this embodiment acquires input / output path point data to determine local latency data, stores it in a mapping table, and parses it to obtain the current average latency. It compares the current average latency with the target latency to obtain the target deviation, calculates the PID adjustment term to determine the control strategy value, converts the control strategy value into a reconfiguration bandwidth control value, and decomposes the reconfiguration bandwidth control value based on the service characteristic indicators determined by the point data. The decomposition results are then sent to the operation units. Each unit verifies the decomposition results and adjusts the reconfiguration speed accordingly. This achieves an intelligent balance between reconfiguration speed and host I / O performance, resolves resource contention, maximizes resource utilization, proactively utilizes idle resources to accelerate reconfiguration, shortens vulnerability periods, ensures seamless service operation, maintains core service stability, adapts to service load fluctuations, automatically optimizes strategies, and reduces operational complexity. Attached Figure Description

[0020] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0021] Figure 1 A schematic flowchart of the reconfiguration speed control method based on PID control provided in the embodiments of this disclosure; Figure 2 A closed-loop flowchart of the reconfigurable speed control method based on PID control provided in the embodiments of this disclosure; Figure 3 A data flow diagram of the reconfigurable speed control method based on PID control provided in the embodiments of this disclosure; Figure 4 A schematic diagram of the reconfiguration speed control device based on PID control provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0022] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0023] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0024] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0025] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0026] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0027] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0028] To address the aforementioned issues, this disclosure provides a reconfiguration speed control method based on PID control. The method will be described below with reference to specific embodiments.

[0029] Figure 1 This is a flowchart illustrating a PID-based reconfiguration speed control method provided in an embodiment of the present disclosure. The method can be executed by a PID-based reconfiguration speed control device, which can be implemented in software and / or hardware and is generally integrated into an electronic device.

[0030] Example 1: This embodiment of the present disclosure provides a reconfiguration speed control method based on PID control, comprising: S101: Obtain the point data of the input / output path of the operation unit, determine the local latency data of each operation unit according to the point data, store the local latency data in the mapping table, parse the mapping table, and obtain the current average latency of the corresponding operation unit. S102: Compare the current average delay with the preset target delay to obtain the current target deviation, calculate the PID adjustment term based on the current target deviation, and determine the control strategy value based on the PID adjustment term; S103: Convert the control strategy value into a reconstructed bandwidth control value, determine the current service characteristic indicators based on the data points, decompose the reconstructed bandwidth control value based on the current service characteristic indicators, and send the decomposition results to each operating unit. S104: Verify the disassembly results based on each operating unit, and adjust the reconstruction speed according to the verification results.

[0031] In this embodiment, the operating unit is a basic working node in the distributed storage system that independently performs data read and write operations, and is responsible for handling specific input / output requests. Each operating unit has independent computing, storage, and network resources, undertakes background tasks such as data reconstruction and migration, and provides business data services to the outside world. Multiple operating units work together to form a distributed cluster, jointly completing data storage and access functions.

[0032] In this embodiment, the input / output path is the complete processing channel for data within the operating unit from receiving a request to completing a response, including request parsing, data reading, buffer transfer, disk access, and network transmission. Each step in this path consumes system resources and generates processing latency, making it a critical path for measuring storage performance and the core location for collecting performance data.

[0033] In this embodiment, the data points are the raw performance information recorded by the data collection points, including fields such as the start time, end time, operation type (read / write), data size, and operation time of a single input / output operation.

[0034] In this embodiment, the local latency data is the performance statistics of the node obtained by the operating unit after preprocessing, which usually includes indicators such as average latency, maximum latency, and percentile latency.

[0035] In this embodiment, the mapping table is a key-value data structure in the master node's memory used to store the latest reported data from each operating unit. The operating unit identifier is used as the key, and the most recently reported local latency data of that unit is used as the value. The mapping table always maintains the latest state of each unit.

[0036] In this embodiment, the current average latency is the arithmetic mean calculated by the master node after traversing the local latency values ​​of all valid units in the mapping table. The formula is the sum of the latency values ​​of all units divided by the number of units.

[0037] In this embodiment, the current target deviation is the difference between the current average latency and the preset target latency, calculated as the target latency minus the current average latency. This value reflects the gap between the system's current performance and the ideal target: a positive value indicates the system is too fast (latency lower than the target), and a negative value indicates the system is too slow (latency higher than the target). The current target deviation is the only input signal for the PID controller, and all subsequent calculations are based on this value.

[0038] In this embodiment, the PID adjustment term is the sum of the proportional adjustment term, integral adjustment term, and derivative adjustment term, representing the abstract adjustment force output by the PID controller.

[0039] In this embodiment, the control strategy value is a specific control instruction that can be directly issued to the operating unit after being transformed by the mapping rule. It usually includes the reconstructed bandwidth target value (MB / s) and the corresponding IOPS target value (times / second).

[0040] In this embodiment, the reconfiguration bandwidth control value is a single numerical value obtained after transformation by a mapping function. It represents the macroscopic command of the reconfiguration speed desired by the master control node, and the unit is usually MB / s. This value does not distinguish between bandwidth and IOPS dimensions; it only indicates the overall speed adjustment direction and intensity, and serves as an intermediate control quantity connecting the PID decision layer and the parameter decomposition layer.

[0041] In this embodiment, the current business characteristic indicators are key parameters extracted from the data points that reflect the characteristics of the business load. These mainly include average input / output size (reflecting whether the business is throughput-intensive or IOPS-intensive), read / write ratio, concurrency, etc., which are used to determine the type of business that the system is currently processing and its resource consumption characteristics.

[0042] In this embodiment, the decomposition process breaks down the single reconfigurable bandwidth control value into the calculation of two specific execution parameters. Combining the current service characteristic indicators and the average input / output size, the corresponding IOPS value is calculated using the formula "IOPS = Bandwidth value / Average input / output size". At the same time, the bandwidth value and IOPS value are independently verified and limited to ensure that both parameters are valid.

[0043] In this embodiment, the disassembly result is the final execution instruction obtained through the disassembly process, which includes two specific parameters: the reconstruction bandwidth value and the corresponding set value of the number of read and write operations per second. These two parameters together constitute a complete reconstruction speed constraint, which is used to control the network throughput and disk operation frequency, respectively, and is the actual execution command issued to the operating unit.

[0044] In this embodiment, the legality of the disassembly result is verified by the operating unit. If it is legal, the transmission queue is updated using the reconstruction bandwidth, and the disk scheduler is updated with the set value of the number of read and write operations per second, and the reconstruction speed is adjusted accordingly. If it is illegal, the update is abandoned.

[0045] In this embodiment, such as Figure 2 As shown, each operational unit (A, B, C) includes four processing steps: request parsing, data retrieval, data persistence to disk, and metadata update. After completing local processing, each unit reports its latency data (delay_A, delay_B, delay_C) to the leader node. The leader node is responsible for summarizing and analyzing this reported latency data to provide a basis for subsequent control decisions.

[0046] In this embodiment, such as Figure 3 As shown, the system first collects IO data from each unit and refreshes the local latency, then periodically reports the information to the main control node. The main control node obtains the control value and determines its validity: if valid, it updates the reconstruction bandwidth and IOPS; if invalid, it resets the time parameters and abandons the update. Next, it analyzes the reported latency data. Once all units have reported and their version numbers are consistent, a new control value is calculated using PID control and sent to each unit, entering the next cycle to achieve dynamic adjustment of the reconstruction speed.

[0047] The working principle and beneficial effects of this embodiment are as follows: Input / output path tracking data is acquired to determine local latency data, stored in a mapping table, and parsed to obtain the current average latency. The current average latency is compared with the target latency to obtain the target deviation. A PID adjustment term is calculated to determine the control strategy value, which is then converted to a reconstructed bandwidth control value. The reconstructed bandwidth control value is decomposed based on the service characteristic indicators determined by the tracking data, and the decomposition results are sent to the operation units. Each unit verifies the decomposition results and adjusts the reconstruction speed accordingly. This achieves an intelligent balance between reconstruction speed and host I / O performance, resolves resource contention, maximizes resource utilization, proactively utilizes idle resources to accelerate reconstruction, shortens the vulnerability period, ensures seamless service operation, maintains core business stability, adapts to service load fluctuations, automatically optimizes strategies, and reduces operational complexity.

[0048] Example 2: The method provided in this embodiment of the present disclosure obtains the point data of the input / output path of the operating unit, determines the local latency data of each operating unit based on the point data, stores the local latency data in a mapping table, parses the mapping table, and obtains the current average latency of the corresponding operating unit, including: Pre-set collection points on the input / output path of each operating unit, acquire point data based on the collection points, pre-process the point data based on the operating unit, and obtain the local latency data of the corresponding operating unit based on the pre-processing result. Each operating unit reports its local latency data according to a preset cycle, and stores the reported local latency data in a mapping table. According to the preset parsing task, the local latency data of all reported operating units in the mapping table is traversed, the local latency value currently stored in the corresponding operating unit is read, and the local latency values ​​of all operating units are averaged to obtain the current average latency.

[0049] In this embodiment, the collection points are pre-set code embedding locations on the input / output path, used to automatically trigger the recording of operation information as data flows through. Collection points are typically set at the entry and exit points of critical processing stages, such as the time of request arrival, the time of disk read start, and the time of operation completion. By comparing the timestamps of different collection points, the processing time of each stage can be calculated.

[0050] In this embodiment, preprocessing is the process by which the operating unit cleans, aggregates, and performs statistical calculations on massive amounts of raw data. This includes operations such as removing abnormal noise values, filtering invalid records, and calculating the average or percentile values ​​within a given period.

[0051] In this embodiment, the preset period is a fixed time interval at which the operating unit reports local latency data to the master control node, such as once per second or every two seconds. The choice of period length needs to balance real-time performance and system overhead: too short a period will increase network and master control load, while too long a period may lead to sluggish control response and inability to respond to changes in service load in a timely manner.

[0052] In this embodiment, the local latency value is the specific latency value stored in the mapping table, that is, the core indicator (such as average latency) in the latest local latency data reported by each operating unit. This value represents the actual response speed of the unit at the current moment and is the basic input unit for the master control node to perform global average calculation and subsequent PID control.

[0053] The working principle and beneficial effects of this embodiment are as follows: Data is collected at preset acquisition points along the input / output paths of the operating unit. Based on this data, the operating unit preprocesses the data to obtain local latency data, which is then reported at a preset period and stored in a mapping table. According to a preset parsing task, the local latency data of all reported units in the mapping table is traversed, the currently stored local latency value is read, and the average local latency values ​​of all operating units are calculated to obtain the current average latency. This accurately collects real-time system performance data, eliminates the impact of single-point fluctuations, truly reflects the cluster load status, and provides precise input for subsequent dynamic speed adjustment.

[0054] Example 3: The method provided in this embodiment of the present disclosure, based on each operating unit reporting the local latency data according to a preset period, and storing the reported local latency data in a mapping table, includes: Assess the reporting status of all operational units; If it is determined that all operating units have reported, the version number of the reported local latency data is checked. If the version numbers of all local latency data are consistent, all local latency data are stored in the mapping table. If the version numbers of local latency data are inconsistent, each operating unit re-reports the local latency data. If it is determined that an operating unit has not reported, then each operating unit will re-report its local latency data.

[0055] In this embodiment, the reporting status refers to the master control node's status check result regarding whether each operating unit has completed its current round of data reporting. The master control node determines whether all units have submitted their local latency data on time by comparing the list of units that have received data with the list of all operating units in the cluster. The reporting status is divided into two states: "all reported" and "some not reported".

[0056] In this embodiment, version number determination refers to the process by which the master control node performs a consistency check on the version identifiers carried by all reported local latency data. The version number represents an iteration marker for data reconstruction or modification, used to confirm whether all operating units are working based on the same data baseline. If the version numbers are consistent, it means that the data snapshots processed by each unit are the same, and subsequent calculations can proceed; if they are inconsistent, re-reporting needs to be triggered to avoid errors in calculation results due to different data baselines.

[0057] The working principle and beneficial effects of this embodiment are as follows: The reporting status of all operating units is determined. If all have reported and their version numbers are consistent, the local latency data is stored in the mapping table; if the version numbers are inconsistent or some have not been reported, a re-reporting is triggered. This ensures that the latency data involved in the calculation comes from the same data benchmark, avoiding decision-making biases due to data version discrepancies and guaranteeing control accuracy.

[0058] Example 4: The method provided in this embodiment of the present disclosure compares the current average latency with a preset target latency to obtain the current target deviation, calculates a PID adjustment term based on the current target deviation, and determines a control strategy value based on the PID adjustment term, including: Subtract the current average delay from the preset target delay to obtain the current target deviation; The proportional adjustment term is obtained by multiplying the current target deviation by a preset proportional coefficient. The integral adjustment term is obtained by accumulating all historical target deviations with the current target deviation and multiplying by the sampling period. The differential adjustment term is obtained by calculating the deviation change rate based on all historical target deviations and the current target deviation. The PID adjustment term is obtained by combining the proportional adjustment term, integral adjustment term, and derivative adjustment term. The PID adjustment term is converted into a control strategy value through a preset mapping rule.

[0059] In this embodiment, the proportional adjustment term is obtained by multiplying the current target deviation by a proportional coefficient. The proportional adjustment term is responsible for responding instantly to the current deviation; the larger the deviation, the greater the adjustment. It determines the system's response speed and is the most important and direct component of the PID output, capable of quickly reducing the current error.

[0060] In this embodiment, the integral adjustment term is obtained by multiplying the sum of all historical target deviations by the sampling period and then by the integral coefficient. The integral adjustment term is responsible for eliminating the long-term accumulated steady-state error. When there is a continuous small deviation in the system and the proportional term is unable to correct it, the integral term will gradually increase the output until the deviation is completely eliminated.

[0061] In this embodiment, the differential adjustment term is calculated based on the rate of change of deviation. The differential adjustment term is responsible for predicting the trend of deviation change. When the deviation is rapidly increasing, it outputs a reverse adjustment amount to suppress the deterioration trend. When the deviation is rapidly decreasing, it reduces the adjustment force in advance to prevent overshoot, thus playing a damping and predictive role.

[0062] In this embodiment, the mapping rule is a transformation relationship that converts abstract PID adjustment terms into control strategy values ​​with actual physical meaning. It is typically a linear mapping function, such as "bandwidth change per unit PID adjustment". The mapping rule also includes safety limiting processing to ensure that the converted values ​​do not exceed hardware capabilities or management thresholds.

[0063] In this embodiment, ,in, Indicates the proportional adjustment item; Indicates the integral adjustment term; Represents the differential adjustment term; Indicates target deviation; Indicates the sampling period; Indicates integral gain; Indicates proportional gain; This represents the differential gain.

[0064] The working principle and beneficial effects of this embodiment are as follows: the target deviation is obtained by subtracting the current average delay from the target delay. Based on the target deviation, the proportional term, integral term, and derivative term are calculated and combined to obtain the PID adjustment term. The adjustment term is converted into a control strategy value through mapping rules, thereby realizing precise dynamic adjustment of the reconstruction speed, eliminating static deviation, predicting the trend of change, ensuring fast and stable speed regulation response, and adapting to load fluctuations.

[0065] Example 5: The method provided in this embodiment converts the regulation strategy value into a reconfigurable bandwidth control value, decomposes the reconfigurable bandwidth control value, and distributes the decomposition results to each operating unit, including: The control strategy value is converted into a reconstructed bandwidth control value through a preset mapping function. The current business characteristic index is extracted from the data points, the current business characteristic index is parsed to determine the priority side, and the reconstructed bandwidth control value is decomposed based on the priority side to obtain the decomposition result. The disassembly results are then distributed to each operating unit.

[0066] In this embodiment, the mapping function is a mathematical transformation relationship that converts the abstract PID adjustment term into a specific reconstructed bandwidth control value. It is usually a linear function, such as new bandwidth = current bandwidth + (PID adjustment term × conversion coefficient). The mapping function also includes boundary limiting processing to ensure that the converted value does not exceed the preset minimum and maximum bandwidth range, thus ensuring the safe operation of the system.

[0067] In this embodiment, the priority side determines the resource allocation tendency based on current business characteristic indicators, deciding which dimension to prioritize when decomposing and reconstructing bandwidth control values. If the average input / output is high, bandwidth accuracy is prioritized; if the average input / output is low, IOPS accuracy is prioritized; if the load is too high, both dimensions are conservatively considered to ensure that the decomposition results adapt to actual business needs.

[0068] The working principle and beneficial effects of this embodiment are as follows: The control strategy value is transformed by a mapping function to reconstruct the bandwidth control value. Current business characteristic indicators are extracted from the data points, and the priority side is determined through analysis. Based on this, the decomposition result of the reconstructed bandwidth control value is broken down and sent to the operation unit. This achieves decoupled control of bandwidth and IOPS, dynamically allocates resources according to business characteristics, improves speed regulation accuracy, avoids resource waste, and ensures business performance.

[0069] Example 6: The method provided in this embodiment of the present disclosure verifies the disassembly results based on each operating unit and adjusts the reconstruction speed according to the verification results, including: Based on the legality verification of the disassembly results by each operating unit, if the disassembly results are legal, the reconstructed bandwidth in the disassembly results is used to perform a first update on the sending queue, and the disk scheduler is updated a second time with the set value of the number of read and write operations per second. Adjust the reconstruction speed based on the first and second update results; If the disassembly result is invalid, then this update will be abandoned.

[0070] In this embodiment, the legality verification is a multi-dimensional inspection process performed by the operating unit on the received disassembly results, including instruction format integrity verification, timestamp timeliness verification, numerical range reasonableness check, such as whether the bandwidth exceeds the network card limit, whether the IOPS exceeds the disk capacity, and whether the management threshold is touched, such as the preset maximum reconstruction ratio.

[0071] In this embodiment, the sending queue is a buffer in the network protocol stack used to temporarily store data packets to be sent, located in the network card driver or operating system kernel. Reconstructed data first enters this queue before entering the network, and is then retrieved and sent by the flow control module at a set rate. The sending queue is a key location for controlling network throughput; bandwidth management is achieved by limiting the queue's dequeue rate.

[0072] In this embodiment, the first update is a parameter refresh operation performed by the operating unit on the network sending queue using the reconstructed bandwidth value in the disassembly result. This includes calling the flow control interface to modify the queue rate limit and updating the token bucket parameters. The first update directly constrains the network egress bandwidth occupied by the reconstructed data per unit time, preventing the reconstructed traffic from crowding out the network resources of service I / O.

[0073] In this embodiment, the disk scheduler is a core module in the operating system kernel located between the file system and the block device driver. It is responsible for managing the queuing order and timing of all read and write requests sent to the disk. The scheduler optimizes disk access efficiency by merging adjacent requests, sorting to reduce seek time, and controlling concurrency depth, while also supporting IOPS limits for specific processes or tasks.

[0074] In this embodiment, the second update is a parameter refresh operation performed by the operating unit on the disk scheduler using the read / write operations per second setting value from the disassembly results. This includes updating the IOPS rate limit value for the reconstruction task in the scheduler, adjusting priority weights, or modifying concurrency control parameters. The second update directly constrains the disk operation frequency initiated by the reconstruction task, protecting the response speed of business I / O.

[0075] In this embodiment, the adjustment of the reconstruction speed is based on the combined result of the first and second updates, representing the change in the actual execution rate of the reconstruction task. Network layer bandwidth limiting controls data throughput, and disk layer IOPS limiting controls operation frequency. Together, they ensure the reconstruction task runs at the target speed calculated by the PID controller, achieving precise speed control.

[0076] The working principle and beneficial effects of this embodiment are as follows: The operating unit verifies the legality of the disassembly result. If legal, the transmission queue is updated using the reconstruction bandwidth, and the disk scheduler is updated with a set value for the number of read / write operations per second, thereby adjusting the reconstruction speed. If illegal, the update is abandoned. This ensures secure execution of instructions, precise control of network and disk resources, avoids system anomalies caused by illegal instructions, and guarantees reliable and effective adjustment of the reconstruction speed.

[0077] To implement the above embodiments, this disclosure also proposes a reconfiguration speed control device based on PID control.

[0078] Figure 4This is a schematic diagram of a PID-based reconfiguration speed control device provided in an embodiment of this disclosure. The device 200 can be implemented by software and / or hardware, and is generally integrated into an electronic device. Figure 4 As shown, the device 200 includes: an acquisition module 201, a conversion module 202, a display module 203, and a verification module 204, wherein, The acquisition module 201 is used to acquire the data points of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the data points, store the local latency data in a mapping table, parse the mapping table, and obtain the current average latency of the corresponding operating unit. The comparison module 202 is used to compare the current average delay with the preset target delay to obtain the current target deviation, calculate the PID adjustment term based on the current target deviation, and determine the control strategy value based on the PID adjustment term. The conversion module 203 is used to convert the control strategy value into a reconstructed bandwidth control value, determine the current service characteristic indicators based on the data points, decompose the reconstructed bandwidth control value based on the current service characteristic indicators, and send the decomposition results to each operating unit. The verification module 204 is used to verify the disassembly results based on each operating unit and adjust the reconstruction speed according to the verification results.

[0079] The apparatus provided in this disclosure, wherein the acquisition module 201 is specifically used for: Pre-set collection points on the input / output path of each operating unit, acquire point data based on the collection points, pre-process the point data based on the operating unit, and obtain the local latency data of the corresponding operating unit based on the pre-processing result. Each operating unit reports its local latency data according to a preset cycle, and stores the reported local latency data in a mapping table. According to the preset parsing task, the local latency data of all reported operating units in the mapping table is traversed, the local latency value currently stored in the corresponding operating unit is read, and the local latency values ​​of all operating units are averaged to obtain the current average latency.

[0080] The apparatus provided in this disclosure, wherein the acquisition module 201 is specifically used for: Assess the reporting status of all operational units; If it is determined that all operating units have reported, the version number of the reported local latency data is checked. If the version numbers of all local latency data are consistent, all local latency data are stored in the mapping table. If the version numbers of local latency data are inconsistent, each operating unit re-reports the local latency data. If it is determined that an operating unit has not reported, then each operating unit will re-report its local latency data.

[0081] The apparatus provided in this disclosure, wherein the comparison module 202 is specifically used for: Subtract the current average delay from the preset target delay to obtain the current target deviation; The proportional adjustment term is obtained by multiplying the current target deviation by a preset proportional coefficient. The integral adjustment term is obtained by accumulating all historical target deviations with the current target deviation and multiplying by the sampling period. The differential adjustment term is obtained by calculating the deviation change rate based on all historical target deviations and the current target deviation. The PID adjustment term is obtained by combining the proportional adjustment term, integral adjustment term, and derivative adjustment term. The PID adjustment term is converted into a control strategy value through a preset mapping rule.

[0082] The conversion module 203 in the apparatus provided in this embodiment is specifically used for: The control strategy value is converted into a reconstructed bandwidth control value through a preset mapping function. The current business characteristic index is extracted from the data points, the current business characteristic index is parsed to determine the priority side, and the reconstructed bandwidth control value is decomposed based on the priority side to obtain the decomposition result. The disassembly results are then distributed to each operating unit.

[0083] The apparatus provided in this disclosure, wherein the verification module 204 is specifically used for: Based on the legality verification of the disassembly results by each operating unit, if the disassembly results are legal, the reconstructed bandwidth in the disassembly results is used to perform a first update on the sending queue, and the disk scheduler is updated a second time with the set value of the number of read and write operations per second. Adjust the reconstruction speed based on the first and second update results; If the disassembly result is invalid, then this update will be abandoned.

[0084] The PID-based reconfiguration speed control device provided in this disclosure can execute the PID-based reconfiguration speed control method provided in any embodiment of this disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0085] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program / instruction, which, when executed by a processor, implements the PID-based reconfiguration speed control method in the above embodiments.

[0086] Figure 5This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0087] The following is a detailed reference. Figure 5 The diagram illustrates a structural schematic suitable for implementing the electronic device 300 in the embodiments of this disclosure. The electronic device 300 in the embodiments of this disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0088] like Figure 5 As shown, the electronic device 300 may include a processor (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a memory 308 into a random access memory (RAM) 303. The RAM 303 also stores various programs and data required for the operation of the electronic device 300. The processor 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0089] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 300 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0090] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from memory 308, or installed from ROM 302. When the computer program is executed by processor 301, it performs the functions defined in the PID-based reconfiguration speed control method of embodiments of this disclosure.

[0091] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0092] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0093] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0094] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the aforementioned PID-based reconfiguration speed control method.

[0095] Electronic devices can be programmed with computer program code in one or more programming languages ​​or combinations thereof to perform the operations of this disclosure. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0097] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0098] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0099] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0100] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0101] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0102] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A reconfigurable speed control method based on PID control, characterized in that, include: Obtain the data points of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the data points, store the local latency data in a mapping table, parse the mapping table, and obtain the current average latency of the corresponding operating unit. The current average delay is compared with the preset target delay to obtain the current target deviation. The PID adjustment term is calculated based on the current target deviation, and the control strategy value is determined based on the PID adjustment term. The control strategy value is converted into a reconstructed bandwidth control value. The current service characteristic indicators are determined based on the data points. The reconstructed bandwidth control value is then decomposed based on the current service characteristic indicators, and the decomposition results are sent to each operating unit. The disassembly results are verified by each operating unit, and the reconstruction speed is adjusted according to the verification results.

2. The method according to claim 1, characterized in that, Acquire the point data of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the point data, store the local latency data in a mapping table, parse the mapping table to obtain the current average latency of the corresponding operating unit, including: Pre-set collection points on the input / output path of each operating unit, acquire point data based on the collection points, pre-process the point data based on the operating unit, and obtain the local latency data of the corresponding operating unit based on the pre-processing result. Each operating unit reports its local latency data according to a preset cycle, and stores the reported local latency data in a mapping table. According to the preset parsing task, the local latency data of all reported operating units in the mapping table is traversed, the local latency value currently stored in the corresponding operating unit is read, and the local latency values ​​of all operating units are averaged to obtain the current average latency.

3. The method according to claim 2, characterized in that, Based on each operating unit reporting the local latency data according to a preset period, the reported local latency data is stored in a mapping table, including: Assess the reporting status of all operational units; If it is determined that all operating units have reported, the version number of the reported local latency data is checked. If the version numbers of all local latency data are consistent, all local latency data are stored in the mapping table. If the version numbers of local latency data are inconsistent, each operating unit re-reports the local latency data. If it is determined that an operating unit has not reported, then each operating unit will re-report its local latency data.

4. The method according to claim 1, characterized in that, The current average latency is compared with the preset target latency to obtain the current target deviation. A PID adjustment term is calculated based on the current target deviation, and a control strategy value is determined based on the PID adjustment term, including: Subtract the current average delay from the preset target delay to obtain the current target deviation; The proportional adjustment term is obtained by multiplying the current target deviation by a preset proportional coefficient. The integral adjustment term is obtained by accumulating all historical target deviations with the current target deviation and multiplying by the sampling period. The differential adjustment term is obtained by calculating the deviation change rate based on all historical target deviations and the current target deviation. The PID adjustment term is obtained by combining the proportional adjustment term, integral adjustment term, and derivative adjustment term. The PID adjustment term is converted into a control strategy value through a preset mapping rule.

5. The method according to claim 1, characterized in that, The control strategy value is converted into a reconstructed bandwidth control value. The reconstructed bandwidth control value is then broken down, and the breakdown results are distributed to each operating unit, including: The control strategy value is converted into a reconstructed bandwidth control value through a preset mapping function. The current business characteristic index is extracted from the data points, the current business characteristic index is parsed to determine the priority side, and the reconstructed bandwidth control value is decomposed based on the priority side to obtain the decomposition result. The disassembly results are then distributed to each operating unit.

6. The method according to claim 1, characterized in that, Based on the verification of the disassembly results by each operating unit, the reconstruction speed is adjusted according to the verification results, including: Based on the legality verification of the disassembly results by each operating unit, if the disassembly results are legal, the reconstructed bandwidth in the disassembly results is used to perform a first update on the sending queue, and the disk scheduler is updated a second time with the set value of the number of read and write operations per second. Adjust the reconstruction speed based on the first and second update results; If the disassembly result is invalid, then this update will be abandoned.

7. A reconfigurable speed control device based on PID control, the device comprising: The acquisition module is used to acquire the data points of the input / output paths of the operating unit, determine the local latency data of each operating unit based on the data points, store the local latency data in a mapping table, parse the mapping table, and obtain the current average latency of the corresponding operating unit. The comparison module is used to compare the current average delay with the preset target delay to obtain the current target deviation, calculate the PID adjustment term based on the current target deviation, and determine the control strategy value based on the PID adjustment term. The conversion module is used to convert the control strategy value into a reconstructed bandwidth control value, determine the current service characteristic indicators based on the data points, decompose the reconstructed bandwidth control value based on the current service characteristic indicators, and send the decomposition results to each operating unit. The verification module is used to verify the disassembly results based on each operating unit and adjust the reconstruction speed according to the verification results.

8. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the steps of the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program / instruction thereon, which, when executed by a processor, implements the steps of the method described in any one of claims 1-6.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-6.

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