A wideband active phase shifter based on inductive compensation

Abstract

The present application relates to a kind of wideband active phase shifter based on inductive compensation, including input balun, quadrature signal generator, inductive compensation network, adder and output balun in series in turn, and 7-bit DAC connected with adder, can realize 360 ° phase shift range;The input balun and output balun all adopt two-stage differential active balun structure;The quadrature signal generator is three-stage Type-II PPF;The inductive compensation network is used to generate peak gain at high frequency point, widen working frequency band and do not affect phase shift accuracy;The adder adopts Gilbert unit and controls phase change by digital signal input mode;7-bit DAC is used to provide different bias voltage for Gilbert unit, to control current size and realize vector modulation.The present application introduces inductive compensation network between quadrature signal generator and vector modulation unit, effectively widen working bandwidth, realize gain flattening, while maintaining high phase shift accuracy and low amplitude error.

Description

Technical Field

[0001] This invention relates to the field of phase shifters, and more specifically to a broadband active phase shifter based on inductive compensation. Background Technology

[0002] Phased array technology is highly adaptable to modern multi-scenario needs such as phased array radar, high-speed communication applications, and millimeter-wave automotive radar due to its flexibility in beam control, multi-task integration capabilities, environmental adaptability, and overall system performance. With the rapid development of III-V technology, the performance of T / R components has been significantly improved, and costs have become increasingly lower. Phased array technology is gradually transitioning from military to civilian applications. Facing the urgent needs of the military in dealing with complex battlefield environments and the performance requirements of the civilian sector for adapting to diverse scenarios, wide operating bandwidth is an indispensable part of phased array technology.

[0003] Phased array technology achieves efficient and rapid beamforming and flexible control of array sidelobes by controlling the beam pointing of the array antenna through beam scanning. Therefore, phase shifters used for phase control have become an important component of phased array systems.

[0004] GaAs technology is relatively expensive, while CMOS technology offers advantages such as low cost, low power consumption, high yield, mass production capability, and easy integration with CMOS digital circuits. This makes CMOS technology particularly suitable for low-cost, low-power applications in mobile communications. Therefore, research on phase shifter design based on CMOS technology is crucial.

[0005] In the field of active phase shifters, the performance of the phase shifter directly determines the performance of the entire phased array system. It is responsible for controlling the phase of each antenna element, causing the beam to move in different directions. In large-scale millimeter-wave phased arrays, high amplitude and phase accuracy of the phase shifter is required to avoid complex amplitude and phase calibration processes.

[0006] The rapid development of high-capacity communication and radar detection has placed higher demands on phase shifters, including high phase resolution, small phase error, low insertion loss, and wider bandwidth. Active phase shifters have become the main candidate architecture for phased array systems due to their advantages of high precision, positive gain, and compatibility with digital control.

[0007] As operating frequencies reach 6 GHz and above, the bandwidth of active phase shifters becomes limited, resulting in a negative gain slope and a significant deterioration in phase-shifting accuracy. Traditional active phase shifter architectures typically exhibit non-flat gain, necessitating gain compensation for other circuits in phased array systems, such as driver amplifiers, greatly increasing design complexity. Consequently, their performance no longer meets the design requirements for high-frequency phase shifters.

[0008] Therefore, there is an urgent need for a new broadband active phase shifter architecture that can effectively expand the operating bandwidth and achieve gain flattening without degrading phase shifting accuracy. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a broadband active phase shifter based on inductive compensation. This phase shifter effectively widens the operating bandwidth and achieves gain flattening by introducing an inductive compensation network between the quadrature signal generator and the vector modulation unit, while maintaining high phase shift accuracy and low amplitude error.

[0010] To achieve the above objectives, the present invention adopts the following technical solution: a broadband active phase shifter based on inductive compensation, comprising an input balun, an orthogonal signal generator, an inductive compensation network, an adder, and an output balun connected in series, and a 7-bit DAC connected to the adder, which can achieve a 360° phase shift range;

[0011] Both the input balun and the output balun adopt a two-stage differential active balun structure. The input balun is used to convert the single-ended signal at the input end into a differential signal, and the output balun is used to convert the differential signal at the output end into a single-ended signal.

[0012] The orthogonal signal generator is a three-stage Type-II PPF used to convert differential signals into orthogonal signals;

[0013] The inductive compensation network is used to generate peak gain at high frequencies, widening the operating bandwidth without affecting phase shift accuracy.

[0014] The adder uses a Gilbert cell and controls the phase change through digital signal input. As a vector modulation module based on the Gilbert cell, it performs polarity selection on orthogonal signals and realizes vector synthesis.

[0015] The 7-bit DAC is used to provide different bias voltages to the Gilbert unit in order to control the current magnitude and achieve vector modulation.

[0016] Further, the input balun includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a reference current source; the RF input terminal is connected to the gate of the third transistor via the first capacitor, the gate of the third transistor is also grounded via the first resistor, the drain of the third transistor is connected to the source of the fifth transistor, and the gate of the third transistor is connected to the drain of the fifth transistor via the second resistor and the third capacitor; the drain of the fifth transistor is also connected to the power supply terminal via the third resistor and a first RF output terminal is led out from the drain of the fifth transistor; in the symmetrical branch, the gate of the fourth transistor is grounded via the second capacitor, and the fourth... The drain of the transistor is connected to the source of the sixth transistor. The drain of the sixth transistor is connected to the power supply terminal via the fourth resistor and a second RF output terminal is led out from the drain of the sixth transistor. The gates of the fifth and sixth transistors are connected to the first bias voltage terminal and grounded via the fourth capacitor. The first and second transistors form a current mirror structure, with their gates shorted to each other. The drain of the first transistor is connected to the reference current source and shorted to its gate. The source of the first transistor is grounded, and the source of the second transistor is grounded. The drain of the second transistor is connected to the sources of the third and fourth transistors, providing bias current for the third and fourth transistors. All grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal provides the operating power supply voltage for each device.

[0017] Furthermore, the third transistor is the same size as the fourth transistor, and the fifth transistor is the same size as the sixth transistor.

[0018] Furthermore, the three-stage Type-II PPF consists of a first-stage PPF, a second-stage PPF, and a third-stage PPF cascaded sequentially. The first-stage PPF is composed of a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor connected in series. The positive terminal of the first RF input is simultaneously connected to one end of the fifth resistor, one end of the fifth capacitor, one end of the sixth resistor, and one end of the sixth capacitor. The negative terminal of the first RF input is simultaneously connected to one end of the seventh resistor, one end of the seventh capacitor, one end of the eighth resistor, and one end of the eighth capacitor. The other end of the fifth capacitor is connected to the other end of the sixth resistor, the other end of the sixth capacitor is connected to the other end of the seventh resistor, the other end of the seventh capacitor is connected to the other end of the eighth resistor, and the other end of the eighth capacitor is connected to the other end of the fifth resistor.

[0019] The second-stage PPF consists of resistors 9, 10, 11, and 12 connected in series with capacitors 9, 10, 11, and 12. The connection point between capacitor 8 and resistor 5 is simultaneously connected to one end of resistor 9 and one end of capacitor 9. The connection point between capacitor 5 and resistor 6 is simultaneously connected to one end of resistor 10 and one end of capacitor 10. The connection point between capacitor 6 and resistor 7 is simultaneously connected to one end of resistor 11 and one end of capacitor 11. The connection point between capacitor 7 and resistor 8 is simultaneously connected to one end of resistor 12 and one end of capacitor 12. The other end of capacitor 9 is connected to the other end of resistor 10. The other end of capacitor 10 is connected to the other end of resistor 11. The other end of capacitor 11 is connected to the other end of resistor 12. The other end of capacitor 12 is connected to the other end of resistor 9.

[0020] The third-stage PPF consists of resistors 13, 14, 15, and 16 connected in series with capacitors 13, 14, 15, and 16. The connection point between capacitor 12 and resistor 9 is simultaneously connected to one end of resistor 13 and capacitor 13. The connection point between capacitor 9 and resistor 10 is simultaneously connected to one end of resistor 14 and capacitor 14. The connection point between capacitor 10 and resistor 11 is simultaneously connected to one end of resistor 15 and capacitor 15. The connection point between capacitor 11 and resistor 12 is simultaneously connected to one end of resistor 16 and capacitor 16. The other end of capacitor 16 is connected to the other end of resistor 13 and leads to the first output terminal. The other end of capacitor 13 is connected to the other end of resistor 14 and leads to the second output terminal. The other end of capacitor 14 is connected to the other end of resistor 15 and leads to the third output terminal. The other end of capacitor 15 is connected to the other end of resistor 16 and leads to the fourth output terminal.

[0021] Furthermore, the resistance values ​​of the fifth to eighth resistors are equal, the capacitance values ​​of the fifth to eighth capacitors are equal, the resistance values ​​of the ninth to twelfth resistors are equal, the capacitance values ​​of the ninth to twelfth capacitors are equal, the resistance values ​​of the thirteenth to sixteenth resistors are equal, and the capacitance values ​​of the thirteenth to sixteenth capacitors are equal.

[0022] Furthermore, the inductive compensation network includes a first inductor, a second inductor, a third inductor, and a fourth inductor; wherein, the first inductor is connected in series between the first output terminal of the three-stage Type-II PPF and the corresponding signal input terminal of the adder; the second inductor is connected in series between the second output terminal of the three-stage Type-II PPF and the corresponding signal input terminal of the adder; the third inductor is connected in series between the third output terminal of the three-stage Type-II PPF and the corresponding signal input terminal of the adder; and the fourth inductor is connected in series between the fourth output terminal of the three-stage Type-II PPF and the corresponding signal input terminal of the adder; each inductor is used to achieve signal transmission matching between the three-stage Type-II PPF and the adder.

[0023] Furthermore, the adder is composed of a fifth inductor, a sixth inductor, a seventeenth capacitor, an eighteenth capacitor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a first single-pole double-throw switch, a second single-pole double-throw switch, a third single-pole double-throw switch, a fourth single-pole double-throw switch, a bias voltage source, and a bias current source;

[0024] Transistors 13 through 20 are of equal size; one end of the fifth inductor is connected to the power supply and then to the first RF output terminal via capacitor 17, while the other end of the fifth inductor is simultaneously connected to the drains of transistors 13, 15, 17, and 19; one end of the sixth inductor is connected to the power supply and then to the second RF output terminal via capacitor 18, while the other end of the sixth inductor is simultaneously connected to the drains of transistors 14, 16, 18, and 20; the first signal input terminal is simultaneously connected to the gates of transistors 13 and 14, the second signal input terminal is simultaneously connected to the gates of transistors 15 and 16, the third signal input terminal is simultaneously connected to the gates of transistors 17 and 18, and the fourth signal input terminal is simultaneously connected to the gates of transistors 19 and 20; the source of transistor 13 is connected to the source of transistor 16 and then to the drain of transistor 9; the source of transistor 14 is connected to the source of transistor 15 and then to the drain of transistor 10. The source of the seventeenth transistor is connected to the source of the twentieth transistor and to the drain of the eleventh transistor; the source of the eighteenth transistor is connected to the source of the nineteenth transistor and to the drain of the twelfth transistor; the gate of the ninth transistor is connected to the first single-pole double-throw switch, the gate of the tenth transistor is connected to the second single-pole double-throw switch, the gate of the eleventh transistor is connected to the third single-pole double-throw switch, and the gate of the twelfth transistor is connected to the fourth single-pole double-throw switch; the control signal for the first single-pole double-throw switch is SI, the control signal for the second single-pole double-throw switch is SI', the control signal for the third single-pole double-throw switch is SQ, and the control signal for the fourth single-pole double-throw switch is SQ'; all four switches are connected to the first bias voltage terminal when the control signal is 0 and grounded when the control signal is 0; the sources of the ninth and tenth transistors are both connected to the drain of the seventh transistor, and the gate of the seventh transistor is connected to the bias voltage source and grounded; the sources of the eleventh and twelfth transistors are both connected to the drain of the eighth transistor, and the gate of the eighth transistor is connected to the bias current source and grounded.

[0025] Further, the output balun includes a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, and a reference current source; the first RF input positive terminal is connected to the gate of the twenty-third transistor via the nineteenth capacitor, the gate of the twenty-third transistor is also grounded via the seventeenth resistor, the drain of the twenty-third transistor is connected to the source of the twenty-fifth transistor, and the gate of the twenty-third transistor is connected to the drain of the twenty-fifth transistor via the nineteenth resistor and the twenty-first capacitor; the drain of the twenty-fifth transistor is also connected to the power supply terminal via the twenty-first resistor and an RF output terminal is led out from the drain of the twenty-fifth transistor; the first RF input negative terminal is connected to the gate of the twenty-fourth transistor via the twenty-tenth capacitor and is also grounded via the eighteenth resistor, the twenty-first... The drain of the four transistors is connected to the source of the twenty-sixth transistor, and the gate of the twenty-fourth transistor is connected to the drain of the twenty-sixth transistor via the twentieth resistor and the twenty-second capacitor. The drain of the twenty-sixth transistor is also connected to the power supply terminal via the twenty-second resistor. The nineteenth resistor and the twenty-first capacitor form a feedback network on one side, and the twentieth resistor and the twenty-second capacitor form a feedback network on the other side. After the gates of the twenty-fifth transistor and the twenty-sixth transistor are connected, they are connected to the first bias voltage terminal and grounded via the twenty-third capacitor. The twenty-first transistor and the twenty-second transistor form a current mirror structure, with their gates shorted to each other. The drain of the twenty-first transistor is connected to the reference current source and shorted to its gate. The source of the twenty-first transistor is grounded. The drain of the twenty-second transistor is connected to the sources of both the twenty-third transistor and the twenty-fourth transistor, providing bias current to the twenty-third and twenty-fourth transistors. All grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal provides the operating power supply voltage for each device.

[0026] Furthermore, the twenty-third transistor is the same size as the twenty-fourth transistor, and the twenty-fifth transistor is the same size as the twenty-sixth transistor.

[0027] Furthermore, it is implemented using SMIC 55nm process, with an operating frequency band of 5-17GHz, a phase shift step of 5.625°, a 3dB bandwidth covering 5-16GHz, and an average peak gain of 0.5dB; within the 5-17GHz operating frequency band, the root mean square error of amplitude is less than 0.74dB, and the root mean square error of phase is less than 4°.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. Broadband and Gain Flattening: By introducing an inductive compensation network, this invention effectively compensates for high-frequency gain loss, significantly extending the operating bandwidth of the phase shifter (e.g., 3dB bandwidth) to 5-16GHz, and achieving an average flat gain of approximately 0.5dB across the entire 5-17GHz frequency band.

[0030] 2. High phase shift accuracy: While expanding the bandwidth, the introduction of the inductive compensation network does not degrade the phase shift accuracy. The phase shifter can achieve 360° phase shift in 5.625° steps within the 5-17GHz range, with a root mean square phase error of less than 4°.

[0031] 3. Low amplitude error: This architecture effectively suppresses gain fluctuations under different phase states, with an amplitude root mean square error of less than 0.74dB across the entire operating frequency band and full phase range, improving the consistency between phased array channels.

[0032] 4. High integration and digital friendliness: All circuits in this invention are implemented based on standard CMOS technology, which makes them easy to integrate with digital control circuits (such as DACs) on a single chip, making them very suitable for large-scale, low-cost phased array system applications. Attached Figure Description

[0033] Figure 1 This is a circuit structure diagram of a broadband active phase shifter based on inductive compensation provided in an embodiment of the present invention.

[0034] Figure 2 This is a circuit diagram of the input balun in an embodiment of the present invention.

[0035] Figure 3 This is a circuit structure diagram of a three-level Type-II PPF in an embodiment of the present invention.

[0036] Figure 4 This is a circuit structure diagram of the inductive compensation network in an embodiment of the present invention.

[0037] Figure 5 This is a circuit diagram of the adder in an embodiment of the present invention.

[0038] Figure 6 This is a comparison diagram of the S21 results with and without the inductive compensation circuit in the embodiments of the present invention.

[0039] Figure 7 This is the circuit diagram for an active output balun.

[0040] Figure 8 This is a phase shifting result diagram in an embodiment of the present invention.

[0041] Figure 9 This is a gain result diagram in an embodiment of the present invention.

[0042] Figure 10This is a comparison chart of the root mean square error of amplitude with and without inductive compensation circuit in the embodiments of the present invention.

[0043] Figure 11 This is a comparison chart of the root mean square error results with and without inductive compensation circuit in the embodiments of the present invention. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0045] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0046] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] like Figure 1 As shown, this embodiment provides a broadband active phase shifter based on inductive compensation, including an input balun, a quadrature signal generator, an inductive compensation network, an adder, and an output balun connected in series, as well as a 7-bit digital-to-analog converter (DAC) connected to the adder. Both the input and output baluns employ a two-stage differential active balun structure. The input balun converts the single-ended input signal into a differential signal, and the output balun converts the differential output signal into a single-ended signal. The quadrature signal generator is a three-stage Type-II polyphase filter (PPF) used to convert the differential signal into a quadrature signal. The inductive compensation network generates peak gain at high frequencies, widening the operating bandwidth without affecting phase shift accuracy. The adder uses a Gilbert cell and controls phase changes via digital signal input. As a Gilbert cell-based vector modulation module, it performs polarity selection and vector synthesis of the quadrature signal. The 7-bit DAC provides different bias voltages to the Gilbert cell to control the current magnitude and achieve vector modulation.

[0048] This circuit architecture enables a 360° phase shift range covered in 5.625° steps, achieving gain flattening, high phase shift accuracy, and low RMSA. This architecture not only enhances the matching between phase shifter poles but also significantly improves phase shift accuracy. Typically, active phase shifters exhibit large gain fluctuations, requiring subsequent driver amplifiers in the receiver / transmitter chain to compensate for the gain, greatly increasing design complexity. Therefore, by adding an inductive gain compensation network between the three-stage PPF and the adder, gain flattening can be achieved without affecting phase shift accuracy, and the operating bandwidth can be extended, thereby comprehensively improving overall performance.

[0049] like Figure 2 As shown, the input balun includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a reference current source Iref. The RF input terminal RFIN is connected to the gate of the third transistor M3 via the first capacitor C1. The gate of the third transistor M3 is also grounded via the first resistor R1. The drain of the third transistor M3 is connected to the source of the fifth transistor M5, and the gate of the third transistor M3 is connected to the drain of the fifth transistor M5 via the second resistor R2 and the third capacitor C3. The drain of the fifth transistor M5 is also connected to the power supply terminal VDD via the third resistor R3, and the first RF output terminal RFOUT+ is led out from the drain of the fifth transistor M5. In the symmetrical branch, the gate of the fourth transistor M4 is grounded via the second capacitor C2, and the drain of the fourth transistor M4 is connected to the source of the sixth transistor M6. The drain of the sixth transistor M6 is connected to the fourth resistor R4. Resistor R4 is connected to the power supply terminal VDD and leads to the second RF output terminal RFOUT- from the drain of the sixth transistor M6. The gates of the fifth transistor M5 and the sixth transistor M6 are connected, then connected to the first bias voltage terminal VB1 and grounded via the fourth capacitor C4. The first transistor M1 and the second transistor M2 form a current mirror structure, with their gates shorted together. The drain of the first transistor M1 is connected to the reference current source Iref and shorted to its gate. The source of the first transistor M1 is grounded, and the source of the second transistor M2 is grounded. The drain of the second transistor M2 is simultaneously connected to the sources of the third transistor M3 and the fourth transistor M4, providing bias current for both transistors. All grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal VDD provides the operating power supply voltage for each device. Furthermore, considering symmetry, the third transistor M3 and the fourth transistor M4 are the same size, and the fifth transistor M5 and the sixth transistor M6 are the same size. Adjusting the dimensions of M3-M6 can achieve a 180° phase change within the wide bandwidth, and adjusting the values ​​of the second resistor R2 and the third capacitor C3 can achieve a flat gain within the operating bandwidth.

[0050] like Figure 3 As shown, the three-stage Type-II PPF consists of a first-stage PPF, a second-stage PPF, and a third-stage PPF cascaded sequentially. The first-stage PPF is composed of resistors R5, R6, R7, and R8 connected in series with capacitors C5, C6, C7, and C8. The first RF input positive terminal RFIN+ is simultaneously connected to one end of resistor R5, one end of capacitor C5, one end of resistor R6, and one end of capacitor C6. The first RF input negative terminal RFIN- is simultaneously connected to one end of resistor R7, one end of capacitor C7, one end of resistor R8, and one end of capacitor C8. The other end of capacitor C5 is connected to the other end of resistor R6, the other end of capacitor C6 is connected to the other end of resistor R7, the other end of capacitor C7 is connected to the other end of resistor R8, and the other end of capacitor C8 is connected to the other end of resistor R5.

[0051] The second-stage PPF consists of resistors R9, R10, R11, and R12 connected in series with capacitors C9, C10, C11, and C12. The connection point between capacitor C8 and resistor R5 is simultaneously connected to one end of resistor R9 and capacitor C9. Similarly, the connection point between capacitor C5 and resistor R6 is simultaneously connected to one end of resistor R10 and capacitor C10. The connection point between capacitor C6 and resistor R7 is simultaneously connected to one end of resistor R11 and capacitor C11. The connection point between capacitor C7 and resistor R8 is simultaneously connected to one end of resistor R12 and capacitor C12. The other end of capacitor C9 is connected to the other end of resistor R10. The other end of capacitor C10 is connected to the other end of resistor R11. The other end of capacitor C11 is connected to the other end of resistor R12. Finally, the other end of capacitor C12 is connected to the other end of resistor R9.

[0052] The third-stage PPF consists of resistors R13 (13th), R14 (14th), R15 (15th), and R16 (16th) connected in series with capacitors C13 (13th), C14 (14th), C15 (15th), and C16 (16th). The connection point between capacitor C12 (12th) and resistor R9 (9th) is simultaneously connected to one end of resistor R13 and one end of capacitor C13. Similarly, the connection point between capacitor C9 (9th) and resistor R10 (10th) is simultaneously connected to one end of resistor R14 and one end of capacitor C14. Finally, the connection point between capacitor C10 (10th) and resistor R11 (11th) is simultaneously connected to the fifteenth resistor R13 and one end of capacitor C16. One end of resistor R15 and one end of the fifteenth capacitor C15, the connection point of the eleventh capacitor C11 and the twelfth resistor R12 are simultaneously connected to one end of the sixteenth resistor R16 and one end of the sixteenth capacitor C16. The other end of the sixteenth capacitor C16 is connected to the other end of the thirteenth resistor R13 and leads out the first output terminal I+. The other end of the thirteenth capacitor C13 is connected to the other end of the fourteenth resistor R14 and leads out the second output terminal Q+. The other end of the fourteenth capacitor C14 is connected to the other end of the fifteenth resistor R15 and leads out the third output terminal I-. The other end of the fifteenth capacitor C15 is connected to the other end of the sixteenth resistor R16 and leads out the fourth output terminal Q-.

[0053] In this configuration, the resistance values ​​of resistors R5 through R8 are equal, the capacitance values ​​of capacitors C5 through C8 are equal, the resistance values ​​of resistors R9 through R12 are equal, the capacitance values ​​of capacitors C9 through C12 are equal, the resistance values ​​of resistors R13 through R16 are equal, and the capacitance values ​​of capacitors C13 through C16 are equal. By adjusting the capacitor and resistance values, a 90° phase difference between the I-channel differential output and the Q-channel differential output can be achieved. This relationship can be expressed by the following formula:

[0054] (1)

[0055] Equation (2)

[0056] (3)

[0057] (4)

[0058] (5)

[0059] In ω n At this point, the phase difference between the I-channel differential output and the Q-channel differential output is 90°, R n C n These are the resistance and capacitance values ​​of the nth stage PPF, respectively.

[0060] like Figure 4As shown, the inductive compensation network includes a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. The first inductor L1 is connected in series between the first output terminal I+ of the three-stage Type-II PPF and the corresponding signal input terminal of the adder, with the two ends of the inductor being I+ (three-stage PPF side) and I1+ (adder side); the second inductor L2 is connected in series between the second output terminal Q+ of the three-stage Type-II PPF and the corresponding signal input terminal of the adder, with the two ends of the inductor being Q+ (three-stage PPF side) and Q1+ (adder side); the third inductor L3 is connected in series between the third output terminal I- of the three-stage Type-II PPF and the corresponding signal input terminal of the adder, with the two ends of the inductor being I- (three-stage PPF side) and I1- (adder side); the fourth inductor L4 is connected in series between the fourth output terminal Q- of the three-stage Type-II PPF and the corresponding signal input terminal of the adder, with the two ends of the inductor being Q- (three-stage PPF side) and Q1- (adder side); each inductor is used to achieve signal transmission matching between the three-stage Type-II PPF and the adder.

[0061] like Figure 5 As shown, the adder consists of a fifth inductor L5, a sixth inductor L6, a seventeenth capacitor C17, an eighteenth capacitor C18, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a first single-pole double-throw switch SI, a second single-pole double-throw switch SI', a third single-pole double-throw switch SQ, a fourth single-pole double-throw switch SQ', a bias voltage source IBIAS, and a bias current source QBIAS.

[0062] Transistors M13 through M20 are of equal size. One end of the fifth inductor L5 is connected to the power supply terminal VDD and then to the first RF output terminal RFOUT1+ via the seventeenth capacitor C17. The other end of the fifth inductor L5 is simultaneously connected to the drains of transistors M13, M15, M17, and M19. One end of the sixth inductor L6 is connected to the power supply terminal VDD and then to the second RF output terminal RFOUT1- via the eighteenth capacitor C18. The other end of the sixth inductor L6 is simultaneously connected to the drains of transistors M14, M16, M18, and M20. The first signal input terminal I1+ is also connected to the thirteenth transistor. The gates of transistors M13 and M14 are connected; the second signal input terminal I1- is simultaneously connected to the gates of transistors M15 and M16; the third signal input terminal Q1+ is simultaneously connected to the gates of transistors M17 and M18; the fourth signal input terminal Q1- is simultaneously connected to the gates of transistors M19 and M20; the source of transistor M13 is connected to the source of transistor M16 and to the drain of transistor M9; the source of transistor M14 is connected to the source of transistor M15 and to the tenth transistor M1... The drain of transistor M10 is connected to the source of transistor M11; the source of transistor M17 is connected to the source of transistor M20, and to the drain of transistor M11; the source of transistor M18 is connected to the source of transistor M19, and to the drain of transistor M12; the gate of transistor M9 is connected to the first single-pole double-throw switch SI; the gate of transistor M10 is connected to the second single-pole double-throw switch SI'; the gate of transistor M11 is connected to the third single-pole double-throw switch SQ; the gate of transistor M12 is connected to the fourth single-pole double-throw switch SQ'; the control signal for the first single-pole double-throw switch SI is SI; the control signal for the second single-pole double-throw switch SQ' is SI. The control signal for I' is SI', the control signal for the third single-pole double-throw switch SQ is SQ, and the control signal for the fourth single-pole double-throw switch SQ' is SQ'. All four sets of switches connect the first bias voltage terminal VBI when the control signal is 1, and are grounded when the control signal is 0. The source of the ninth transistor M9 and the source of the tenth transistor M10 are both connected to the drain of the seventh transistor M7. The gate of the seventh transistor M7 is connected to the bias voltage source IBIAS, and its source is grounded. The source of the eleventh transistor M11 and the source of the twelfth transistor M12 are both connected to the drain of the eighth transistor M8. The gate of the eighth transistor M8 is connected to the bias current source QBIAS, and its source is grounded.

[0063] Furthermore, the transfer function of the inductor in the inductive compensation network cascaded with the amplifier transistor in the subsequent adder can be expressed as follows:

[0064]

[0065] CM13 and gm13 are the equivalent capacitance and conductance of M13, respectively. Since M13-M20 have the same dimensions, their equivalent capacitance and conductance are also the same, so only one equivalent calculation is performed here. It can be seen that L1 and the equivalent capacitance CM13 of M13 form a series resonant network. By adjusting the values ​​of L1 and M13, the phase shifter can achieve peak gain at high frequencies. By adjusting the aspect ratio of the first capacitor C1, the first resistor R1, and M3 in the input balun, peak gain can be achieved at low frequencies, thereby flattening the gain of the phase shifter over a wide operating frequency band and greatly expanding the operating bandwidth of the active phase shifter.

[0066] Figure 6 This is a comparison diagram of the S21 results with and without the inductive compensation circuit in this embodiment. It can be seen that by adding the inductive compensation network, the operating bandwidth can be greatly expanded.

[0067] like Figure 7As shown, the output balun includes a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, and a reference current source Iref. The first RF input positive terminal RFIN+ is connected to the gate of the twenty-third transistor M23 via the nineteenth capacitor C19. The gate of the twenty-third transistor M23 is also grounded via the seventeenth resistor R17. The drain of the twenty-third transistor M23 is connected to the source of the twenty-fifth transistor M25, and the gate of the twenty-third transistor M23 is connected to the drain of the twenty-fifth transistor M25 via the nineteenth resistor R19 and the twenty-first capacitor C21. The drain of the twenty-fifth transistor M25 is also connected to the power supply terminal VDD via the twenty-first resistor R21, and the RF output terminal RFOUT is led out from the drain of the twenty-fifth transistor M25. The first RF input negative terminal RFIN- is connected to the gate of the twenty-fourth transistor M24 via the twentieth capacitor C20 and is also grounded via the eighteenth resistor R18. The drain of the twenty-fourth transistor M24 is connected to the source of the twenty-sixth transistor M26, and the gate of the twenty-fourth transistor M24 is connected to the twentieth resistor R20 and the twenty-second capacitor C22. The drain of transistor M26 (the 26th transistor) is connected; the drain of transistor M26 is also connected to the power supply terminal VDD via resistor R22 (the 22nd resistor); resistor R19 (the 19th resistor) and capacitor C21 (the 21st capacitor) form a feedback network on one side, and resistor R20 (the 20th resistor) and capacitor C22 (the 22nd capacitor) form a feedback network on the other side; transistor M25 (the 25th transistor) is connected to the gate of transistor M26 (the 26th transistor), then connected to the first bias voltage terminal VB1 and grounded via capacitor C23 (the 23rd capacitor); transistors M21 (the 21st transistor) and M22 (the 22nd transistor) form a current mirror structure, with their gates shorted to each other. The drain of transistor M21 (the 21st transistor) is connected to the reference current source Iref and shorted to its gate. The source of transistor M21 (the 21st transistor) is grounded. The drain of transistor M22 (the 22nd transistor) is connected to the source of transistors M23 (the 23rd transistor) and M24 (the 24th transistor), providing bias current for transistors M23 (the 23rd transistor) and M24 (the 24th transistor). All grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal VDD provides the operating power supply voltage for each device. The twenty-third transistor M23 and the twenty-fourth transistor M24 have the same size, and the twenty-fifth transistor M25 and the twenty-sixth transistor M26 have the same size. Output matching can be achieved by adjusting the resistance value of the twenty-first resistor R21 and the width-to-length ratio of the twenty-fifth transistor M25.

[0068] The broadband active phase shifter based on inductive compensation provided in this embodiment is implemented using SMIC 55nm process, operates in the 5-17GHz frequency band, has a phase shift step of 5.625°, a 3dB bandwidth covering 5-16GHz, and an average peak gain of 0.5dB. Within the 5-17GHz operating frequency band, the root mean square error of amplitude is less than 0.74dB, and the root mean square error of phase is less than 4°.

[0069] Figure 8 This is a phase shift result diagram in this embodiment. Within the wide operating frequency range of 5-17GHz, the phase shifter can achieve phase adjustment in a range of 360° and a step of 5.625°, with 64 phase states that are essentially non-overlapping, thus achieving a wideband phase shift effect.

[0070] Figure 9 This is the gain result diagram in this embodiment. Within the wide operating frequency range, the average peak gain is 0.5dB, and the 3dB bandwidth covers 5-16GHz, achieving gain flattening.

[0071] Figure 10 This is a comparison chart showing the root mean square error (RMSE) of amplitude with and without the inductive compensation circuit in this embodiment. Within the wide operating frequency range of 5-17 GHz, the RMSE of amplitude with the inductive compensation network is less than 0.74 dB, indicating that this phase shifter achieves a small amplitude error, and that the addition of the inductive compensation network reduces the RMSE to some extent.

[0072] Figure 11 This is a comparison chart of the phase root mean square error results in this embodiment. Within the wide operating frequency range of 5-17GHz, the phase root mean square error of adding the inductive compensation network is less than 4°, indicating that this phase shifter achieves high-precision phase shifting performance, and the addition of the inductive compensation network does not significantly worsen the phase root mean square error.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A broadband active phase shifter based on inductive compensation, characterized in that, It includes an input balun, a quadrature signal generator, an inductive compensation network, an adder, and an output balun connected in series, as well as a 7-bit DAC connected to the adder, which can achieve a 360° phase shift range; Both the input balun and the output balun adopt a two-stage differential active balun structure. The input balun is used to convert the single-ended signal at the input end into a differential signal, and the output balun is used to convert the differential signal at the output end into a single-ended signal. The orthogonal signal generator is a three-stage Type-II PPF used to convert differential signals into orthogonal signals; The inductive compensation network is used to generate peak gain at high frequencies, widening the operating bandwidth without affecting phase shift accuracy. The adder uses a Gilbert cell and controls the phase change through digital signal input. As a vector modulation module based on the Gilbert cell, it performs polarity selection on orthogonal signals and realizes vector synthesis. The 7-bit DAC is used to provide different bias voltages to the Gilbert unit in order to control the current magnitude and achieve vector modulation.

2. The inductance-based wideband active phase shifter of claim 1, wherein, The input balun includes a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), a sixth transistor (M6), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), and a reference current source (Iref); the radio frequency input terminal (RFIN) is connected to the third transistor (M3) via the first capacitor (C1). The gate of the third transistor (M3) is grounded via the first resistor (R1). The drain of the third transistor (M3) is connected to the source of the fifth transistor (M5), and the gate of the third transistor (M3) is connected to the drain of the fifth transistor (M5) via the second resistor (R2) and the third capacitor (C3). The drain of the fifth transistor (M5) is also connected to the power supply terminal (VDD) via the third resistor (R3), and the first RF output terminal (RFOUT+) is led out from the drain of the fifth transistor (M5). In the symmetrical branch, the fourth transistor (M4) The gate of transistor M1 is grounded via capacitor C2. The drain of transistor M4 is connected to the source of transistor M6. The drain of transistor M6 is connected to the power supply terminal (VDD) via resistor R4, and a second RF output terminal (RFOUT-) is led out from the drain of transistor M6. After the gates of transistors M5 and M6 are connected, transistor M5 is connected to the first bias voltage terminal (VB1) and grounded via capacitor C4. Transistors M1 and M2 form a circuit. The circuit features a flow mirror structure with the gates of the two transistors shorted together. The drain of the first transistor (M1) is connected to the reference current source (Iref) and shorted to its gate. The source of the first transistor (M1) is grounded, and the source of the second transistor (M2) is grounded. The drain of the second transistor (M2) is simultaneously connected to the source of the third transistor (M3) and the source of the fourth transistor (M4), providing bias current for the third transistor (M3) and the fourth transistor (M4). All grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal (VDD) provides the operating power supply voltage for each device.

3. The broadband active phase shifter based on inductive compensation according to claim 2, characterized in that, The third transistor (M3) and the fourth transistor (M4) are the same size, and the fifth transistor (M5) and the sixth transistor (M6) are the same size.

4. The broadband active phase shifter based on inductive compensation according to claim 1, characterized in that, The three-stage Type-II PPF consists of a first-stage PPF, a second-stage PPF, and a third-stage PPF cascaded sequentially. The first-stage PPF is composed of resistors R5, R6, R7, and R8 connected in series with capacitors C5, C6, C7, and C8. The first RF input positive terminal (RFIN+) is simultaneously connected to one end of resistor R5, one end of capacitor C5, one end of resistor R6, and the third stage PPF. One end of the sixth capacitor (C6) is connected to the first RF input negative terminal (RFIN-) and simultaneously to one end of the seventh resistor (R7), one end of the seventh capacitor (C7), one end of the eighth resistor (R8), and one end of the eighth capacitor (C8). The other end of the fifth capacitor (C5) is connected to the other end of the sixth resistor (R6), the other end of the sixth capacitor (C6) is connected to the other end of the seventh resistor (R7), the other end of the seventh capacitor (C7) is connected to the other end of the eighth resistor (R8), and the other end of the eighth capacitor (C8) is connected to the other end of the fifth resistor (R5). The second-stage PPF consists of resistors 9 (R9), 10 (R10), 11 (R11), and 12 (R12) connected in series with capacitors 9 (C9), 10 (C10), 11 (C11), and 12 (C12). The connection point between capacitor 8 (C8) and resistor 5 (R5) is simultaneously connected to one end of resistor 9 (R9) and one end of capacitor 9 (C9). The connection point between capacitor 5 (C5) and resistor 6 (R6) is simultaneously connected to one end of resistor 10 (R10) and one end of capacitor 10 (C10). Capacitor 6 (C6) is connected to... The connection point of resistor 7 (R7) is simultaneously connected to one end of resistor 11 (R11) and one end of capacitor 11 (C11). The connection point of capacitor 7 (C7) and resistor 8 (R8) is simultaneously connected to one end of resistor 12 (R12) and one end of capacitor 12 (C12). The other end of capacitor 9 (C9) is connected to the other end of resistor 10 (R10). The other end of capacitor 10 (C10) is connected to the other end of resistor 11 (R11). The other end of capacitor 11 (C11) is connected to the other end of resistor 12 (R12). The other end of capacitor 12 (C12) is connected to the other end of resistor 9 (R9). The third-stage PPF consists of the thirteenth resistor (R13), fourteenth resistor (R14), fifteenth resistor (R15), and sixteenth resistor (R16) connected in series with the thirteenth capacitor (C13), fourteenth capacitor (C14), fifteenth capacitor (C15), and sixteenth capacitor (C16). The connection point between the twelfth capacitor (C12) and the ninth resistor (R9) is simultaneously connected to one end of the thirteenth resistor (R13) and one end of the thirteenth capacitor (C13). The connection point between the ninth capacitor (C9) and the tenth resistor (R10) is simultaneously connected to one end of the fourteenth resistor (R14) and one end of the fourteenth capacitor (C14). The connection point between the tenth capacitor (C10) and the eleventh resistor (R11) is simultaneously connected to the fifteenth capacitor (C16). One end of resistor (R15) and one end of the fifteenth capacitor (C15), the connection point of the eleventh capacitor (C11) and the twelfth resistor (R12) are simultaneously connected to one end of the sixteenth resistor (R16) and one end of the sixteenth capacitor (C16). The other end of the sixteenth capacitor (C16) is connected to the other end of the thirteenth resistor (R13) and leads out the first output terminal (I+). The other end of the thirteenth capacitor (C13) is connected to the other end of the fourteenth resistor (R14) and leads out the second output terminal (Q+). The other end of the fourteenth capacitor (C14) is connected to the other end of the fifteenth resistor (R15) and leads out the third output terminal (I-). The other end of the fifteenth capacitor (C15) is connected to the other end of the sixteenth resistor (R16) and leads out the fourth output terminal (Q-).

5. The broadband active phase shifter based on inductive compensation according to claim 4, characterized in that, The resistance values ​​of the fifth resistor (R5) to the eighth resistor (R8) are equal, the capacitance values ​​of the fifth capacitor (C5) to the eighth capacitor (C8) are equal, the resistance values ​​of the ninth resistor (R9) to the twelfth resistor (R12) are equal, the capacitance values ​​of the ninth capacitor (C9) to the twelfth capacitor (C12) are equal, the resistance values ​​of the thirteenth resistor (R13) to the sixteenth resistor (R16) are equal, and the capacitance values ​​of the thirteenth capacitor (C13) to the sixteenth capacitor (C16) are equal.

6. The broadband active phase shifter based on inductive compensation according to claim 1, characterized in that, The inductive compensation network includes a first inductor (L1), a second inductor (L2), a third inductor (L3), and a fourth inductor (L4). The first inductor (L1) is connected in series between the first output terminal (I+) of the three-stage Type-II PPF and the corresponding signal input terminal of the adder. The second inductor (L2) is connected in series between the second output terminal (Q+) of the three-stage Type-II PPF and the corresponding signal input terminal of the adder. The third inductor (L3) is connected in series between the third output terminal (I-) of the three-stage Type-II PPF and the corresponding signal input terminal of the adder. The fourth inductor (L4) is connected in series between the fourth output terminal (Q-) of the three-stage Type-II PPF and the corresponding signal input terminal of the adder. Each inductor is used to achieve signal transmission matching between the three-stage Type-II PPF and the adder.

7. The broadband active phase shifter based on inductive compensation according to claim 1, characterized in that, The adder consists of a fifth inductor (L5), a sixth inductor (L6), a seventeenth capacitor (C17), an eighteenth capacitor (C18), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11), a twelfth transistor (M12), a thirteenth transistor (M13), a fourteenth transistor (M14), a fifteenth transistor (M15), a sixteenth transistor (M16), a seventeenth transistor (M17), an eighteenth transistor (M18), a nineteenth transistor (M19), a twentieth transistor (M20), a first single-pole double-throw switch (SI), a second single-pole double-throw switch (SI'), a third single-pole double-throw switch (SQ), a fourth single-pole double-throw switch (SQ'), a bias voltage source (IBIAS), and a bias current source (QBIAS). The thirteenth transistor (M13) through the twentieth transistor (M20) have the same dimensions; One end of the fifth inductor (L5) is connected to the power supply terminal (VDD) and then to the first RF output terminal (RFOUT1+) via the seventeenth capacitor (C17). The other end of the fifth inductor (L5) is simultaneously connected to the drains of the thirteenth transistor (M13), the fifteenth transistor (M15), the seventeenth transistor (M17), and the nineteenth transistor (M19). One end of the sixth inductor (L6) is connected to the power supply terminal (VDD) and then to the second RF output terminal (RFOUT1-) via the eighteenth capacitor (C18). The other end of the sixth inductor (L6) is simultaneously connected to the fourteenth transistor (M14), the sixteenth transistor (M16), the eighteenth transistor (M18), and the twentieth transistor (M20). The drains of transistors are connected; the first signal input terminal (I1+) is simultaneously connected to the gates of the thirteenth transistor (M13) and the fourteenth transistor (M14); the second signal input terminal (I1-) is simultaneously connected to the gates of the fifteenth transistor (M15) and the sixteenth transistor (M16); the third signal input terminal (Q1+) is simultaneously connected to the gates of the seventeenth transistor (M17) and the eighteenth transistor (M18); the fourth signal input terminal (Q1-) is simultaneously connected to the gates of the nineteenth transistor (M19) and the twentieth transistor (M20); the source of the thirteenth transistor (M13) is connected to the source of the sixteenth transistor (M16), and is connected to the ninth transistor (M14). The drain of transistor M9 is connected to the drain of transistor M11; the source of transistor M14 is connected to the source of transistor M15, and then to the drain of transistor M10; the source of transistor M17 is connected to the source of transistor M20, and then to the drain of transistor M11; the source of transistor M18 is connected to the source of transistor M19, and then to the drain of transistor M12; the gate of transistor M9 is connected to the first single-pole double-throw switch (SI), the gate of transistor M10 is connected to the second single-pole double-throw switch (SI'), and the gate of transistor M11 is connected to the third single-pole double-throw switch (SI'). A single-pole double-throw switch (SQ) is used, and the gate of the twelfth transistor (M12) is connected to the fourth single-pole double-throw switch (SQ'). All four switches are connected to the first bias voltage terminal (VBI) when the control signal is 1, and grounded when the control signal is 0. The source of the ninth transistor (M9) and the source of the tenth transistor (M10) are both connected to the drain of the seventh transistor (M7). The gate of the seventh transistor (M7) is connected to the bias voltage source (IBIAS), and its source is grounded. The source of the eleventh transistor (M11) and the source of the twelfth transistor (M12) are both connected to the drain of the eighth transistor (M8). The gate of the eighth transistor (M8) is connected to the bias current source (QBIAS), and its source is grounded.

8. The broadband active phase shifter based on inductive compensation according to claim 1, characterized in that, The output balun includes a seventeenth resistor (R17), an eighteenth resistor (R18), a nineteenth resistor (R19), a twentieth resistor (R20), a twenty-first resistor (R21), a twenty-second resistor (R22), a nineteenth capacitor (C19), a twentieth capacitor (C20), a twenty-first capacitor (C21), a twenty-second capacitor (C22), a twenty-third capacitor (C23), a twenty-first transistor (M21), a twenty-second transistor (M22), a twenty-third transistor (M23), a twenty-fourth transistor (M24), a twenty-fifth transistor (M25), a twenty-sixth transistor (M26), and a reference current source (Iref); the first RF input positive terminal (RFIN+) is connected to the nineteenth capacitor (C19). 19) The gate of the 23rd transistor (M23) is connected, and the gate of the 23rd transistor (M23) is also grounded through the 17th resistor (R17). The drain of the 23rd transistor (M23) is connected to the source of the 25th transistor (M25), and the gate of the 23rd transistor (M23) is connected to the drain of the 25th transistor (M25) through the 19th resistor (R19) and the 21st capacitor (C21). The drain of the 25th transistor (M25) is also connected to the power supply terminal (VDD) through the 21st resistor (R21), and the RF output terminal (RFOUT) is led out from the drain of the 25th transistor (M25). The first RF input negative terminal (RFIN-) is connected to the 24th transistor through the 20th capacitor (C20). The gate of transistor M24 is grounded via the eighteenth resistor (R18). The drain of transistor M24 is connected to the source of transistor M26, and the gate of transistor M24 is connected to the drain of transistor M26 via the twentieth resistor (R20) and the twenty-second capacitor (C22). The drain of transistor M26 is also connected to the power supply terminal (VDD) via the twenty-second resistor (R22). The nineteenth resistor (R19) and the twenty-first capacitor (C21) form a feedback network on one side, and the twentieth resistor (R20) and the twenty-second capacitor (C22) form a feedback network on the other side. After the gates of transistors M25 and M26 are connected, The circuit is connected to the first bias voltage terminal (VB1) and grounded through the twenty-third capacitor (C23); the twenty-first transistor (M21) and the twenty-second transistor (M22) form a current mirror structure, with their gates shorted to each other. The drain of the twenty-first transistor (M21) is connected to the reference current source (Iref) and shorted to its gate. The source of the twenty-first transistor (M21) is grounded. The drain of the twenty-second transistor (M22) is connected to the source of both the twenty-third transistor (M23) and the twenty-fourth transistor (M24), providing bias current for the twenty-third transistor (M23) and the twenty-fourth transistor (M24); all grounding nodes in the circuit are connected to a common ground potential, and the power supply terminal (VDD) provides the operating power supply voltage for each device.

9. The broadband active phase shifter based on inductive compensation according to claim 8, characterized in that, The 23rd transistor (M23) and the 24th transistor (M24) are the same size, and the 25th transistor (M25) and the 26th transistor (M26) are the same size.

10. The broadband active phase shifter based on inductive compensation according to claim 1, characterized in that, It is implemented using SMIC 55nm process, operates in the frequency band of 5-17GHz, has a phase shift step of 5.625°, a 3dB bandwidth covering 5-16GHz, and an average peak gain of 0.5dB. Within the 5-17GHz operating frequency band, the root mean square error of amplitude is less than 0.74dB, and the root mean square error of phase is less than 4°.

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