A package substrate with buried interconnection bridge, semiconductor package structure and manufacturing method thereof

Abstract

This invention discloses a packaging substrate for buried interconnect bridges, a semiconductor packaging structure, and a method for fabricating the same. The packaging substrate includes a core board, which is a substrate or PCB board without a solder mask layer. The core board has opposing first and second surfaces. An outermost circuit layer is formed on the first surface and electrically connected to the circuit layer within the core board. The outermost circuit layer has a metal disk. Interconnect bridges are bonded or attached to the metal disk of the outermost circuit layer. A molding layer is formed on the first surface, the outermost circuit layer, and the interconnect bridges, and covers the interconnect bridges. Multiple conductive interconnect structures penetrate the molding layer and are electrically connected to the metal disk and interconnect bridges of the outermost circuit layer, respectively, to provide electrical paths to external chips. Multiple external connection terminals are electrically connected one-to-one to the side of the multiple conductive interconnect structures away from the core board. This packaging substrate for buried interconnect bridges can be used for board-level or system-level multi-chip packaging, achieving high-density interconnection between chips and compatibility with the domestic industrial chain.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging technology, and in particular to a packaging substrate with buried interconnect bridges, a semiconductor packaging structure, and a method for manufacturing the same. Background Technology

[0002] With the rapid development of fields such as artificial intelligence (AI) and high-performance computing (HPC), the demand for chip integration, interconnect density, and transmission performance is increasing. 2.5D / 3D advanced packaging technology has become a core direction for breaking through performance bottlenecks. Existing mainstream solutions, such as TSMC's COWOS series and Intel's EMIB series, while achieving high-density interconnects, suffer from problems such as foreign monopoly on core process equipment, high costs, and incompatibility with mature domestic PCB processes, resulting in limited domestic production capacity and insufficient output.

[0003] Therefore, there is an urgent need to develop a packaging technology that is compatible with domestic processes, low-cost, and achieves high-density interconnection, in order to break through the technological blockade and meet the needs of domestic industrialization. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the objective of this invention is to provide a packaging substrate for buried interconnect bridges, a semiconductor packaging structure, and a method for fabricating the same. This packaging substrate for buried interconnect bridges can be used for board-level or system-level multi-chip packaging, achieving high-density interconnection between chips and compatibility with the domestic industrial chain.

[0005] To achieve the above objectives, the present invention provides, in a first aspect, a package substrate for buried interconnect bridges, comprising: The core board is a substrate or PCB board without a solder resist layer, and the core board has a first surface and a second surface opposite to each other. The outermost circuit layer is formed on the first surface and electrically connected to the circuit layer within the core board, the outermost circuit layer having a metal disk; Interconnect bridges are attached or bonded to the metal disk of the outermost circuit layer; A molding layer is formed on the first surface, the outermost circuit layer, and the interconnect bridge, and covers the interconnect bridge; Multiple conductive interconnect structures extend through the molding layer and are electrically connected to the metal disk of the outermost circuit layer and the interconnect bridge, respectively, to provide an electrical path to an external chip; Multiple external connection terminals are electrically connected one-to-one to the side of the multiple conductive interconnect structures away from the core board.

[0006] According to a packaging substrate for embedded interconnect bridges of the present invention, the packaging substrate uses a substrate without a solder mask layer, PCB board, etc., as a core board to provide mechanical support and initial electrical wiring layers. Based on this, laser drilling and electroplating processes can be used to form the outermost circuit and metal pads, providing connection points for the embedding of interconnect bridges. The interconnect bridge, as the core of high-density interconnection, can provide short-distance, high-bandwidth inter-chip interconnect paths, using metal pads directly bonded or attached to the outermost circuit layer. Subsequently, a molding process can be used to form a molding layer to encapsulate the outermost circuit and interconnect bridges as a whole, providing protection and structural stability. To connect the internal interconnect bridges and circuits to the outside, laser drilling technology can be used to form precise holes in the molding layer, and these holes can be filled by a metallization process to form conductive interconnect structures; these conductive interconnect structures serve as vertical interconnect paths, connecting the embedded interconnect bridges, the external metal pads on the substrate, and the final external connection terminals. Therefore, the entire process of manufacturing this packaging substrate can be carried out through a series of steps compatible with domestic processes, realizing the compact integration and efficient interconnection of multiple chips on a single common substrate, thereby overcoming the bottlenecks faced by existing advanced packaging technologies.

[0007] In addition, the packaging substrate for buried interconnect bridges proposed according to the present invention may also have the following additional technical features: Optionally, the conductive interconnect structure is a via penetrating the molding layer, and the via is formed by laser drilling and metallization of the molding layer.

[0008] Optionally, the interconnect bridges are multiple, spaced apart, and each interconnect bridge is attached or bonded to a metal disk of at least one of the outermost circuit layers.

[0009] Furthermore, the interconnect bridge is a silicon bridge, a glass bridge, and / or a ceramic bridge.

[0010] Furthermore, the silicon bridge is a silicon bridge containing TSV, the glass bridge is a glass bridge containing TGV, and the ceramic bridge is a ceramic bridge containing TCV.

[0011] Furthermore, the plurality of conductive interconnect structures are electrically connected one-to-one to the plurality of interconnect bridges and the metal disks of the plurality of outermost circuit layers that are not bonded or attached to the interconnect bridges.

[0012] Optionally, the interconnect bridge is attached to the metal disk of the outermost circuit layer via a chip attachment film or reflow soldering.

[0013] Optionally, the outermost circuit layer is also formed on the second surface of the core board, and the outermost circuit layer on the second surface also has the metal disk.

[0014] Furthermore, a solder resist layer is provided on the second surface of the core board, and a window is provided on the solder resist layer at the position of the metal disk of the outermost circuit layer on the second surface.

[0015] Furthermore, a molding layer is also formed on the second surface of the core board, the molding layer covers the outermost circuit layer of the second surface, and a through hole is formed at the position of the metal disk of the outermost circuit layer to expose the metal disk.

[0016] Optionally, the external connection terminal is a solder ball or a bump.

[0017] Optionally, the substrate includes a substrate, redistribution structures disposed on two opposite surfaces of the substrate, and conductive pillars interconnecting the two redistribution structures, wherein the redistribution structures have alternating circuit layers and dielectric layers; the substrate is an organic copper-clad laminate, a ceramic substrate, or a glass substrate.

[0018] To achieve the above objectives, a second aspect of the present invention provides a method for fabricating the above-mentioned buried interconnect bridge packaging substrate, comprising the following steps: A core board is provided, wherein the core board is a substrate or PCB board without a solder resist layer, and the core board has a first surface and a second surface opposite to each other. An outermost circuit layer electrically connected to the circuit layer within the core board is formed on the first surface of the core board, and the outermost circuit layer has a metal disk; Provide interconnect bridges and attach or bond the interconnect bridges to the metal disk of the outermost circuit layer; A molding layer is formed on the first surface of the core board, the outermost circuit layer, and the interconnect bridge, the molding layer covering the interconnect bridge; Multiple conductive interconnect structures are formed on the molding layer by laser drilling followed by metallization, which penetrate the molding layer and are electrically connected to the outermost circuit layer and the interconnect bridge, respectively. Multiple external connection terminals are formed one-to-one on the side of the multiple conductive interconnect structures away from the core board.

[0019] According to the method for manufacturing a packaging substrate for buried interconnect bridges of the present invention, the entire process of the method involves a series of steps compatible with domestic processes to manufacture the packaging substrate for buried interconnect bridges. This method can reuse PCB production line equipment, utilize the mature domestic PCB process system, and does not rely on high-end wafer equipment. It breaks through the dependence of existing advanced packaging technologies on high-end equipment, achieves a balance between high-density interconnects and industrialization feasibility, and provides a feasible path for domestic advanced packaging.

[0020] Optionally, the outermost circuit layer is formed on the first surface of the core board by laser drilling followed by metallization.

[0021] Optionally, the method includes providing a plurality of interconnect bridges and spacing the plurality of interconnect bridges apart, each of the interconnect bridges being attached or bonded to a metal disk of at least one of the outermost circuit layers.

[0022] Optionally, the outermost circuit layer is formed on the second surface of the core board, the outermost circuit layer on the second surface also having a metal disk; and a solder resist layer or a molding layer is provided on the second surface.

[0023] Furthermore, if a solder resist layer is provided on the second surface, a window is provided on the solder resist layer at the position of the metal disk of the outermost circuit layer on the second surface; if a molding layer is provided on the second surface, the molding layer covers the outermost circuit layer of the second surface, and a through hole is provided at the position of the metal disk of the outermost circuit layer to expose the metal disk.

[0024] Furthermore, the solder resist layer is formed after the molding layer on the first surface is formed; the molding layer on the second surface is formed simultaneously with the molding layer on the first surface.

[0025] To achieve the above objectives, a third aspect of the present invention provides a semiconductor packaging structure, comprising: At least two external chips; The package substrate of the aforementioned buried interconnect bridge is coupled to the at least two external chips through the external connection terminals, and the at least two external chips are interconnected through the interconnect bridge.

[0026] According to a semiconductor packaging structure of the present invention, the above-mentioned packaging substrate with embedded interconnect bridges serves as a platform for high-performance multi-chip integration. Through the embedded interconnect bridges inside the packaging substrate, high-bandwidth, low-latency interconnection between multiple external functional chips (such as CPU, GPU, HBM memory, AI accelerator, etc.) can be achieved, thereby constructing a compact, high-performance heterogeneous integrated system to meet the requirements of AI and HPC fields for extreme integration and performance.

[0027] Optionally, there are three or more external chips and multiple interconnect bridges. Each interconnect bridge is electrically connected to a different external chipset to achieve interconnection between the multiple external chips. In other words, if there are more external chips (such as CPU, GPU, multiple HBMs), multiple embedded interconnect bridges can be used to connect different chipsets respectively, further improving system bandwidth. Attached Figure Description

[0028] Figure 1 This is a cross-sectional schematic diagram of the packaging substrate of the buried interconnect bridge according to an embodiment of the present invention; Figure 2This is a schematic flowchart illustrating the fabrication method of the packaging substrate for the buried interconnect bridge according to an embodiment of the present invention. Figures 3-9 This is a schematic cross-sectional view of the substrate for each step of the method for manufacturing the packaging substrate of the buried interconnect bridge according to an embodiment of the present invention. Figure 10 This is a cross-sectional schematic diagram of the semiconductor packaging structure according to an embodiment of the present invention; Label Explanation: Packaging substrate 1; Core board 100, first surface 100a, second surface 100b; The outermost circuit layer is 200, and the metal disk is 210; Interconnect bridge 300, pad 310; Molding layer 400; Multiple conductive interconnect structures 500; Multiple external connection terminals 600; Solder mask 700; External chip 2. Detailed Implementation

[0029] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0030] This application is based on the following considerations: In the current global AI chip and high-performance computing (HPC) field, the demand for high-density interconnects is growing, but existing advanced packaging technologies face the dilemma of tight production capacity, high costs, and reliance on foreign core equipment, which seriously restricts the independent development of the domestic AI industry.

[0031] To this end, this application proposes an advanced packaging technology that is compatible with domestic processes, low in cost, and capable of high-density interconnection; aiming to provide a reliable packaging solution for domestic AI chips and HPC processors.

[0032] Specifically, according to one or more embodiments of the embedded interconnect bridge packaging substrate, the packaging substrate uses a substrate or PCB board without a solder mask layer as the core board, providing mechanical support and the initial electrical wiring layer. The substrate or PCB board without a solder mask layer is a board that has not been coated with solder mask after the required circuit fabrication is completed. The substrate is mainly manufactured using SAP / mSAP processes, while the PCB board uses a tenting process. The main difference between these two products is that the wiring on the substrate is finer than that on the PCB board. Based on this, laser drilling and electroplating processes (common processes in PCB board manufacturing, such as high-density interconnect (HDI) boards) can be used to form the outermost circuit and metal pad, providing connection points for the embedding of the interconnect bridge. As the core of high-density interconnect, the interconnect bridge can provide short-distance, high-bandwidth inter-chip interconnect paths, using a metal pad directly bonded or bonded to the outermost circuit layer. Subsequently, a molding process (such as plastic encapsulation in integrated circuit packaging) can be used to form a molding layer to encapsulate the outermost circuit and the interconnect bridge as a whole, providing protection and structural stability. To connect internal interconnect bridges and circuits to the outside, laser drilling technology can be used to form precise holes in the molding layer. These holes are then filled using metallization processes (such as electroplating, commonly used in PCB manufacturing) to form conductive interconnect structures. These conductive interconnect structures serve as vertical interconnect paths, connecting the embedded interconnect bridges, external metal pads on the substrate, and finally, external connection terminals. Thus, the entire process of manufacturing this packaging substrate can be carried out through a series of steps compatible with domestic processes, achieving compact integration and efficient interconnection of multiple chips on a single common substrate. This focuses on the independent research and development and production of high-performance AI acceleration modules for domestic data centers. These modules typically integrate multiple high-power AI processing units (such as custom ASICs or GPUs) and high-bandwidth memory (HBM), placing extremely high demands on packaging integration, interconnect density, and long-term reliability. By adopting this domestically developed advanced packaging technology, manufacturing costs can be effectively reduced, dependence on foreign advanced packaging capacity can be eliminated, and the deployment of domestically produced AI chips in the data center field can be accelerated.

[0033] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0034] Example 1 Figure 1 A package substrate for buried interconnect bridges according to one or more embodiments is shown.

[0035] refer to Figure 1 The encapsulation substrate 1 for the buried interconnect bridge includes: a core board 100, an outermost circuit layer 200, an interconnect bridge 300, a molding layer 400, multiple conductive interconnect structures 500, and multiple external connection terminals 600. The core board 100 is a substrate or PCB board without a solder mask layer. The core board 100 has a first surface 100a and a second surface 100b. The outermost circuit layer 200 is formed on the first surface 100a and electrically connected to the circuit layer in the core board 100. The outermost circuit layer 200 has a metal disk 210. The interconnect bridge 300 is attached or bonded to the metal disk 210 of the outermost circuit layer 200. The molding layer 400 is formed on the first surface 100a, the outermost circuit layer 200 and the interconnect bridge 300, and covers the interconnect bridge 300. A plurality of conductive interconnect structures 500 penetrate the molding layer 400 and are electrically connected to the metal disk 210 of the outermost circuit layer 200 and the interconnect bridge 300, respectively, to provide an electrical path to an external chip. A plurality of external connection terminals 600 are electrically connected one-to-one to the side of the plurality of conductive interconnect structures 500 away from the core board 100.

[0036] In other words, the packaging substrate 1 of the buried interconnect bridge directly uses a substrate or PCB board without a solder mask layer as the core board 100. The substrate or PCB board has at least two pre-fabricated initial wiring layers on opposite surfaces, rather than being fabricated from scratch on a bare substrate. The outermost wiring layer 200 can be formed on the first surface 100a of the core board 100 using processes such as laser drilling and electroplating, forming conductive traces 220 and metal disks 210. Some of the metal disks 210 can be electrically connected to the wiring layers within the core board 100, and some of the metal disks 210 can be laid out according to the design of the interconnect bridge 300. The interconnect bridge 300 can use existing bridging components, such as silicon bridges, glass bridges, etc., and the interconnect bridge 300 can use silicon bridges containing TSVs, etc. In this embodiment, the interconnect bridge 300 is directly bonded or attached to the metal disk 210 of the outermost circuit layer 200, and then covered by a molding layer 400 to embed the interconnect bridge 300 into the packaging substrate 1. This method of embedding the interconnect bridge 300 differs from the prior art in which a cavity is created in the packaging substrate to embed the interconnect bridge, and this method of embedding the interconnect bridge 300 is compatible with domestic PCB manufacturing processes. To extract the power from the interconnect bridge 300 and the outermost circuit layer 200, a through conductive interconnect structure 500 can be fabricated on the molding layer 400 using metallization methods such as laser drilling and electroplating. It can be understood that one end of the through conductive interconnect structure 500 can be electrically connected to the metal disk 210 of the outermost circuit layer 200 or the interconnect bridge 300, while the other end is exposed on the surface of the molding layer 400. Finally, an external connection terminal 600 is fabricated on the exposed end of the conductive interconnect structure, which can then be used to package external chips.

[0037] Therefore, the entire process of manufacturing the packaging substrate 1 can be carried out through a series of steps compatible with domestic processes, realizing the compact integration and efficient interconnection of multiple chips on a single common substrate, thereby overcoming the bottlenecks faced by existing advanced packaging technologies.

[0038] The core board 100 primarily serves as a crucial support for mechanical operation, circuit interconnection, and orderly signal routing, providing a stable and reliable foundation for subsequent structures such as the outermost circuit layer 200 and interconnect bridges 300. When the core board 100 is made of a substrate material, the substrate specifically includes a substrate, redistribution structures disposed on opposite surfaces of the substrate, and conductive pillars penetrating the substrate to achieve electrical interconnection of the redistribution structures on the two surfaces. The redistribution structure is a multi-layer interconnect architecture with alternating stacked circuit layers and dielectric layers, with interlayer conduction through metal vias to meet the requirements of high-density signal transmission. The substrate can be flexibly selected according to the packaging scenario, and can be an organic copper-clad laminate, a ceramic substrate, or a glass substrate to adapt to different reliability, heat resistance, and high-frequency transmission requirements. This substrate is an existing structure and will not be described in detail here.

[0039] According to one or more embodiments, the conductive interconnect structure 500 is a via through the molding layer 400, which is formed by laser drilling followed by metallization of the molding layer 400. That is, the conductive interconnect structure 500 can be fabricated on the molding layer 400 by forming through holes that expose metal disks through laser drilling, and then metallizing the through holes to form vias. The metallization process can be electroplating to fill the holes. These vias serve as vertical interconnect paths, connecting the embedded interconnect bridge 300, the metal disk 210 on the core board 100, and the final external connection terminals.

[0040] According to one or more embodiments, the molding layer 400 uses existing molding materials. For example, an epoxy resin mold is used to mold the first surface of the core board 100 to form the molding layer 400, which covers the interconnect bridge 300 and the outermost circuit layer 200.

[0041] According to one or more embodiments, multiple interconnect bridges 300 are arranged at intervals, each interconnect bridge 300 being bonded or attached to a metal disk 210 of at least one outermost circuit layer 200. For example, on a package substrate, two or more silicon bridge chips can be placed side by side, each silicon bridge chip responsible for connecting a specific set of logic chips and memory chips, maintaining a certain distance between them to avoid mutual interference. It is understood that the buried interconnect bridge approach of this embodiment can support the embedding of multiple interconnect bridges 300 to achieve a more flexible and modular chip interconnect architecture. This helps to distribute hotspots, optimize signal integrity, and allow for the connection of more or different types of chipsets. For large AI chips or HPC systems, multiple interconnect bridges can be used to build a distributed high-bandwidth interconnect network, improving overall performance and scalability.

[0042] In this embodiment, the interconnect bridge 300 can be a silicon bridge, a glass bridge, and / or a ceramic bridge. Silicon bridges, glass bridges, or ceramic bridges can be fabricated using existing processes. For example, silicon bridges can be commercially available through-silicon via (TSV) silicon interconnect bridges or passive silicon interposers, fabricated using standard wafer-level processes, including silicon wafer thinning, deep silicon etching to form TSV channels, copper plating to fill the channels, metal sputtering on the silicon wafer surface, and photolithography to form a redistribution layer (RDL), followed by wafer dicing to obtain independent silicon bridges. Glass bridges can be commercially available through-glass via (TGV) glass interconnect bridges, fabricated using existing laser drilling or wet etching processes. The process involves fabricating TGV vias, metallizing the via walls, and filling with copper to achieve vertical conductivity. Subsequently, a dielectric layer is deposited, and metal wiring forms surface interconnects. After cutting, the finished glass bridge is obtained. Ceramic bridges can be alumina ceramic bridges or aluminum nitride ceramic bridges containing ceramic vias (TCVs). Existing thick-film printing, high-temperature co-firing, or low-temperature co-firing ceramic (HTCC / LTCC) processes are used. TCVs are formed by drilling and filling with metal paste, while surface metal wiring is simultaneously fabricated. After sintering, the ceramic bridge is cut to the required size. It should be noted that if the bridge is not a TSV silicon bridge or a non-TGV glass bridge, the interconnect bridge 300 must be bonded or attached to the metal disk 210 with its functional side (front side) facing upwards.

[0043] More specifically, multiple conductive interconnect structures 500 are electrically connected one-to-one to multiple interconnect bridges 300 and multiple outermost circuit layers 200 metal disks 210 that are not bonded to or attached to the interconnect bridges 300. Specifically, for the conductive interconnect structure 500 corresponding to the interconnect bridge 300, one end is precisely aligned with and electrically connected to the surface interconnect bonding pad (such as the TSV lead-out pad of the silicon bridge) of the interconnect bridge 300, and the other end extends to the outer surface of the molding layer 400 and forms a reliable electrical connection with the external connection terminal 600, realizing direct signal conduction between the interconnect bridge 300 and the external chip; while for the metal disk 210 that is not bonded to the outermost circuit layer 200 of the interconnect bridge 300, the corresponding conductive interconnect structure 500 is electrically connected to the metal disk 210 by surface contact at one end, and the other end is also connected to the external connection terminal 600, constructing an independent circuit path between the initial wiring layer of the core board 100 and the external chip. This ensures crosstalk-free transmission of interconnect signals. Independent conductive interconnect structures 500 carry both the high-speed interconnect signals of the interconnect bridge 300 and the conventional signals of the basic wiring of the core board 100, preventing interference between different signal types during transmission. This is particularly effective in reducing signal attenuation for the high-bandwidth data between AI / HPC chips carried by the interconnect bridge 300. Furthermore, when the number of external chips increases or functional partitions are adjusted, the conductive interconnect structures 500 corresponding to the metal disks 210 not attached to the interconnect bridge 300 can serve as expansion interfaces. This allows for the addition of new connection paths between external chips and the core board 100 without altering the core interconnect architecture of the interconnect bridge 300, improving the compatibility and scalability of the packaging structure. Simultaneously, this connection method improves packaging yield. If a conductive interconnect structure 500 fails, only the circuit function of the corresponding path is affected, preventing the failure of the entire packaging substrate and reducing the overall risk of scrap.

[0044] According to one or more embodiments, interconnect bridge 300a (with TSV, TGV, or TCV) is bonded to the metal disk 210 of the outermost circuit layer 200 by thermoforming or mass reflow bonding, and interconnect bridge 300b (without TSV, TGV, or TCV) is bonded to the metal disk 210 of the outermost circuit layer 200 by die attach film. The film (DAF) is bonded to the independent large metal disk 210 of the outermost circuit layer 200. When bonding the interconnect bridge 300b, a chip adhesion film is used, and a thermosetting epoxy resin DAF is selected. Its thickness is adapted to the gap design between the interconnect bridge 300b and the metal disk 210, which is 5-20μm. The DAF needs to be pre-bonded on the mounting surface of the interconnect bridge 300, and then aligned with the metal disk 210 for bonding. When bonding the interconnect bridge 300a, reflow soldering is used. Flux needs to be printed on the surface of the metal disk 210 first. The flux printing thickness is 5-10μm. Then the interconnect bridge 300a is precisely placed on the flux and then sent to the reflow oven. After the solder paste melts, it wets the metal solder area of ​​the metal disk 210 and the interconnect bridge 300a. After cooling, the solder pad 310 is formed. Next, underfill is performed using capillary underfill adhesive. The underfill adhesive is made of underfill epoxy resin, and capillary action is used to fill the entire gap. It is then cured at 150-180℃ for 60-90 minutes. This underfill process effectively enhances the mechanical strength and reliability between the interconnect bridge 300a and the metal disk 210, disperses thermal stress, and prevents fatigue cracking of the solder joints. In this embodiment, the silicon bridges bonded using thermocompression bonding or reflow soldering contain TSV; the silicon bridges bonded using DAF film do not contain TSV.

[0045] According to one or more embodiments, the second surface 100b of the core board 100 also has an outermost circuit layer, and the outermost circuit layer of the second surface 100b also has a metal disk. The outermost circuit layer 200 of the second surface 100b can be fabricated using the same process as the outermost circuit layer of the first surface 100a, ensuring structural consistency and process compatibility. Specifically, the outermost circuit layer 200 of the second surface 100b uses the second surface 100b substrate of the core board 100 as a support, and is formed by laser drilling and copper electroplating. The ends of the outermost circuit layer 200 also have metal disks, and the surface of the metal disks is treated with electroless nickel gold (ENIG) or electroless tin (Immersion Tin) to improve the solderability and oxidation resistance of the metal disks. Meanwhile, the outermost circuit layer 200 of the second surface 100b is electrically interconnected with the outermost circuit layer 200 of the first surface 100a through a pre-set conductive via (such as a metallized via) inside the core board 100, forming a complete circuit path that runs through the core board.

[0046] Furthermore, a solder mask layer 700 is provided on the second surface 100b of the core board 100. This solder mask layer 700 can be green solder mask, which is applied to the surface of the outermost circuit layer 200 of the second surface 100b by screen printing or spraying. A window 710 is provided in the solder mask layer 700 corresponding to the position of the metal pad of the outermost circuit layer 200 of the second surface 100b. The formation of the solder mask layer 700 and the opening of the window in the solder mask layer 700 are common practices in PCB manufacturing and are relatively low in cost.

[0047] According to one or more embodiments, the external connection terminal 600 is a solder ball or a bump. If the external connection terminal 600 is a solder ball, such as a NiSn solder ball, the diameter of the solder ball is designed according to the interconnection requirements, and its forming process can be a ball-mounting process. If the external connection terminal 600 is a bump, a micro bump can be used as the connection terminal. Using micro bumps as external connection terminals can achieve smaller spacing and higher I / O density compared to traditional solder balls or larger bumps. This is crucial for applications requiring a large number of high-speed signal transmissions, such as AI chips and high-performance computing (HPC), and helps to further improve the integration and electrical performance of the package. Specifically, a micro bump array with a diameter and spacing much smaller than that of traditional solder balls can be fabricated on the surface of the molding layer 400 through processes such as electroplating or printing for high-density connection with external chips.

[0048] According to one or more embodiments, this application also provides a method for fabricating a packaging substrate with buried interconnect bridges. Please refer to [reference needed]. Figure 2 The diagram shows the process flow of this manufacturing method, which includes the following steps: S1: Provide a core board, wherein the core board is a substrate or PCB board without a solder resist layer, and the core board has a first surface and a second surface opposite to each other; S2: An outermost circuit layer electrically connected to the circuit layer within the core board is formed on the first surface of the core board, the outermost circuit layer having a metal disk; S3: Provide an interconnect bridge and attach or bond the interconnect bridge to the metal disk of the outermost circuit layer; S4: A molding layer is formed on the first surface of the core board, the outermost circuit layer and the interconnect bridge, the molding layer covering the interconnect bridge; S5: A metal disk and an interconnect bridge are formed on the molding layer by means of laser drilling followed by metallization, which penetrate the molding layer and are electrically connected to the outermost circuit layer respectively. S6: Multiple external connection terminals are formed one-to-one on the side of the multiple conductive interconnect structures away from the core board.

[0049] In other words, the method first prepares a substrate with incomplete solder resist coating as a core board 100. This core board mainly serves to support and connect wiring, and its material can be a substrate or PCB board, etc. Based on the core board material, the outermost circuit layer 200 and metal pad 210 (Cu pad) can be formed on the first surface 100a of the core board 100 using processes such as laser drilling and electroplating. Next, the interconnect bridge 300 is precisely bonded to the formed Cu pad using bonding or thermoforming bonding processes. Then, the first surface 100a of the core board 100 is molded to encapsulate the bonded interconnect bridge 300 and the outermost circuit layer 200. Next, holes are formed on the molding layer 400 using laser drilling technology, and these holes are filled by metallization methods such as electroplating to form a conductive interconnect structure 500. Finally, external connection terminals 600 of the packaging substrate 1 are fabricated on the side of the conductive interconnect structure 500 away from the core board 100 to facilitate connection with external chips.

[0050] The entire process of this method involves a series of steps compatible with domestic processes to create a packaging substrate for buried interconnect bridges. It can reuse PCB production line equipment and utilize the mature domestic PCB process system without relying on high-end wafer equipment. This breaks through the dependence of existing advanced packaging technologies on high-end equipment, achieving a balance between high-density interconnects and industrialization feasibility. It is suitable for scenarios such as AI chips, high-performance computing, and mobile devices, meeting the dual requirements of computing power and size for next-generation electronic devices, and promoting the localization of advanced packaging in China.

[0051] Specifically, please refer to Figures 3 to 8 as well as Figure 1 A cross-sectional schematic diagram of the packaging substrate is shown, illustrating each step of the fabrication method for the above-described embedded interconnect bridge packaging substrate.

[0052] First, refer to Figure 3 Step S1: Provide a core board 100, which is a substrate or PCB board without a solder mask layer. The core board 100 has a first surface 100a and a second surface 100b with opposite surfaces. For example, a domestic FR-4 organic copper clad laminate (substrate thickness 1.0-1.6 mm, the mainstream specification of domestic PCB) is used as the core board. The core board 100 has multiple pre-fabricated circuit layers, and interlayer conduction is achieved through metallized vias. Both surfaces of the organic copper clad laminate have initial wiring layers and no solder mask layer.

[0053] Next, refer to Figure 4Step S2: An outermost circuit layer 200 electrically connected to the circuit layers within the core board 100 is formed on the first surface 100a of the core board 100. The outermost circuit layer 200 has a metal disk 210. Specifically, laser drilling and electroplating processes can be used to form conductive traces and a metal disk, which is compatible with domestic PCB equipment. Laser drilling can be performed using a domestic nanosecond CO2 laser drilling machine, drilling holes at the positions of the metal disks corresponding to the circuit layers inside the core board on the first surface 100a, with a hole diameter of 45-100 μm. After drilling, plasma etching or chemical desmearing is performed to remove residue from the holes. Then, copper electroplating is used to form conductive traces and a metal disk to create the outermost circuit layer 200. In this embodiment, the line width / spacing of the outermost circuit layer 200 can be ≥8 μm / 8 μm. Additionally, as... Figure 4 As shown, the outermost circuit layer 200 and metal disk can also be formed on the second surface 100b of the core board 100.

[0054] Then, refer to Figure 5 Step S3: Provide an interconnect bridge 300 and bond or attach the interconnect bridge 300 to the metal disk 210 of the outermost circuit layer 200. Specifically, a domestically produced silicon bridge containing TSV can be selected, and a domestically compatible bonding method (DAF / reflow soldering) can be selected. For example, a DAF film can be pre-attached to the silicon bridge mounting surface, and then a domestically produced high-precision pick-and-place machine can be used to align the silicon bridge with the reserved metal disk 210 for bonding. Additionally, if... Figure 5 As shown, multiple interconnect bridges 300 can be provided, spaced apart. The interconnect bridges 300 can be of different models. Each interconnect bridge 300 has a DAF film pre-attached to its mounting surface before being attached to the metal disk 210. Alternatively, some interconnect bridges 300 can be mounted on the metal disk 210 using reflow soldering or thermoforming. This spaced arrangement of multiple interconnect bridges 300 supports distributed high-bandwidth interconnect networks, suitable for scenarios such as AI accelerator cards and HPC servers.

[0055] Next, refer to Figure 6 Step S4: A molding layer 400 is formed on the first surface 100a, the outermost circuit layer 200, and the interconnect bridge 300 of the core board 100, and the molding layer 400 covers the interconnect bridge 300. Specifically, a domestically produced transfer molding machine can be used to mold epoxy resin on the first surface 100a, the outermost circuit layer 200, and the interconnect bridge 300 of the core board 100, and completely cover the interconnect bridge 300. The thickness of the molding layer 400 covers the top of the interconnect bridge 300 by ≥5 μm.

[0056] Subsequently, reference Figure 7After forming the molding layer 400, a solder resist layer 700 covering the outermost circuit layer of the second surface 100b can be formed on the second surface 100b. The solder resist layer 700 can be made using domestically produced green solder mask. The solder resist layer 700 can be applied using a domestic screen printing machine, followed by pre-baking, exposure using a domestic ultraviolet exposure machine, development using a domestic spray developing machine, and then curing. Finally, a window is made in the solder resist layer 700 at the position corresponding to the metal disk of the outermost circuit layer of the second surface 100b to complete the surface treatment nickel-palladium-gold layer, which can be used to subsequently fabricate the external connection terminals corresponding to the second surface 100b.

[0057] Next, refer to Figure 8 Step S5: Multiple conductive interconnect structures 500 are formed on the molding layer 400 through the molding layer 400 and electrically connected to the metal disk and interconnect bridge 300 of the outermost circuit layer 200, respectively, using a laser drilling and metallization process. Specifically, a domestically produced laser drilling machine can be used to drill holes in the molding layer 400. The hole positions are divided into two categories: ① aligned with the surface solder area of ​​the interconnect bridge 300; ② aligned with the metal disk 210 without interconnect bridges. After drilling, plasma cleaning removes residue. Then, copper is electroplated to completely fill the holes, forming vias that penetrate the molding layer 400, connecting the interconnect bridge solder area or the metal disk 210 to achieve vertical conductivity.

[0058] Finally, refer to Figure 1 Step S6: Form multiple external connection terminals 600 one-to-one on the side of the multiple conductive interconnect structures 500 away from the core board 100. The external connection terminals 600 can be domestically compatible terminal types, such as solder balls or micro-bumps. Solder balls can be domestically produced NiSn solder balls, manufactured using a ball-planting process; micro-bumps can be electroplated CuNi micro-bumps, etc.

[0059] At this point, it is possible to produce something like... Figure 1 The encapsulation substrate 1 of the buried interconnect bridge is shown.

[0060] Example 2 The overall structure and core manufacturing process of this embodiment are largely the same as those of Embodiment 1, and the similarities will not be repeated here. The differences are as follows: Figure 9As shown, the second surface 100b of the core board 100 in this embodiment is also formed with a molding layer 400. The molding layer 400 covers the outermost circuit layer 200 of the second surface 100b and forms a through hole at the position of the metal disk of the outermost circuit layer 200 to expose the metal disk. In terms of process implementation, the molding layer 400 of the second surface 100b is prepared by synchronous molding with the molding layer 400 of the first surface 100a. Epoxy molding compound (EMC) of the same type as the first surface 100a is used. A one-time molding process with double-sided synchronous transfer molding (using existing encapsulation technology, not detailed here) ensures uniformity in material, thickness, and curing degree of the molding layers 400 on both sides of the core board 100. This effectively counteracts the unidirectional stress caused by single-sided molding of the core board 100, significantly reducing the overall warpage deformation of the core board 100. This provides a stable structural foundation for subsequent high-precision processes such as laser drilling and ball bonding. Simultaneously, the synchronous molding process reduces an independent molding step, shortens the overall process cycle, and improves mass production efficiency. Then, a laser drilling machine can be used to create through-holes on the molding layer 400 at the location corresponding to the metal disk of the outermost circuit layer, exposing the metal disk. Afterward, a nickel-palladium-gold surface treatment is applied to the exposed metal disk, allowing for the subsequent fabrication of external connection terminals corresponding to the second surface 100b.

[0061] According to one or more embodiments, this application also proposes a semiconductor packaging structure, such as... Figure 10 As shown, the semiconductor package structure includes at least two external chips 2 and a package substrate 1 with embedded interconnect bridges as described above. The package substrate 1 is coupled to the at least two external chips 2 through external connection terminals 600, and the at least two external chips 2 are interconnected through interconnect bridges 300. For example, a silicon bridge is embedded inside a package substrate 1. On top of this package substrate, a CPU chip and two HBM memory chips are mounted using flip-chip bonding or other methods. In this case, high-speed communication between the CPU and HBM is achieved through the silicon bridge inside the package substrate 1, forming a high-performance computing unit.

[0062] If there are more external chips (such as CPU, GPU, multiple HBMs), multiple embedded interconnect bridges 300 can be used to connect different chipsets respectively, such as Figure 1 As shown, it can realize high-bandwidth, low-latency interconnection between multiple external functional chips (such as CPU, GPU, HBM memory, AI accelerator, etc.), thereby building a compact, high-performance heterogeneous integrated system to meet the needs of AI, HPC and other fields for extreme integration and performance.

[0063] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0065] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0066] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0067] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0068] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A packaging substrate for buried interconnect bridges, characterized in that, include: The core board is a substrate or PCB board without a solder resist layer, and the core board has a first surface and a second surface opposite to each other. The outermost circuit layer is formed on the first surface and electrically connected to the circuit layer within the core board, the outermost circuit layer having a metal disk; Interconnect bridges are attached or bonded to the metal disk of the outermost circuit layer; A molding layer is formed on the first surface, the outermost circuit layer, and the interconnect bridge, and covers the interconnect bridge; Multiple conductive interconnect structures extend through the molding layer and are electrically connected to the metal disk of the outermost circuit layer and the interconnect bridge, respectively, to provide an electrical path to an external chip; Multiple external connection terminals are electrically connected one-to-one to the side of the multiple conductive interconnect structures away from the core board.

2. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The conductive interconnect structure is a via that penetrates the molding layer, and the via is formed by laser drilling and metallization of the molding layer.

3. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The interconnect bridges are multiple and spaced apart, with each interconnect bridge bonded or bonded to a metal disk of at least one of the outermost circuit layers.

4. The packaging substrate for the buried interconnect bridge as described in claim 3, characterized in that, The interconnect bridge is a silicon bridge, a glass bridge, and / or a ceramic bridge.

5. The packaging substrate for the buried interconnect bridge as described in claim 4, characterized in that, The silicon bridge is a silicon bridge containing TSV, the glass bridge is a glass bridge containing TGV, and the ceramic bridge is a ceramic bridge containing TCV.

6. The packaging substrate for the buried interconnect bridge as described in claim 3, characterized in that, The plurality of conductive interconnect structures are electrically connected one-to-one to the plurality of interconnect bridges and the metal disks of the plurality of outermost circuit layers that are not bonded or attached to the interconnect bridges.

7. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The interconnect bridge is attached to the metal disk of the outermost circuit layer via a chip attachment film or reflow soldering.

8. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The outermost circuit layer is also formed on the second surface of the core board, and the outermost circuit layer on the second surface also has the metal disk.

9. The packaging substrate for the buried interconnect bridge as described in claim 8, characterized in that, The second surface of the core board is provided with a solder resist layer, and the solder resist layer has a window at the position of the metal disk of the outermost circuit layer on the second surface.

10. The packaging substrate for the buried interconnect bridge as described in claim 8, characterized in that, A molding layer is also formed on the second surface of the core board. The molding layer covers the outermost circuit layer of the second surface and forms a through hole at the position of the metal disk of the outermost circuit layer to expose the metal disk.

11. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The external connection terminals are solder balls or bumps.

12. The packaging substrate for the buried interconnect bridge as described in claim 1, characterized in that, The substrate includes a substrate, redistribution structures disposed on two opposite surfaces of the substrate, and conductive pillars interconnecting the two redistribution structures. The redistribution structures have alternating circuit layers and dielectric layers. The substrate is an organic copper-clad laminate, a ceramic substrate, or a glass substrate.

13. A method for manufacturing a packaging substrate for buried interconnect bridges according to any one of claims 1-12, characterized in that, Includes the following steps: A core board is provided, wherein the core board is a substrate or PCB board without a solder resist layer, and the core board has a first surface and a second surface opposite to each other. An outermost circuit layer electrically connected to the circuit layer within the core board is formed on the first surface of the core board, and the outermost circuit layer has a metal disk; Provide interconnect bridges and attach or bond the interconnect bridges to the metal disk of the outermost circuit layer; A molding layer is formed on the first surface of the core board, the outermost circuit layer, and the interconnect bridge, the molding layer covering the interconnect bridge; Multiple conductive interconnect structures are formed on the molding layer by laser drilling followed by metallization, which penetrate the molding layer and are electrically connected to the outermost circuit layer and the interconnect bridge, respectively. Multiple external connection terminals are formed one-to-one on the side of the multiple conductive interconnect structures away from the core board.

14. The manufacturing method as described in claim 13, characterized in that, The outermost circuit layer is formed on the first surface of the core board by laser drilling followed by metallization.

15. The manufacturing method as described in claim 13, characterized in that, A plurality of interconnect bridges are provided and the plurality of interconnect bridges are spaced apart, each of the interconnect bridges being attached or bonded to a metal disk of at least one of the outermost circuit layers.

16. The manufacturing method as described in claim 13, characterized in that, It also includes forming the outermost circuit layer on the second surface of the core board, the outermost circuit layer on the second surface also having a metal disk; and providing a solder resist layer or a molding layer on the second surface.

17. The manufacturing method as described in claim 16, characterized in that, If a solder resist layer is provided on the second surface, a window is provided on the solder resist layer at the position of the metal disk of the outermost circuit layer on the second surface; if a molding layer is provided on the second surface, the molding layer covers the outermost circuit layer of the second surface, and a through hole is provided at the position of the metal disk of the outermost circuit layer to expose the metal disk.

18. The manufacturing method as described in claim 17, characterized in that, The solder resist layer is formed after the molding layer on the first surface is formed; the molding layer on the second surface is formed simultaneously with the molding layer on the first surface.

19. A semiconductor packaging structure, characterized in that, include: At least two external chips; And the package substrate of any one of claims 1-12 with an embedded interconnect bridge, wherein the package substrate is coupled to the at least two external chips through the external connection terminal, and the at least two external chips are interconnected through the interconnect bridge.

20. The semiconductor packaging structure as described in claim 19, characterized in that, There are three or more external chips and multiple interconnect bridges. Each of the multiple interconnect bridges is electrically connected to a different external chip group to achieve interconnection between the multiple external chips.

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