Thread scheduling method and apparatus, electronic device, and storage medium

Abstract

This disclosure relates to a thread scheduling method, apparatus, electronic device, and storage medium. The thread scheduling method includes: obtaining a first parameter, which characterizes the number of processor cycles in which processor wait events occurred during the execution of a target thread in a historical scheduling cycle; a processor wait event characterizes a running event that causes a processor core to be in a waiting state; determining a second parameter based on the first parameter, which characterizes whether the occurrence of processor wait events during the execution of the target thread in a historical scheduling cycle leads to inefficient operation of the processor core; and scheduling the target thread based on the second parameter. This method uses the number of processor cycles in a waiting state as a criterion for judging processor core performance, subdividing the thread execution process from the perspective of processor cycles. This allows for a more accurate understanding of the target thread's requirements for processor core performance, ensuring that the target thread is scheduled to the most suitable processor core and maximizing the utilization of processor resources.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a thread scheduling method, apparatus, electronic device, and storage medium. Background Technology

[0002] Thread scheduling based on the duty cycle of a task running on a specific processor (CPU) core over a past period is the most widely used thread scheduling technique. This technique determines the processor load during that period by statistically analyzing the time a processor core spends running the task, thus understanding the task's performance requirements. Threads within the task are then scheduled to the appropriate processor core based on these requirements. However, while the time spent running the task is based on statistics of the thread execution time within that task, a processor core is not always running a particular thread. Therefore, thread-based load tracking has limitations, leading to some deviations in thread scheduling results and preventing the optimal utilization of processor resources. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a thread scheduling method, apparatus, electronic device, and storage medium.

[0004] According to a first aspect of the present disclosure, a thread scheduling method is provided, the method comprising:

[0005] Obtain the first parameter, which represents the number of processor cycles in which processor wait events occur during the execution of the target thread in the historical scheduling cycle, and the processor wait event represents a running event that causes the processor core to be in a waiting state;

[0006] Based on the first parameter, a second parameter is determined, wherein the second parameter characterizes whether the processor wait event occurring during the execution of the target thread in the historical scheduling cycle will cause the processor core to run inefficiently;

[0007] The target thread is scheduled based on the second parameter.

[0008] In an exemplary embodiment, determining the second parameter based on the first parameter includes:

[0009] Obtain a third parameter, which characterizes the degree of impact of the processor wait event occurring during the runtime of the target thread on the performance of the processor core;

[0010] The first parameter is adjusted based on the third parameter to obtain the fourth parameter;

[0011] The second parameter is determined based on the fourth parameter and the first threshold.

[0012] In an exemplary embodiment, determining the second parameter based on the fourth parameter and the first threshold includes:

[0013] If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be a first set value. The first set value indicates that the processor core will run inefficiently when the processor wait event occurs during the historical scheduling cycle of the target thread.

[0014] If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be a second set value. The second set value indicates that the occurrence of the processor wait event during the operation of the target thread in the historical scheduling cycle will not cause the processor core to run inefficiently.

[0015] In one exemplary embodiment, scheduling the target thread based on the second parameter includes:

[0016] Determine the fifth parameter, which is the sum of the second parameters obtained from all scheduling interrupts;

[0017] The target thread is scheduled based on the fifth parameter and the second threshold.

[0018] In an exemplary embodiment, scheduling the target thread based on the fifth parameter and the second threshold includes:

[0019] If there are multiple first parameters, a target parameter is determined based on multiple fifth parameters and a preset function, wherein the preset function is used to merge multiple fifth parameters into the target parameter;

[0020] The target thread is scheduled based on the target parameter and the second threshold.

[0021] In an exemplary embodiment, scheduling the target thread based on the target parameter and the second threshold includes:

[0022] If the target parameter is greater than or equal to the second threshold, the target thread is prohibited from being scheduled to the high-performance processor core for a preset time period.

[0023] If the target parameter is less than the second threshold, the target processor core is determined based on the preset scheduling rules, and the target thread is scheduled to the target processor core.

[0024] In an exemplary embodiment, determining the target processor core based on a preset scheduling rule includes:

[0025] If the number of instructions used to perform floating-point operations in the target thread is greater than or equal to the third threshold, the target processor core is determined based on the first mapping relationship, wherein the first mapping relationship represents the mapping relationship between the number of instructions used to perform floating-point operations and the processor core.

[0026] If the processor wait event includes branch prediction failure and the fourth parameter associated with the branch prediction failure is greater than or equal to the fourth threshold, the target processor core is determined based on the second mapping relationship. The second mapping relationship represents the mapping relationship between the fourth parameter associated with the branch prediction failure and the processor core. The fourth parameter associated with the branch prediction failure is obtained by adjusting the first parameter associated with the branch prediction failure based on the third parameter associated with the branch prediction failure.

[0027] In one exemplary embodiment, the processor wait event includes at least one of a front-end pause, a back-end pause, and a branch prediction failure in the processor pipeline.

[0028] According to a second aspect of the present disclosure, a thread scheduling apparatus is provided, the apparatus comprising:

[0029] The acquisition module is configured to acquire a first parameter, which represents the number of processor cycles in which processor wait events occur during the execution of the target thread in a historical scheduling cycle, and the processor wait event represents a running event that causes the processor core to be in a waiting state.

[0030] The determination module is configured to determine a second parameter based on the first parameter, wherein the second parameter characterizes whether the occurrence of the processor wait event during the execution of the target thread in the historical scheduling cycle will cause the processor core to run inefficiently;

[0031] The scheduling module is configured to schedule the target thread based on the second parameter.

[0032] According to a third aspect of the present disclosure, an electronic device is provided, comprising:

[0033] processor;

[0034] Memory used to store processor-executable instructions;

[0035] The processor is configured to perform the method described in the first aspect of the embodiments of this disclosure.

[0036] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method described in the first aspect of the present disclosure.

[0037] The above-described method of this disclosure has the following beneficial effects: the method uses the number of processor cycles in the waiting state as the first parameter to subdivide the thread running process from the perspective of processor cycles, which can obtain the running state of the processor from the perspective of the processor. Then, using the first parameter as the judgment condition of the processor core performance, it can more accurately obtain the target thread's demand for the running performance of the processor core, thereby ensuring that the target thread is scheduled to the most suitable processor core and making the maximum use of processor resources.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0040] Figure 1 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment;

[0041] Figure 2 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment;

[0042] Figure 3 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment;

[0043] Figure 4 This is a block diagram illustrating a thread scheduling device according to an exemplary embodiment;

[0044] Figure 5 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0046] In some embodiments, if a processor core is occupied by tasks A, B, ..., n for a total of N milliseconds within a time period of M milliseconds, then the processor load during this time period is N / M. The time taken to run a single task is based on the execution time of its threads. Since processor load tracing is limited to the kernel layer, and kernel-level processor load tracing is thread-based, and threads, as the smallest unit of kernel scheduling, cannot be further subdivided, from the kernel layer's perspective, the processor load when executing a single thread is 100%. However, because the processor core's state includes waiting and running states, a processor core is not always in the running state when running a thread. Therefore, from the processor's perspective, the processor load when executing a single thread is not 100%. Thus, determining processor load based on the time taken to run a single thread has limitations, leading to some deviation in thread scheduling results and preventing the maximization of processor resource utilization.

[0047] In the exemplary embodiments of this disclosure, to overcome the problem of certain deviations in thread scheduling results in related technologies, a thread scheduling method is provided, comprising: obtaining a first parameter, the first parameter representing the number of processor cycles in which processor wait events occurred during the execution of a target thread in a historical scheduling cycle, wherein a processor wait event represents a running event that causes a processor core to be in a waiting state; determining a second parameter based on the first parameter, the second parameter representing whether the occurrence of processor wait events during the execution of a target thread in a historical scheduling cycle leads to inefficient operation of the processor core; and scheduling the target thread based on the second parameter. This method uses the number of processor cycles in a waiting state as the first parameter to subdivide the thread execution process from the perspective of processor cycles, enabling the understanding of the processor's running state from the processor's perspective. Furthermore, using the first parameter as a judgment condition for processor core performance allows for a more accurate understanding of the target thread's requirements for processor core performance, thereby ensuring that the target thread is scheduled to the most suitable processor core and maximizing the utilization of processor resources.

[0048] The thread scheduling method provided in this disclosure is applied to electronic devices, including mobile phones, tablets, personal computers, smart wearable devices, smart home devices, smart vehicle systems, etc.

[0049] In an exemplary embodiment of this disclosure, a thread scheduling method is provided. Figure 1 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment, such as... Figure 1 As shown, it includes the following steps:

[0050] Step S101: Obtain the first parameter. The first parameter represents the number of processor cycles in which processor wait events occur during the execution of the target thread in the historical scheduling cycle. The processor wait event represents the running event that causes the processor core to be in a waiting state.

[0051] Step S102: Based on the first parameter, determine the second parameter. The second parameter characterizes whether the processor wait event that occurs when the target thread runs in the historical scheduling cycle will cause the processor core to run inefficiently.

[0052] Step S103: Based on the second parameter, schedule the target thread.

[0053] In step S101, the operating system performs thread scheduling at each scheduling interrupt according to a preset scheduling cycle. The duration of the scheduling cycle is an empirical value, and the scheduling interrupt can also be called a scheduling interval. The historical scheduling cycle is the scheduling cycle before the current scheduling interruption. The target thread is any thread that needs to be scheduled. The target thread runs on a preset processor core during the historical scheduling cycle. If the historical scheduling cycle is the first scheduling cycle, the preset processor core is the pre-set default processor core. If the historical scheduling cycle is any of the other scheduling cycles, the preset processor core is the processor core that was scheduled at the last scheduling interruption. When a thread is running on a processor core, the processor core may be in a waiting state due to various factors, which is called a processor wait event. For example, if a thread needs to read data from memory, and the processor core does not need to work during the data reading process, the processor core will be in a waiting state. This involves counting the number of CPU cycles that experienced processor wait events during historical scheduling cycles. Specifically, it's the number of CPU cycles when a processor core was in a wait state. When a processor core is in a wait state, it may stall; therefore, the number of CPU cycles when a processor core stalls is also counted. The first parameter is the number of CPU cycles that experienced processor wait events during historical scheduling cycles. Here, a processor cycle represents the processor's clock cycle. This can also be seen as classifying CPU cycles based on their operating state, with the number of CPU cycles in a wait state serving as the first parameter. If different factors lead to different processor wait events, the first parameter corresponding to each processor wait event is counted.

[0054] In some implementations, a stall cycle counter is used to count the number of processor cycles in which processor wait events occur. The counter value is read at each scheduling interrupt, and the difference between the value read in the current scheduling interrupt and the value read in the previous scheduling interrupt is taken as the number of processor cycles in which processor wait events occur in the historical scheduling cycles. If different processor wait events occur, a corresponding counter is set for each processor wait event, and the number of processor cycles for each processor wait event is counted separately.

[0055] In some implementations, processor wait events include at least one of the following: front-end stall, back-end stall, and branch prediction failure. A front-end stall indicates processor wait due to a lack of front-end resources for instruction execution; a back-end stall indicates processor wait due to a lack of back-end resources for instruction execution; and a branch prediction failure indicates processor wait due to a failure to predict an instruction branch.

[0056] In one example, processor wait events include front-end stall, back-end stall, and branch prediction failure in the processor pipeline. Counters are set for each processor wait event: Front-End stall cycle counter, Back-End stall cycle counter, and Misprediction cycle counter. During the previous scheduling interrupt, the Front-End stall cycle counter had a value of A11, the Back-End stall cycle counter had a value of A21, and the Misprediction cycle counter had a value of A31. During the current scheduling interrupt, the Front-End stall cycle counter had a value of A12, the Back-End stall cycle counter had a value of A22, and the Misprediction cycle counter had a value of A32. Therefore, the first parameter B corresponding to the front-end stall is represented as: B = A12 - A11; the first parameter C corresponding to the back-end stall is represented as: C = A22 - A21; and the first parameter D corresponding to the branch prediction failure is represented as: D = A32 - A31.

[0057] In step S102, the number of processor wait events that occur during the target thread's execution in the historical scheduling cycle determines whether the processor wait event will lead to inefficient operation of the processor core. This is achieved by judging the second parameter based on the first parameter, using a preset rule. The preset rule is set according to the actual impact of the first parameter on the processor core's performance. For example, a larger first parameter indicates a longer processing time for the processor core in the wait state, resulting in poorer processor core performance. Therefore, the preset rule could be set as follows: when the first parameter is greater than a threshold, the second parameter indicates that a processor wait event during the target thread's execution in the historical scheduling cycle will lead to inefficient operation of the processor core; when the first parameter is less than the threshold, the second parameter indicates that a processor wait event during the target thread's execution in the historical scheduling cycle will not lead to inefficient operation of the processor core. Alternatively, if the processor core on which the target thread runs in the historical scheduling cycle is not a high-performance core, the magnitude of the first parameter has little impact on the processor core's performance. In this case, the preset rule could be set as follows: when the first parameter is any value, the second parameter indicates that a processor wait event during the target thread's execution in the historical scheduling cycle will not lead to inefficient operation of the processor core.

[0058] In step S103, after obtaining the second parameter, it becomes clear whether a processor wait event occurring during the target thread's historical scheduling cycle would lead to inefficient processor core operation. This allows the determination of the target thread's performance requirements for the processor core. By scheduling the target thread according to these performance requirements, it can be scheduled to a suitable processor core. In some implementations, if a processor wait event occurring during the target thread's historical scheduling cycle does not lead to inefficient processor core operation, the target thread can continue to be scheduled to a processor core with similar performance. Conversely, if a processor wait event occurring during the target thread's historical scheduling cycle would lead to inefficient processor core operation, the target thread can be scheduled to a processor core with lower performance.

[0059] In the exemplary embodiments of this disclosure, a first parameter is obtained. The first parameter represents the number of processor cycles in which processor wait events occur during the execution of the target thread in the historical scheduling cycle. A processor wait event represents a running event that causes the processor core to be in a waiting state. By using the number of processor cycles in a waiting state as the first parameter, the thread execution process is subdivided from the perspective of processor cycles, and the running state of the processor can be known from the processor's perspective. Then, the first parameter is used as a judgment condition for the processor core performance to determine the second parameter. The second parameter represents whether the occurrence of processor wait events during the execution of the target thread in the historical scheduling cycle will cause the processor core to run inefficiently. This allows for a more accurate understanding of the target thread's requirements for the running performance of the processor core. Based on the second parameter, the target thread is scheduled to ensure that the target thread is scheduled to the most suitable processor core, maximizing the utilization of processor resources.

[0060] In an exemplary embodiment of this disclosure, a thread scheduling method is provided. Figure 2 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment, such as... Figure 2 As shown, it includes the following steps:

[0061] Step S201: Obtain the first parameter. The first parameter represents the number of processor cycles in which processor wait events occur during the execution of the target thread in the historical scheduling cycle. The processor wait event represents the running event that causes the processor core to be in a waiting state.

[0062] Step S202: Obtain the third parameter, which represents the degree of impact of the processor wait event occurring during the runtime of the target thread on the performance of the processor core;

[0063] Step S203: Adjust the first parameter based on the third parameter to obtain the fourth parameter;

[0064] Step S204: Based on the fourth parameter and the first threshold, determine the second parameter. The second parameter characterizes whether the processor wait event that occurs when the target thread runs in the historical scheduling cycle will cause the processor core to run inefficiently.

[0065] Step S205: Determine the fifth parameter, which is the sum of the second parameters obtained from all scheduling interrupts;

[0066] Step S206: Based on the fifth parameter, schedule the target thread.

[0067] The specific implementation of step S201 is described in step S101, and will not be repeated here.

[0068] In step S202, the third parameter characterizes the impact of processor wait events occurring during the target thread's runtime on the processor core's performance. Different processor wait events may have different impacts on the same processor core, and the same processor wait event may also have different impacts on different processor cores. The third parameter is an empirical value; the larger the value of the third parameter, the greater the impact on the processor core's performance. A mapping table between processor wait events, processor cores, and the third parameter is pre-stored in the electronic device. During a historical scheduling cycle, when the target thread runs on a preset processor core, the third parameter matching the preset processor core and processor wait event is searched from this mapping table.

[0069] In step S203, the third parameter is used as the weight of the first parameter, and the product of the third parameter and the first parameter is taken as the fourth parameter. In one example, processor wait events include front-end pauses, back-end pauses, and branch prediction failures in the processor pipeline. The fourth parameter corresponding to each processor wait event is determined by the following formula:

[0070] valB=b×B

[0071] valC=c×C

[0072] valD=d×D

[0073] Where valB represents the fourth parameter corresponding to the front-end pause, b represents the third parameter corresponding to the front-end pause, B represents the first parameter corresponding to the front-end pause, valC represents the fourth parameter corresponding to the back-end pause, c represents the third parameter corresponding to the back-end pause, C represents the first parameter corresponding to the back-end pause, valD represents the fourth parameter corresponding to the branch prediction failure, d represents the third parameter corresponding to the branch prediction failure, and D represents the first parameter corresponding to the branch prediction failure.

[0074] In step S204, the first threshold is an empirical value, and different processor wait events correspond to different first thresholds. By comparing the fourth parameter and the first threshold, it is determined whether a processor wait event occurring during the target thread's historical scheduling cycle will lead to inefficient processor core operation, thus determining the second parameter. Since the fourth parameter comprehensively considers both the number of processor cycles in which processor wait events occur and the degree of impact of processor wait events on processor core performance, the performance of the processor core can be accurately judged based on the fourth parameter.

[0075] In some implementations, the second parameter is determined based on the fourth parameter and the first threshold, including the following two cases:

[0076] The first method is to determine the second parameter as the first set value if the fourth parameter is greater than or equal to the first threshold. The first set value indicates that the processor core will run inefficiently when the target thread encounters a processor wait event during the historical scheduling cycle.

[0077] The first setting is a positive number, used to record a single instance of inefficient processor core operation.

[0078] In one example, the first setting is 1. Processor wait events include front-end pauses, back-end pauses, and branch prediction failures in the processor pipeline. The fourth parameter corresponding to each processor wait event is denoted as valB, valC, and valD, respectively. The first threshold corresponding to each processor wait event is denoted as TB, TC, and TD, respectively. The fourth parameter and the first threshold corresponding to each processor wait event are compared. If valB ≥ TB, the second parameter corresponding to the front-end pause is 1, indicating that a front-end pause during the target thread's execution in the historical scheduling cycle will cause inefficient operation of the processor core. If valC ≥ TC, the second parameter corresponding to the back-end pause is 1, indicating that a back-end pause during the target thread's execution in the historical scheduling cycle will cause inefficient operation of the processor core. If valD ≥ TD, the second parameter corresponding to the branch prediction failure is 1, indicating that a branch prediction failure during the target thread's execution in the historical scheduling cycle will cause inefficient operation of the processor core.

[0079] The second approach is to determine the second parameter as the second set value if the fourth parameter is greater than or equal to the first threshold. The second set value indicates that the processor wait event that occurs during the execution of the target thread in the historical scheduling cycle will not cause the processor core to run inefficiently.

[0080] The second setting value is different from the first setting value. The second setting value can be 0, which means that the performance of the processor core is not counted in this operation, or it can be a negative number to offset the inefficient operation of the processor core in one operation.

[0081] In one example, the first setpoint is -1. Processor wait events include front-end pauses, back-end pauses, and branch prediction failures in the processor pipeline. The fourth parameter corresponding to each processor wait event is denoted as valB, valC, and valD, respectively. The first threshold corresponding to each processor wait event is denoted as TB, TC, and TD, respectively. The fourth parameter and the first threshold corresponding to each processor wait event are compared. If valB < TB, the second parameter corresponding to the front-end pause is -1, indicating that a front-end pause in the target thread during the historical scheduling cycle will not cause inefficient operation of the processor core. If valC < TC, the second parameter corresponding to the back-end pause is -1, indicating that a back-end pause in the target thread during the historical scheduling cycle will not cause inefficient operation of the processor core. If valD < TD, the second parameter corresponding to the branch prediction failure is -1, indicating that a branch prediction failure in the target thread during the historical scheduling cycle will not cause inefficient operation of the processor core.

[0082] In step S205, the second parameters obtained from all scheduling interrupts are summed to obtain the fifth parameter. For example, if the second parameter is 1 during the first scheduling interrupt, then the fifth parameter is 1; if the second parameter is 1 during the second scheduling interrupt, then the fifth parameter is 1 + 1 = 2; if the second parameter is -1 during the third scheduling interrupt, then the fifth parameter is 2 - 1 = 1. It should be noted that the minimum value of the fifth parameter is 0. If the second parameter is -1 when the fifth parameter is 0, then the fifth parameter remains 0.

[0083] In step S206, the second threshold is an empirical value, and the second threshold varies depending on the processor wait event. The target thread is scheduled by comparing the fifth parameter and the second threshold. Since the fifth parameter reflects the total number of times the processor core runs inefficiently due to processor wait events occurring during all scheduling cycles, scheduling the target thread based on the fifth parameter, and comprehensively considering the impact of processor wait events on processor core performance in all scheduling cycles, can more accurately determine the target thread's processor core performance requirements, ensuring that the target thread is scheduled to the most suitable processor core and maximizing the utilization of processor resources.

[0084] In some embodiments, step S206 in the above embodiments, which schedules the target thread based on the fifth parameter and the second threshold, includes the following steps:

[0085] S206-1, If ​​there are multiple first parameters, determine the target parameter based on multiple fifth parameters and a preset function. The preset function is used to merge multiple fifth parameters into the target parameter.

[0086] S206-2, schedule the target thread based on the target parameter and the second threshold.

[0087] The number of first parameters is the same as the number of processor wait events. If there are multiple processor wait events, then there are multiple first parameters. If there are multiple first parameters, then there are also multiple calculated fifth parameters. In this case, a preset function is obtained. The preset function is used to merge multiple fifth parameters into a target parameter. Inputting multiple fifth parameters into the preset function outputs the target parameter. In one example, processor wait events include front-end pauses, back-end pauses, and branch prediction failures. The fifth parameters corresponding to each processor wait event are denoted as CntB, CntC, and CntD, respectively. The preset function is y = fn(x1, x2, x3), and the target parameter is fn(CntB, CntC, CntD). By comparing the target parameter and the second threshold, the target thread is scheduled. Since the target parameter comprehensively considers multiple processor wait events of the target thread, it can more comprehensively represent the target thread's demand for processor core performance, thereby ensuring that the target thread is scheduled to the most suitable processor core.

[0088] In some implementations, the target thread is scheduled based on the target parameter and a second threshold, including the following two cases:

[0089] The first approach is to prevent the target thread from being scheduled to the high-performance processor core if the target parameter is greater than or equal to the second threshold for a preset duration.

[0090] The preset duration and high-performance processor cores are empirical values. If the target parameter is greater than or equal to the second threshold, it indicates that the target thread has a serious non-computational bottleneck, causing the processor core to run inefficiently. If the target thread runs on the high-performance processor core, it will waste processor resources and is not suitable for using the high-performance processor core. Therefore, the target thread is prohibited from being scheduled to the high-performance processor core within the preset duration to ensure that the computing resources of the high-performance processor core can be provided to threads without non-computational bottlenecks, thereby improving the utilization of processor resources and the response performance of the system. In addition, keeping the target thread on the low-performance processor core can also reduce the overall power consumption of the processor.

[0091] In some implementations, if the target parameter is greater than or equal to the second threshold, the target thread is marked as a garbage thread, which can prevent the target thread from being scheduled to the high-performance processor core. At the same time, a preset timer is started, and when the preset timer reaches the preset duration, the garbage thread mark of the target thread is canceled.

[0092] In one example, the target parameter is denoted as fn(CntB, CntC, CntD), and the second threshold is denoted as Th_Troublemaker. If fn(CntB, CntC, CntD) ≥ Th_Troublemaker, then the target thread is prohibited from being scheduled to the high-performance processor core for a preset duration.

[0093] In some implementations, high-performance processor cores are identified in the processor cores by identification information. When selecting a processor core for a target thread, all processor cores in the electronic device are traversed. For each processor core traversed, if the identification information determines that the processor core is a high-performance processor core, the scheduling of the target thread to that processor core is stopped, and the traversal of the next processor core continues.

[0094] The second approach is to determine the target processor core based on the preset scheduling rules if the target parameter is less than the second threshold, and then schedule the target thread to the target processor core.

[0095] If the fifth parameter is less than the second threshold, it indicates that the target thread has no non-computational bottlenecks and can be scheduled to run on a high-performance processor core to ensure that the target thread has sufficient running resources and improve its response performance. To further ensure that the target thread is scheduled to the most suitable processor core, preset scheduling rules are stored in advance. When the target parameter is less than the second threshold, the target processor core is determined based on the preset scheduling rules, and the target thread is scheduled to the target processor core. By further subdividing the high-performance processor cores through the preset scheduling rules, a high-performance processor core that better matches the performance requirements of the target thread can be selected.

[0096] In some implementations, if the number of instructions used to perform floating-point operations in the target thread is greater than or equal to a third threshold, the target processor core is determined based on a first mapping relationship, which represents the mapping relationship between the number of instructions used to perform floating-point operations and the processor core.

[0097] The third threshold is an empirical value. The number of instructions used to perform floating-point operations in the target thread is counted. If this number exceeds the third threshold, a first mapping relationship is obtained. This first mapping relationship is preset and stored in the electronic device. It represents the mapping relationship between the number of instructions used to perform floating-point operations and the processor cores. Different numbers of instructions for performing floating-point operations correspond to different processor cores. The processor cores corresponding to the number of instructions used to perform floating-point operations in the target thread are matched from the first mapping relationship and used as the target processor cores. Optionally, the first mapping relationship can also represent the mapping relationship between the range of values ​​for the number of instructions used to perform floating-point operations and the processor cores. The target range of values ​​for the number of instructions used to perform floating-point operations in the target thread is determined, and the processor cores corresponding to the target range are matched from the first mapping relationship and used as the target processor cores.

[0098] In some implementations, if the processor wait event includes branch prediction failure and the fourth parameter associated with branch prediction failure is greater than or equal to the fourth threshold, the target processor core is determined based on the second mapping relationship. The second mapping relationship characterizes the mapping relationship between the fourth parameter associated with branch prediction failure and the processor core. The fourth parameter associated with branch prediction failure is obtained by adjusting the first parameter associated with branch prediction failure based on the third parameter associated with branch prediction failure.

[0099] Let D be the first parameter associated with the branch prediction failure, d be the third parameter associated with the branch prediction failure, and valD be the fourth parameter associated with the branch prediction failure. Then valD = d × D. If valD is greater than or equal to the fourth threshold, obtain a two-way mapping relationship. The second mapping relationship is preset and stored in the electronic device. The second mapping relationship represents the mapping relationship between the fourth parameter associated with the branch prediction failure and the processor core. Different values ​​of the fourth parameter associated with the branch prediction failure correspond to different processor cores. Match the processor core corresponding to valD from the second mapping relationship and use it as the target processor core.

[0100] In some embodiments, step S206 in the above embodiments, which schedules the target thread based on the fifth parameter and the second threshold, includes the following steps:

[0101] If the number of the first parameter is one, the target thread is scheduled based on the fifth parameter and the second threshold.

[0102] If the fifth parameter is greater than or equal to the second threshold, it indicates that the target thread has a serious non-computational bottleneck and is not suitable for using a high-performance processor core. In this case, the target thread is prohibited from being scheduled to the high-performance processor core for a preset time period to ensure that the computing resources of the high-performance processor core can be provided to threads without non-computational bottlenecks, thereby improving the utilization of processor resources. If the fifth parameter is less than the second threshold, it indicates that the target thread does not have a non-computational bottleneck and can be scheduled to the high-performance processor core to ensure that the target thread has sufficient running resources. Alternatively, the target processor core can be determined based on preset scheduling rules, and the target thread can be scheduled to the target processor core.

[0103] In the exemplary embodiments of this disclosure, processor wait events are exemplified by front-end stall, back-end stall, and branch prediction missprediction in the processor pipeline, providing a thread scheduling method. Figure 3 This is a flowchart illustrating a thread scheduling method according to an exemplary embodiment, such as... Figure 3 As shown, it includes the following steps:

[0104] S1, upon entering a scheduling interrupt, read the values ​​of the Front-End stall cycle counter, Back-End stall cycle counter, and Misprediction cycle counter, and calculate the difference between this value and the corresponding counter value at the time of the last scheduling interrupt, to obtain the first parameter corresponding to each processor wait event, denoted as B, C, and D respectively;

[0105] S2, multiply the third parameters b, c, d corresponding to each processor wait event by the first parameters B, C, D corresponding to each processor wait event to obtain the fourth parameters valB, valC, valD corresponding to each processor wait event;

[0106] The fourth parameters valB, valC, and valD represent the impact factors of each processor wait event on the processor core's operating performance. These three impact factors are saved to the target thread's own data structure.

[0107] S3. Compare these three influencing factors with their respective thresholds TB, TC, and TD. Use counters CntB, CntC, and CntD to represent the comparison results of each influencing factor in all scheduling cycles. If the result is higher than the corresponding threshold, the counter increments; if it is lower, the counter decrements.

[0108] The minimum value of each counter is 0;

[0109] S4, call the preset function to quantize CntB, CntC, and CntD into a single value, fn(CntB, CntC, CntD). If this value is greater than Th_Troublemaker, mark the target thread as "Troublemaker" and prohibit scheduling to the high-performance processor core. Simultaneously, start a timer; the marking is lifted after the timer's preset duration. If the value is less than the threshold Th_Troublemaker, determine the target processor core Best_Target according to the following preset scheduling rules:

[0110] 1. If the target thread contains floating-point arithmetic instructions and the proportion of floating-point arithmetic instructions is greater than the instruction threshold, the target processor core Best_Target is determined according to the floating-point energy efficiency table, which is a mapping relationship between the number of floating-point arithmetic instructions and the number of processor cores.

[0111] 2. If the target thread’s valD is greater than the prediction failure threshold, the target processor core Best_Target is determined according to the branch prediction performance table. The branch prediction performance table is the mapping relationship between the fourth parameter corresponding to the branch prediction failure and the processor core.

[0112] 3. Add corresponding mechanisms for special cases, such as if the target thread is locked to run on a certain processor core, then use that processor core as Best_Target;

[0113] IV. In other cases, the target processor core Best_Target is determined by the system's built-in scheduling mechanism.

[0114] In some embodiments, after marking the target thread as "Troublemaker" or determining the target processor core Best_Target through the above embodiments, when scheduling the target thread, the system iterates through each processor core sequentially. When it reaches a certain processor core, it first determines whether the target thread is marked as a garbage thread. If it is determined that the target thread is marked as a garbage thread, it determines the identification information of the currently traversed processor core. If there is no identification information indicating that the currently traversed processor core is a high-performance processor core, the target thread can be scheduled to the currently traversed processor core. If the identification information indicates that the currently traversed processor core is a high-performance processor core, the target thread can be scheduled to the currently traversed processor core. If the target thread is a high-performance processor core, the process continues to traverse the next processor core until no identifier indicates that the currently traversed processor core is a high-performance processor core. If it is determined that the target thread has not been marked as a garbage thread, the process determines whether the currently traversed processor core is the target processor core Best_Target. If the currently traversed processor core is the target processor core Best_Target, the target thread is scheduled to the currently traversed processor core. If the currently traversed processor core is not the target processor core Best_Target, the process continues to traverse the next processor core until the target processor core Best_Target is reached.

[0115] In an exemplary embodiment of this disclosure, a thread scheduling device is provided. Figure 4 This is a block diagram illustrating a thread scheduling device according to an exemplary embodiment, such as... Figure 4 As shown, the thread scheduling device includes:

[0116] The acquisition module 401 is configured to acquire a first parameter, which represents the number of processor cycles in which processor wait events occurred during the execution of the target thread in the historical scheduling cycle, and the processor wait event represents a running event that causes the processor core to be in a waiting state.

[0117] The determination module 402 is configured to determine the second parameter based on the first parameter. The second parameter characterizes whether a processor wait event occurring during the execution of the target thread in a historical scheduling cycle will lead to inefficient operation of the processor core.

[0118] The scheduling module 403 is configured to schedule the target thread based on the second parameter.

[0119] In one exemplary embodiment, the determining module 402 is further configured to:

[0120] Obtain the third parameter, which represents the extent to which the processor wait event occurring during the target thread's runtime affects the performance of the processor core;

[0121] The first parameter is adjusted based on the third parameter to obtain the fourth parameter;

[0122] The second parameter is determined based on the fourth parameter and the first threshold.

[0123] In one exemplary embodiment, the determining module 402 is further configured to:

[0124] If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be the first set value. The first set value indicates that the processor core will run inefficiently when the target thread encounters a processor wait event during the historical scheduling cycle.

[0125] If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be the second set value. The second set value indicates that the processor wait event that occurs when the target thread is running in the historical scheduling cycle will not cause the processor core to run inefficiently.

[0126] In one exemplary embodiment, the scheduling module 403 is further configured to:

[0127] Determine the fifth parameter, which is the sum of the second parameters obtained from all scheduling interrupts;

[0128] The target thread is scheduled based on the fifth parameter and the second threshold.

[0129] In one exemplary embodiment, the scheduling module 403 is further configured to:

[0130] If there are multiple first parameters, the target parameter is determined based on multiple fifth parameters and a preset function. The preset function is used to merge multiple fifth parameters into the target parameter.

[0131] The target thread is scheduled based on the target parameter and the second threshold.

[0132] In one exemplary embodiment, the scheduling module 403 is further configured to:

[0133] If the target parameter is greater than or equal to the second threshold, the target thread is prohibited from being scheduled to the high-performance processor core for a preset time period.

[0134] If the target parameter is less than the second threshold, the target processor core is determined based on the preset scheduling rules, and the target thread is scheduled to the target processor core.

[0135] In one exemplary embodiment, the scheduling module 403 is further configured to:

[0136] If the number of instructions used to perform floating-point operations in the target thread is greater than or equal to the third threshold, the target processor core is determined based on the first mapping relationship. The first mapping relationship represents the mapping relationship between the number of instructions used to perform floating-point operations and the processor core.

[0137] If the processor wait event includes branch prediction failure and the fourth parameter associated with branch prediction failure is greater than or equal to the fourth threshold, the target processor core is determined based on the second mapping relationship. The second mapping relationship characterizes the mapping relationship between the fourth parameter associated with branch prediction failure and the processor core. The fourth parameter associated with branch prediction failure is obtained by adjusting the first parameter associated with branch prediction failure based on the third parameter associated with branch prediction failure.

[0138] In one exemplary embodiment, the processor wait event includes at least one of the following: front-end pause, back-end pause, and branch prediction failure in the processor pipeline.

[0139] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0140] Figure 5 This is a block diagram illustrating an electronic device 500 according to an exemplary embodiment.

[0141] Reference Figure 5 The electronic device 500 may include one or more of the following components: processing component 502, memory 504, power supply component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514, and communication component 516.

[0142] Processing component 502 typically controls the overall operation of electronic device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 502 may include one or more processors 520 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 502 may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502.

[0143] Memory 504 is configured to store various types of data to support the operation of electronic device 500. Examples of such data include instructions for any application or method operating on electronic device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0144] Power supply component 506 provides power to various components of electronic device 500. Power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 500.

[0145] Multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When the electronic device 500 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0146] Audio component 510 is configured to output and / or input audio signals. For example, audio component 510 includes a microphone (MIC) configured to receive external audio signals when electronic device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 504 or transmitted via communication component 516. In some embodiments, audio component 510 also includes a speaker for outputting audio signals.

[0147] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0148] Sensor assembly 514 includes one or more sensors for providing state assessments of various aspects of electronic device 500. For example, sensor assembly 514 may detect the on / off state of electronic device 500, the relative positioning of components such as the display and keypad of electronic device 500, changes in position of electronic device 500 or a component of electronic device 500, the presence or absence of user contact with electronic device 500, orientation or acceleration / deceleration of electronic device 500, and temperature changes of electronic device 500. Sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0149] Communication component 516 is configured to facilitate wired or wireless communication between electronic device 500 and other devices. Electronic device 500 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0150] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0151] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, which can be executed by a processor 520 of an electronic device 500 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0152] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform a thread scheduling method, including any of the methods described above.

[0153] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0154] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A thread scheduling method, characterized in that, The method includes: Obtain the first parameter, which represents the number of processor cycles in which processor wait events occur during the execution of the target thread in the historical scheduling cycle, and the processor wait event represents a running event that causes the processor core to be in a waiting state; Based on the first parameter, a second parameter is determined, wherein the second parameter characterizes whether the processor wait event occurring during the execution of the target thread in the historical scheduling cycle will cause the processor core to run inefficiently; The target thread is scheduled based on the second parameter.

2. The method according to claim 1, characterized in that, Determining the second parameter based on the first parameter includes: Obtain a third parameter, which characterizes the degree of impact of the processor wait event occurring during the runtime of the target thread on the performance of the processor core; The first parameter is adjusted based on the third parameter to obtain the fourth parameter; The second parameter is determined based on the fourth parameter and the first threshold.

3. The method according to claim 2, characterized in that, Determining the second parameter based on the fourth parameter and the first threshold includes: If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be a first set value. The first set value indicates that the processor core will run inefficiently when the processor wait event occurs during the historical scheduling cycle of the target thread. If the fourth parameter is greater than or equal to the first threshold, the second parameter is determined to be a second set value. The second set value indicates that the occurrence of the processor wait event during the operation of the target thread in the historical scheduling cycle will not cause the processor core to run inefficiently.

4. The method according to claim 1, characterized in that, The step of scheduling the target thread based on the second parameter includes: Determine the fifth parameter, which is the sum of the second parameters obtained from all scheduling interrupts; The target thread is scheduled based on the fifth parameter and the second threshold.

5. The method according to claim 4, characterized in that, The scheduling of the target thread based on the fifth parameter and the second threshold includes: If there are multiple first parameters, a target parameter is determined based on multiple fifth parameters and a preset function, wherein the preset function is used to merge multiple fifth parameters into the target parameter; The target thread is scheduled based on the target parameter and the second threshold.

6. The method according to claim 5, characterized in that, The step of scheduling the target thread based on the target parameter and the second threshold includes: If the target parameter is greater than or equal to the second threshold, the target thread is prohibited from being scheduled to the high-performance processor core for a preset time period. If the target parameter is less than the second threshold, the target processor core is determined based on the preset scheduling rules, and the target thread is scheduled to the target processor core.

7. The method according to claim 6, characterized in that, The step of determining the target processor core based on preset scheduling rules includes: If the number of instructions used to perform floating-point operations in the target thread is greater than or equal to the third threshold, the target processor core is determined based on the first mapping relationship, wherein the first mapping relationship represents the mapping relationship between the number of instructions used to perform floating-point operations and the processor core. If the processor wait event includes branch prediction failure and the fourth parameter associated with the branch prediction failure is greater than or equal to the fourth threshold, the target processor core is determined based on the second mapping relationship. The second mapping relationship represents the mapping relationship between the fourth parameter associated with the branch prediction failure and the processor core. The fourth parameter associated with the branch prediction failure is obtained by adjusting the first parameter associated with the branch prediction failure based on the third parameter associated with the branch prediction failure.

8. The method according to claim 1, characterized in that, The processor wait events include at least one of the following: front-end pause, back-end pause, and branch prediction failure in the processor pipeline.

9. A thread scheduling device, characterized in that, The device includes: The acquisition module is configured to acquire a first parameter, which represents the number of processor cycles in which processor wait events occur during the execution of the target thread in a historical scheduling cycle, and the processor wait event represents a running event that causes the processor core to be in a waiting state. The determination module is configured to determine a second parameter based on the first parameter, wherein the second parameter characterizes whether the occurrence of the processor wait event during the execution of the target thread in the historical scheduling cycle will cause the processor core to run inefficiently; The scheduling module is configured to schedule the target thread based on the second parameter.

10. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to perform the method as described in any one of claims 1-8.

11. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method as described in any one of claims 1-8.

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