Chip verification method and device, electronic equipment and storage medium

Abstract

This application discloses a chip verification method, apparatus, electronic device, and storage medium, relating to the field of chip design technology. The method includes: determining the target hardware corresponding to the chip verification task from a hardware resource pool; obtaining chip verification information based on the target hardware and test cases corresponding to the chip verification task; generating encrypted information corresponding to the chip verification information, and generating a compliance report corresponding to the chip verification task based on the encrypted information, the chip verification information, and preset audit rules; and generating user permissions, allowing users to access data within their authorized scope. This method addresses the problems of low resource scheduling efficiency, lack of auditing during the chip verification process, and insufficient data security isolation. The method employs a flexible resource scheduling approach to improve resource scheduling efficiency; generates a compliance report based on preset audit rules to meet the automated compliance requirements of functional safety standards; and generates encrypted information and user permissions to achieve data security isolation.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to chip verification methods, apparatus, electronic devices, and storage media. Background Technology

[0002] Chip design complexity is increasing exponentially, and traditional chip verification methods face challenges such as low resource utilization, long verification cycles, and insufficient security.

[0003] In addition, cloud-native technologies are currently widely used for chip verification. While cloud-native technologies provide elastic computing power and agile development capabilities for chip verification, their distributed architecture also introduces problems such as low resource scheduling efficiency, lack of verification process auditing, and insufficient data security isolation. Summary of the Invention

[0004] This invention provides a chip verification method, apparatus, electronic device, and storage medium to solve the problems of low resource scheduling efficiency, lack of verification process auditing, and insufficient data security isolation in the chip verification process.

[0005] In a first aspect, this application provides a chip verification method, the method comprising: Obtain the chip verification task and determine the target hardware corresponding to the chip verification task from the hardware resource pool; The chip verification task is assigned to the target hardware, and the chip verification information is obtained based on the test cases corresponding to the target hardware and the chip verification task. Generate encrypted information corresponding to chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information, and preset audit rules; Generate user permissions for multiple users, whereby user permissions are used to access preset data, chip verification information, encrypted information, and compliance reports corresponding to chip verification tasks.

[0006] Secondly, this application provides a chip verification apparatus, which includes: The hardware determination module is used to acquire chip verification tasks and determine the target hardware corresponding to the chip verification tasks from the hardware resource pool. The testing module is used to assign chip verification tasks to target hardware and obtain chip verification information based on the test cases corresponding to the target hardware and chip verification tasks. The report generation module is used to generate encrypted information corresponding to chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information and preset audit rules. The permission generation module is used to generate user permissions for multiple users. These user permissions are used to access preset data, chip verification information, encrypted information, and compliance reports corresponding to the chip verification task.

[0007] Thirdly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the chip verification method of the first aspect or any corresponding embodiment described above.

[0008] Fourthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the chip verification method of the first aspect or any corresponding embodiment described above.

[0009] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the chip verification method of the first aspect or any corresponding embodiment described above.

[0010] This application identifies the target hardware corresponding to a chip verification task within a hardware resource pool; obtains chip verification information based on the target hardware and test cases corresponding to the chip verification task; generates encrypted information corresponding to the chip verification information; and generates a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information, and preset audit rules; and generates user permissions, allowing users to access preset data, chip verification information, encrypted information, and the compliance report within their authorized scope. This addresses the problems of low resource scheduling efficiency, lack of auditing during the chip verification process, and insufficient data security isolation. The method employs a flexible resource scheduling approach, allocating chip verification tasks to the target hardware, thus improving resource scheduling efficiency and shortening the verification cycle. It generates a compliance report corresponding to the chip verification task based on encrypted information, chip verification information, and preset audit rules, meeting the automated compliance requirements of functional safety standards. Furthermore, it generates encrypted information corresponding to the chip verification information and achieves data security isolation through user permissions, improving data security during the verification process. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a chip verification method according to an embodiment of this application; Figure 2 This is a schematic diagram of the dynamic resource scheduling process according to an embodiment of this application; Figure 3 This is a schematic diagram of the verification process according to an embodiment of this application; Figure 4 This is a schematic diagram of the blockchain evidence storage compliance process according to an embodiment of this application; Figure 5 This is a structural block diagram of a chip verification apparatus according to an embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] With the exponential increase in chip design complexity, traditional verification methods face challenges such as low resource utilization, long verification cycles, and insufficient security. The core characteristics of cloud-native technologies (containerization, microservices, and dynamic resource scheduling) provide chip verification with elastic computing power and agile development capabilities, but their distributed architecture also introduces problems such as low resource scheduling efficiency, unauditable verification process, insufficient security isolation, and poor cross-platform verification consistency.

[0017] The reasons for low resource scheduling efficiency are as follows: Traditional verification environments use static resource allocation, which cannot dynamically match the sudden computing power demands of chip verification tasks, such as parallel simulation of AI (Artificial Intelligence) chips, leading to resource idleness or queuing delays. The reason for the lack of auditability in the verification process is that cloud verification involves multi-party collaboration, such as IP (Intellectual Property) suppliers and design teams, but key nodes (coverage achievement, vulnerability remediation) lack trusted records, making it difficult to meet functional safety standards. The reason for insufficient security isolation is that in containerized verification environments, incomplete network isolation between microservices may lead to the leakage of sensitive data (such as AI chip model parameters), and hardware Trojan detection capabilities are limited. The reason for poor cross-platform verification consistency is that the scheduling strategy for heterogeneous resources lacks a unified optimization model, making it difficult to align verification results across vendor toolchains. Heterogeneous resources include CPUs (Central Processing Units), GPUs (Graphics Processing Units), and FPGAs (Field-Programmable Gate Arrays).

[0018] In addition, the immutability of blockchain technology provides a new approach to the storage and traceability of verification data, but deep integration with cloud-native verification platforms still requires technological breakthroughs.

[0019] This application provides a chip verification method. Elastic resource scheduling shortens the verification cycle (compared to static resource allocation) and reduces resource costs. Blockchain-based evidence storage supports full lifecycle traceability, meeting the automated compliance requirements of functional safety standards and ensuring audit compliance. Through microservice network isolation strategies and hardware Trojan signature database matching, the accuracy of side-channel attack detection is improved, enhancing the security of the chip verification process. A unified scheduling model reduces the error rate of verification results across vendor toolchains, improving cross-platform data consistency.

[0020] According to an embodiment of this application, a chip verification method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be run in the chip verification system described above, or in a computer system such as a set of executable instructions, for example, a computer, a server, etc. Although a logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order than that shown here.

[0021] This embodiment provides a chip verification method. Figure 1 This is a flowchart of a chip verification method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the chip verification task and determine the target hardware corresponding to the chip verification task in the hardware resource pool.

[0022] Specifically, the hardware resource pool includes hardware such as CPUs, GPUs, and FPGAs. In this embodiment, the computing resources of the hardware in the resource pool are encapsulated as independent microservices, and the SpreadConstraints strategy is used to distribute tasks in a distributed manner. The SpreadConstraints strategy is used to evenly distribute chip verification tasks across the CPU / GPU / FPGA hardware nodes, avoiding load imbalance and resource contention caused by concentrated task clustering, while reducing resource fragmentation and improving cluster resource utilization and scheduling stability.

[0023] Based on the task type of the chip verification task, hardware that is good at handling the corresponding task type is selected from the hardware resource pool as the target hardware. For example, if the chip verification task is a formal verification task, it is assigned to the FPGA cluster, and the FPGA cluster is the target hardware, taking advantage of the hardware acceleration of the FPGA cluster; if the chip verification task is a dynamic simulation task, it is assigned to the GPU cluster, and the GPU cluster is the target hardware, taking advantage of the parallel computing capabilities of the GPU cluster.

[0024] Additionally, if the chip verification task is a small-scale task, the LeastRequestedPriority strategy can be used to merge and schedule small-scale verification tasks to the target hardware on the same compute node, thereby consolidating resource fragmentation and reducing resource waste. The LeastRequestedPriority strategy prioritizes scheduling tasks to the hardware node with the most idle resources, centrally merging and deploying small-scale chip verification tasks, reducing node resource fragmentation and idle waste, and maximizing the resource utilization of the hardware cluster.

[0025] Step S102: Assign the chip verification task to the target hardware, and obtain the chip verification information based on the test cases corresponding to the target hardware and the chip verification task.

[0026] Specifically, chip verification tasks are assigned to target hardware, which then utilizes its computing power to process these tasks and obtain chip verification information. The target hardware requires test cases to process the chip verification tasks.

[0027] This embodiment generates intelligent test stimuli based on the Accellera PSS standard, adapting to the UVM (Universal Verification Methodology) transaction-level model and hardware simulation platform to dynamically generate test cases. For example, for the link layer protocol of a communication chip, it automatically generates boundary value test cases. Accellera PSS is a portable test stimulus standard.

[0028] Step S103: Generate encrypted information corresponding to the chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, the chip verification information, and preset audit rules.

[0029] Specifically, encrypted information corresponding to chip verification information is generated. For example, the hash value of coverage reports and vulnerability remediation records is generated using SHA-256 as encrypted information. Zero-knowledge proofs (zk-SNARKs) are used to protect the privacy of RTL (Register Transfer Level) code. For example, IP vendors can only access data in their associated chain segments, preventing design leaks.

[0030] In addition, preset audit rules can be set, such as: defining coverage criteria for deployed smart contracts (e.g., functional coverage ≥ 95%). If the criteria are not met, the task queue will be automatically frozen and an alarm will be triggered.

[0031] Based on encrypted information, chip verification information, and preset audit rules, a compliance report corresponding to the chip verification task is generated. For example, in an autonomous driving chip project, the timestamps of vulnerability remediation records are fixed through the National Time Service Center API, meeting ISO 26262 compliance requirements.

[0032] Step S104: Generate user permissions for multiple users, wherein the user permissions are used to access the preset data, chip verification information, encrypted information and compliance report corresponding to the chip verification task.

[0033] Specifically, this embodiment designs a hierarchical permission management mechanism. For example, using the RBAC model, it sets data access permissions, i.e., user permissions, for different users in the IP vendor, design team, and verification team. For example, the IP vendor can only access the chain segment data related to it, and the verification team has full-process audit permissions.

[0034] Users can access preset data, chip verification information, encrypted information, and compliance reports corresponding to chip verification tasks based on their user permissions. Preset data includes, for example, AI chip model parameters and RTL code. Additionally, Merkle tree structures can be used to quickly locate tampering activities.

[0035] The chip verification method provided in this embodiment determines the target hardware corresponding to the chip verification task from the hardware resource pool; obtains chip verification information based on the target hardware and the test cases corresponding to the chip verification task; generates encrypted information corresponding to the chip verification information, and generates a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information, and preset audit rules; and generates user permissions, allowing users to access preset data, chip verification information, encrypted information, and the compliance report within their authorized scope. This method employs a flexible resource scheduling approach, allocating chip verification tasks to the target hardware, improving resource scheduling efficiency and shortening the verification cycle; it generates a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information, and preset audit rules, meeting the automated compliance requirements of functional safety standards; and it generates encrypted information corresponding to the chip verification information and achieves data security isolation through user permissions, improving data security during the verification process. This method solves the problems of low resource scheduling efficiency, lack of auditing during the verification process, and insufficient data security isolation in the chip verification process.

[0036] As an optional embodiment, assigning chip verification tasks to target hardware includes: Obtain the task type and resource consumption ratio of the chip verification task; Determine the task priority of chip verification tasks based on task type and resource consumption ratio; Determine the time slice of the target hardware occupied by the chip verification task; Chip verification tasks are assigned to target hardware based on task priority and time slice.

[0037] Specifically, this embodiment is used for intelligent scheduling and task distribution. First, the task type and resource usage ratio of the chip verification task are obtained. For example, the task type includes timing verification, functional coverage testing, etc., and the resource usage ratio includes CPU usage, memory usage, etc.

[0038] The task priority of chip verification tasks is determined based on task type and resource consumption ratio. For example, the task priority is calculated using a priority list algorithm based on task type and resource consumption ratio. High-priority tasks are assigned to low-latency nodes, and a preemptive scheduling strategy is set.

[0039] The time slice occupied by the chip verification task on the target hardware is determined. For example, by optimizing the Kubernetes scheduling strategy based on deep reinforcement learning algorithms and combining it with a dynamic time slice calculation module, the task polling time slice size is adjusted in real time to generate the time slice occupied by the chip verification task on the target hardware. Dynamic time slice allocation for chip verification tasks ensures that task migration time is controlled to <30 seconds, and resource utilization is improved to 85%. Kubernetes is a container orchestration engine. The Kubernetes scheduling strategy is a set of rules used to allocate chip verification tasks to suitable computing nodes, including node filtering, priority scoring, load balancing, task migration and merging logic, to achieve reasonable task allocation, hardware load balancing, and improved resource utilization.

[0040] Based on task priority and time slice, chip verification tasks are allocated to target hardware. Combining task priority ranking and dynamically calculated time slice parameters, and following the rule of prioritizing high-priority tasks and adaptively matching time slices, chip verification tasks are scheduled to suitable target hardware nodes, achieving orderly task execution and efficient utilization of hardware resources.

[0041] In this embodiment, intelligent scheduling and distribution of chip verification tasks are realized. Priority is accurately determined according to task type and resource ratio, hardware time slices are dynamically adjusted, task migration time is reduced, resource utilization is improved, resource idleness is effectively avoided, high-priority task blocking is prevented, and overall scheduling efficiency is improved.

[0042] As an optional embodiment, determining the target hardware corresponding to the chip verification task from the hardware resource pool includes: Determine the node identifier and node resources of the computing nodes; Determine the primary resource requirements for the chip verification task; Computing nodes that are marked with a preset label and whose resources meet the first resource requirement are selected as candidate computing nodes. Based on the node resources of the candidate computing nodes, determine the utilization difference among multiple hardware components in the candidate computing nodes; Candidate computing nodes whose utilization difference is less than the first preset threshold are used as intermediate computing nodes; Determine the mapping relationship between chip verification tasks and hardware, and based on the mapping relationship, determine the target computing node in the intermediate computing nodes, wherein the target computing node contains the target hardware.

[0043] Specifically, the node tags and node resources of the computing nodes are determined. Node tags include, for example, marking faulty nodes or FPGA clusters under maintenance using taints. Node tags include those other than faulty node tags and maintenance tags, as well as preset tags. Node resources include, for example, remaining node resources such as CPU idle time, remaining memory size, and remaining storage capacity. The primary resource requirements for the chip verification task are determined, such as the required computing power, required memory capacity, and required storage capacity. Preset tags are those other than faulty node tags and maintenance tags. If a node is marked with a preset tag, it indicates that the computing node is available.

[0044] This embodiment employs a node filtering mechanism. Within the Kubernetes scheduling framework, filtering strategies (Predicates) are used to rigorously screen candidate nodes based on hard conditions. For example, the PodFitsResources strategy verifies whether the remaining resources (CPU, memory, storage) of a node meet the dynamic requirements of chip simulation tasks, ensuring that high-priority tasks (such as timing verification) are not blocked due to insufficient resources. The PodToleratesNodeTaints strategy marks faulty nodes or FPGA clusters under maintenance with taints, filtering out these unusable compute nodes. Only compute nodes with pre-marked taints are used, combined with tolerances, to allow critical tasks (such as parallel simulation of AI chips) to continue running under specific conditions. Compute nodes marked with pre-marked taints and whose resources meet the first resource requirement are selected as candidate compute nodes.

[0045] Based on the node resources of candidate computing nodes, the utilization difference among multiple hardware components within the candidate computing nodes is determined. Candidate computing nodes with utilization differences less than a first preset threshold are designated as intermediate computing nodes. The first preset threshold is, for example, 1%, 2%, or other values. Candidate computing nodes with utilization differences less than the first preset threshold have relatively balanced hardware utilization. For example, nodes that pass the filtering process are dynamically scored based on a priority strategy. The BalancedResourceAllocation strategy prioritizes nodes with balanced CPU and memory utilization to avoid resource imbalance (such as a node with full CPU load but idle memory), thereby improving the overall throughput of the FPGA cluster.

[0046] Determine the mapping relationship between chip verification tasks and hardware. For example, formal verification tasks within chip verification are mapped to FPGA clusters, and dynamic simulation tasks are mapped to GPU clusters. Employ the NodeAffinityPriority strategy, which, based on the characteristics of the chip verification task (e.g., the need for low-latency nodes), uses tag matching (nodeSelector) to directionally allocate tasks to nodes configured with dedicated hardware (e.g., FPGA clusters with high-speed interconnects). The NodeAffinityPriority strategy is used to directionally allocate chip verification tasks to suitable dedicated hardware nodes through node tag matching, achieving precise mapping between tasks and hardware, and ensuring both verification performance and low latency requirements.

[0047] Based on the above mapping relationship, the target computing node is determined in the intermediate computing nodes, and the target hardware is determined in the hardware within the target computing node. The above process is as follows: Figure 2 As shown, dynamic load prediction is performed; a node filtering mechanism called Predicates is initiated, including PodFitsResources for CPU / memory / storage checks and PodToleratesNodeTints for faulty node isolation, resulting in a candidate node set; a smart scoring mechanism called Priorities is initiated, including BalancedResourceAllocation for balancing utilization and NodeAffinityPriority for tag matching with dedicated hardware to select target nodes. Task scheduling is performed: property verification → FPGA cluster, dynamic simulation → GPU cluster; resource fragmentation merging is carried out using the LeastRequestedPriority strategy to improve resource utilization.

[0048] In this embodiment, precise hardware matching for chip verification tasks is achieved, unavailable computing nodes are filtered out, ensuring that node resources meet task requirements, nodes with balanced hardware utilization are selected to avoid resource skew, and targeted allocation is combined with task-hardware mapping to ensure that high-priority tasks are not blocked, effectively improving the overall throughput and scheduling rationality of the hardware cluster.

[0049] As an optional embodiment, after determining the target hardware corresponding to the chip verification task in the hardware resource pool, the method further includes: Obtain the node load of the target computing node; If the node load exceeds the second preset threshold, create a snapshot of the target computing node; Identify replacement computing nodes among computing nodes other than the target computing node; Based on the snapshot, the chip verification task will be migrated to a replacement compute node; Determine the second resource requirement for the chip verification task; Chip verification tasks with second resource requirements less than the third preset threshold are merged to obtain merged tasks, and the merged tasks are scheduled to computing nodes.

[0050] Specifically, obtain the node load of the target computing node, such as CPU utilization, percentage of used memory capacity, percentage of used storage capacity, etc.

[0051] This embodiment deploys a task status monitor that triggers migration when node load exceeds a threshold (e.g., CPU utilization > 90%). Lossless migration is achieved using container snapshot technology (such as Pod affinity strategies), and resource fragmentation is reduced through the SpreadConstraints strategy.

[0052] The second preset threshold is, for example, 90% or 95%. When the node load exceeds the second preset threshold, a snapshot of the target compute node is created. Replacement compute nodes are then selected from among the compute nodes other than the target compute node. For example, compute nodes with remaining capacity that meet the resource requirements of the tasks to be processed in the target compute node are selected as replacement compute nodes.

[0053] Based on the snapshot, the chip verification task can be migrated to a replacement compute node, for example, by using container snapshot technology (such as Pod affinity strategy) to achieve lossless migration.

[0054] This embodiment reduces resource fragmentation through the LeastRequestedPriority strategy. By employing this strategy, small-scale verification tasks are merged and scheduled to the same node, reducing resource waste. First, the second resource requirements of the chip verification task are determined, such as the required computing power, memory capacity, and storage capacity. Chip verification tasks with second resource requirements less than a third preset threshold are merged to obtain merged tasks, which are then scheduled to the computing node, thus achieving resource fragmentation merging. The third preset threshold may include, for example, a computing power threshold of 64 TFLOPS, a memory capacity threshold of 1 GB, and a storage capacity threshold of 8 GB, among other sub-thresholds. Chip verification tasks with second resource requirements less than the third preset threshold represent small-scale verification tasks; merging them before processing reduces resource waste.

[0055] In this embodiment, fault tolerance and resource optimization for chip verification tasks are achieved, node load is monitored in real time, and task migration is completed without loss when the threshold is exceeded through snapshots to avoid node overload; small-scale tasks are merged to reduce resource fragmentation, improve hardware resource utilization, ensure continuous and stable operation of verification tasks, and optimize cluster scheduling efficiency.

[0056] As an optional embodiment, before determining the target hardware corresponding to the chip verification task in the hardware resource pool, the method further includes: Acquire historical task data and create a resource demand prediction model based on the historical task data; Based on the resource demand forecasting model and chip verification tasks, the predicted value of resource demand is determined; Adjust the hardware based on the predicted resource demand to obtain the adjusted hardware. Create a hardware resource pool based on the adjusted hardware.

[0057] Specifically, historical task data is acquired, for example, by collecting historical task data from the chip verification platform through resource monitoring probes, including parameters such as simulation cycle, FPGA resource utilization, and coverage fluctuations, to construct a standardized time-series database. The data is then denoised and normalized to eliminate dimensional differences between different task types (such as UVM simulation and formal verification).

[0058] A resource demand prediction model is created based on historical task data. Based on the resource demand prediction model and the chip verification task, the predicted value of resource demand is determined. For example, a Long Short-Term Memory (LSTM) network is used to analyze the temporal characteristics of historical data as a resource demand prediction model to predict the resource demand in the next 6-24 hours, i.e., the predicted value of resource demand.

[0059] The hardware is adjusted based on predicted resource requirements, resulting in the adjusted hardware. This includes: if the current hardware resources can meet the predicted resource requirements, no adjustment is needed; if the current hardware resources cannot meet the predicted resource requirements, the hardware scale needs to be expanded, increasing hardware resources to obtain the adjusted hardware, for example, increasing the number of GPU nodes from 20 to 30. For AI chip verification tasks, the FPGA cluster size is dynamically adjusted based on peak computing power requirements (e.g., 120 TFLOPS). Model training needs to incorporate transfer learning techniques, reusing pre-trained parameters to shorten the training cycle by 30%.

[0060] Based on the adjusted hardware, a hardware resource pool is created, and this pool is managed using a microservice-based approach. For example, CPU / GPU / FPGA resources are encapsulated as independent microservices, and tasks are distributed through a SpreadConstraints strategy. For instance, formal verification tasks are assigned to the FPGA cluster (due to hardware acceleration advantages), while dynamic simulation tasks are assigned to the GPU cluster (due to parallel computing capabilities). The above content is as follows... Figure 3As shown, the initial resources include 50 FPGA nodes and 20 GPU nodes; burst load detection is performed; dynamic expansion: the number of GPU nodes is increased to 30; task migration, the BalanceResourceAllocation strategy takes effect, improving resource utilization and shortening the verification cycle; physical layer protocol test data is hashed and uploaded to the blockchain; timestamp is fixed: year A, month B, day C, hour D.

[0061] In this embodiment, an LSTM resource demand prediction model is built based on historical data to accurately predict computing power demand and dynamically adjust the hardware scale. Transfer learning shortens the model training cycle. A hardware resource pool is built using microservices and tasks are allocated on demand to create elastic computing power support and improve resource adaptability and hardware cluster utilization efficiency.

[0062] As an optional embodiment, encrypted information corresponding to the chip verification information is generated, and a compliance report corresponding to the chip verification task is generated based on the encrypted information, the chip verification information, and preset audit rules, including: Generate encrypted information corresponding to chip verification information, and store the preset data, chip verification information, and encrypted information corresponding to the chip verification task in a distributed file system; Obtain the timestamps of preset operations during the chip verification task and store the timestamps in a distributed file system; A data chain is created based on the data in the distributed file system, and the data chain is synchronized to the blockchain so that users can access the on-chain data of the data chain through the blockchain. Extract preset fields from on-chain data, generate a compliance report based on preset audit rules and preset fields, and synchronize the compliance report to the blockchain.

[0063] Specifically, key data during chip verification is hashed, with preset data including coverage reports and vulnerability remediation records. Encrypted information corresponding to the chip verification information is generated, and the preset data, chip verification information, and encrypted information for the chip verification task are stored in a distributed file system. For example, coverage reports and vulnerability remediation records are generated using SHA-256 to create unique hash values, and the original data is encrypted and stored in the IPFS distributed file system. Zero-knowledge proofs (zk-SNARKs) are used to protect the privacy of RTL code.

[0064] The system acquires the timestamps of preset operations during chip verification tasks and stores them in a distributed file system. For example, it connects to the National Time Service Center API to generate authoritative timestamps and records evidence information via a Hyperledger Fabric private chain, storing both timestamps and evidence information in the distributed file system. It deploys smart contracts to define automated auditing rules, such as freezing the task queue when functional coverage is <95% and achieving a vulnerability remediation record tampering detection accuracy of ≥99.99%. It also combines zero-knowledge proofs (zk-SNARKs) to protect RTL code privacy. For example, IP vendors can only access data from their associated blockchain segments, preventing design leaks.

[0065] Based on data in the distributed file system, a data chain is created and synchronized to the blockchain, enabling users to access on-chain data through the blockchain. For example, by connecting Hyperledger Fabric and Ethereum through the Polkadot relay chain, it supports cross-chain data synchronization among multiple teams (such as designers, verifiers, and chipmakers), ensuring full traceability throughout the process.

[0066] Preset audit rules include, for example, defining coverage criteria for smart contract deployments (e.g., functional coverage ≥ 95%). If the criteria are not met, the task queue is automatically frozen and an alarm is triggered. For instance, in an autonomous driving chip project, the timestamps of vulnerability remediation records are fixed through the National Time Service Center API to meet compliance requirements. Preset fields include compliance fields such as coverage achievement time and fault injection test results.

[0067] The above content is as follows Figure 4 As shown, the process involves: acquiring key data; generating hash values ​​for the key data; using zero-knowledge proofs to protect the security of RTL code; cross-chain interoperability; multi-team data synchronization; and implementing smart contract audit rules to determine if the coverage rate is greater than 95%. If it is greater than 95%, the process passes and generates a compliance report, and data tampering is detected. If it is less than or equal to 95%, the task queue is frozen and an alarm is issued, and data tampering is detected.

[0068] Preset fields are extracted from on-chain data, and a compliance report is generated based on preset audit rules and these fields. This compliance report is then synchronized to the blockchain. For example, compliance fields such as coverage achievement time and fault injection test results are extracted from on-chain data to generate a standardized verification report template, i.e., a compliance report. This compliance report is then synchronized to the blockchain, achieving mutual recognition across multiple jurisdictions through cross-chain protocols. The above process is as follows: Figure 4 As shown.

[0069] In this embodiment, chip verification data is encrypted and stored with an authoritative timestamp, enabling full-process traceability; zero-knowledge proofs protect core privacy, smart contracts are automatically audited, compliance reports are automatically generated and uploaded to the blockchain, and cross-chain synchronization and mutual recognition across multiple jurisdictions are supported to meet compliance requirements.

[0070] As an optional embodiment, chip verification information is obtained based on the test cases corresponding to the target hardware and the chip verification task, including: Obtain the test cases corresponding to the chip verification task; Obtain the chip performance metrics corresponding to the chip verification task, and adjust the test cases according to the chip performance metrics to obtain the adjusted test cases; Based on the adjusted test cases, process the chip verification task.

[0071] Specifically, it obtains test cases corresponding to chip verification tasks, such as dynamically generating test cases, generating intelligent test stimuli based on the Accellepa PSS standard, adapting to the UVM transaction-level model and hardware simulation platform, such as automatically generating boundary value test cases for link layer protocols of communication chips.

[0072] Chip performance metrics include: functional coverage, code coverage, assertion coverage, etc.

[0073] Obtain the chip performance metrics corresponding to the chip verification task, and adjust the test cases based on these metrics to obtain the adjusted test cases. For example, monitor functional coverage, code coverage, and assertion coverage metrics in real time, and dynamically adjust the testing strategy through a feedback collection queue, such as triggering the generation of supplementary test cases for uncovered code paths. Process the chip verification task based on the adjusted test cases.

[0074] In addition, this embodiment will also evaluate and optimize the chip verification process, first by performing quantitative analysis of performance indicators, and then by dynamically updating the rule base. Quantitative analysis of performance indicators includes metrics such as computing resource utilization (e.g., increasing FPGA cluster utilization from 40% to 85%) and shortening the verification cycle (e.g., reducing it from 14 days to 8 days), using an evaluation model to verify the scheduling effect. Dynamic updates to the rule base include optimizing scheduling rule parameters based on historical data (e.g., task migration overhead, throughput deviation), such as adjusting the weight allocation of the load balancing algorithm (priority list strategy).

[0075] In this embodiment, adapted chip verification test cases are dynamically generated, and test cases are adjusted in real time based on performance indicators such as functional coverage, and uncovered test paths are supplemented. Verification performance can be quantitatively analyzed, scheduling rule base can be dynamically updated, scheduling strategy can be optimized, resource utilization can be effectively improved, and chip verification cycle can be significantly shortened.

[0076] This embodiment also provides a chip verification device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0077] This embodiment provides a chip verification device, such as... Figure 5 As shown, it includes: The hardware determination module 501 is used to acquire the chip verification task and determine the target hardware corresponding to the chip verification task in the hardware resource pool. Test module 502 is used to assign chip verification tasks to target hardware and obtain chip verification information based on the test cases corresponding to the target hardware and chip verification tasks. The report generation module 503 is used to generate encrypted information corresponding to chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, chip verification information and preset audit rules. The permission generation module 504 is used to generate user permissions for multiple users. These user permissions are used to access preset data, chip verification information, encrypted information, and compliance reports corresponding to the chip verification task.

[0078] In some alternative implementations, test module 502 includes: The first acquisition unit is used to acquire the task type and resource usage ratio of the chip verification task; The first determining unit is used to determine the task priority of the chip verification task based on the task type and resource consumption ratio. The second determining unit is used to determine the time slice of the target hardware occupied by the chip verification task. The allocation unit is used to allocate chip verification tasks to the target hardware based on task priority and time slice.

[0079] In some alternative implementations, the hardware determination module 501 includes: The third determining unit is used to determine the node label and node resources of the computing node; The fourth determining unit is used to determine the first resource requirements for the chip verification task; The first setting unit is used to mark computing nodes that are marked with a preset label and whose node resources meet the first resource requirements as candidate computing nodes. The fifth determining unit is used to determine the utilization difference between multiple hardware components in the candidate computing nodes based on the node resources of the candidate computing nodes. The second setting unit is used to select candidate computing nodes whose utilization difference is less than the first preset threshold as intermediate computing nodes. The sixth determining unit is used to determine the mapping relationship between the chip verification task and the hardware, and to determine the target computing node in the intermediate computing nodes according to the mapping relationship, wherein the target computing node contains the target hardware.

[0080] In some alternative embodiments, the device further includes: The first acquisition module is used to acquire the node load of the target computing node; The first creation module is used to create a snapshot of the target computing node when the node load is greater than the second preset threshold. The first determining module is used to determine a replacement computing node among computing nodes other than the target computing node; The migration module is used to migrate chip verification tasks to replacement compute nodes based on snapshots; The second determination module is used to determine the second resource requirements of the chip verification task. The merging module is used to merge chip verification tasks whose second resource requirements are less than a third preset threshold to obtain merged tasks, and then schedule the merged tasks to computing nodes.

[0081] In some alternative embodiments, the device further includes: The second acquisition module is used to acquire historical task data and create a resource demand prediction model based on the historical task data. The third determination module is used to determine the predicted value of resource demand based on the resource demand prediction model and the chip verification task; The adjustment module is used to adjust the hardware based on the predicted resource demand values ​​to obtain the adjusted hardware. The second creation module is used to create a hardware resource pool based on the adjusted hardware.

[0082] In some alternative implementations, the report generation module 503 includes: The first generation unit is used to generate encrypted information corresponding to chip verification information, and store the preset data, chip verification information and encrypted information corresponding to the chip verification task in a distributed file system. The second acquisition unit is used to acquire the timestamps of preset operations during the chip verification task and store the timestamps in a distributed file system. The creation unit is used to create a data chain based on the data in the distributed file system and synchronize the data chain to the blockchain so that users can access the on-chain data of the data chain through the blockchain. The second generation unit is used to extract preset fields from on-chain data, generate a compliance report based on preset audit rules and preset fields, and synchronize the compliance report to the blockchain.

[0083] In some alternative implementations, test module 502 includes: The third acquisition unit is used to acquire the test cases corresponding to the chip verification task; The fourth acquisition unit is used to acquire the chip performance indicators corresponding to the chip verification task, and adjust the test cases according to the chip performance indicators to obtain the adjusted test cases. The processing unit is used to process chip verification tasks based on the adjusted test cases.

[0084] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0085] In this embodiment, the chip verification device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0086] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0087] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural design for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0088] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0089] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the chip verification method of the embodiments of the present invention.

[0090] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present invention.

[0091] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the chip verification method shown in the above embodiments is implemented.

[0092] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0093] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A chip verification method, characterized in that, The method includes: Obtain the chip verification task and determine the target hardware corresponding to the chip verification task in the hardware resource pool; The chip verification task is assigned to the target hardware, and chip verification information is obtained based on the test cases corresponding to the target hardware and the chip verification task. Generate encrypted information corresponding to the chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, the chip verification information, and preset audit rules; Generate user permissions for multiple users, wherein the user permissions are used to access the preset data corresponding to the chip verification task, the chip verification information, the encrypted information, and the compliance report.

2. The method according to claim 1, characterized in that, The step of assigning the chip verification task to the target hardware includes: Obtain the task type and resource usage ratio of the chip verification task; The task priority of the chip verification task is determined based on the task type and the resource consumption ratio. Determine the time slice occupied by the chip verification task in the target hardware; The chip verification task is assigned to the target hardware based on the task priority and the time slice.

3. The method according to claim 1, characterized in that, The step of determining the target hardware corresponding to the chip verification task in the hardware resource pool includes: Determine the node identifier and node resources of the computing nodes; Determine the first resource requirements for the chip verification task; The computing nodes that are marked with a preset label and whose resources meet the first resource requirement are selected as candidate computing nodes. Based on the node resources of the candidate computing nodes, determine the utilization difference among multiple hardware components in the candidate computing nodes; Candidate computing nodes whose utilization difference is less than a first preset threshold are used as intermediate computing nodes; The mapping relationship between the chip verification task and the hardware is determined, and the target computing node is determined in the intermediate computing node according to the mapping relationship, wherein the target computing node contains the target hardware.

4. The method according to claim 3, characterized in that, After determining the target hardware corresponding to the chip verification task in the hardware resource pool, the method further includes: Obtain the node load of the target computing node; If the node load exceeds a second preset threshold, a snapshot of the target computing node is created. Determine a replacement computing node among the computing nodes other than the target computing node; Based on the snapshot, the chip verification task is migrated to the replacement computing node; Determine the second resource requirements for the chip verification task; Chip verification tasks whose second resource requirements are less than the third preset threshold are merged to obtain merged tasks, and the merged tasks are scheduled to the computing node.

5. The method according to claim 1, characterized in that, Before determining the target hardware corresponding to the chip verification task in the hardware resource pool, the method further includes: Acquire historical task data and create a resource demand prediction model based on the historical task data; Based on the resource demand prediction model and the chip verification task, the predicted resource demand value is determined; Adjust the hardware based on the predicted resource demand to obtain the adjusted hardware. The hardware resource pool is created based on the adjusted hardware.

6. The method according to claim 1, characterized in that, The process of generating encrypted information corresponding to the chip verification information, and generating a compliance report corresponding to the chip verification task based on the encrypted information, the chip verification information, and preset audit rules, includes: Generate the encrypted information corresponding to the chip verification information, and store the preset data corresponding to the chip verification task, the chip verification information, and the encrypted information in a distributed file system; Obtain the timestamps of preset operations during the processing of the chip verification task, and store the timestamps in the distributed file system; A data chain is created based on the data in the distributed file system, and the data chain is synchronized to the blockchain so that the user can access the on-chain data of the data chain through the blockchain; Preset fields are extracted from the on-chain data, and the compliance report is generated according to the preset audit rules and the preset fields. The compliance report is then synchronized to the blockchain.

7. The method according to claim 1, characterized in that, The step of obtaining chip verification information based on the test cases corresponding to the target hardware and the chip verification task includes: Obtain the test cases corresponding to the chip verification task; Obtain the chip performance indicators corresponding to the chip verification task, and adjust the test cases according to the chip performance indicators to obtain the adjusted test cases; The chip verification task is processed based on the adjusted test cases.

8. A chip verification device, characterized in that, The device includes: The hardware determination module is used to acquire chip verification tasks and determine the target hardware corresponding to the chip verification tasks from the hardware resource pool. The testing module is used to assign the chip verification task to the target hardware and obtain chip verification information based on the test cases corresponding to the target hardware and the chip verification task. The report generation module is used to generate encrypted information corresponding to the chip verification information, and generate a compliance report corresponding to the chip verification task based on the encrypted information, the chip verification information and preset audit rules. The permission generation module is used to generate user permissions for multiple users, wherein the user permissions are used to access the preset data corresponding to the chip verification task, the chip verification information, the encrypted information, and the compliance report.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the chip verification method according to any one of claims 1 to 7.

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